From: Peng Fan <peng.fan@nxp.com> To: "sboyd@kernel.org" <sboyd@kernel.org>, "shawnguo@kernel.org" <shawnguo@kernel.org>, "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>, "festevam@gmail.com" <festevam@gmail.com>, Abel Vesa <abel.vesa@nxp.com>, Leonard Crestez <leonard.crestez@nxp.com> Cc: "kernel@pengutronix.de" <kernel@pengutronix.de>, dl-linux-imx <linux-imx@nxp.com>, Aisheng Dong <aisheng.dong@nxp.com>, "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Anson Huang <anson.huang@nxp.com>, Jacky Bai <ping.bai@nxp.com>, "l.stach@pengutronix.de" <l.stach@pengutronix.de> Subject: RE: [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Date: Wed, 19 Feb 2020 10:20:17 +0000 [thread overview] Message-ID: <AM0PR04MB4481BEE793A6FEE5588ACEAC88100@AM0PR04MB4481.eurprd04.prod.outlook.com> (raw) In-Reply-To: <1582106022-20926-2-git-send-email-peng.fan@nxp.com> > Subject: [PATCH V3 1/4] clk: imx: composite-8m: add > imx8m_clk_hw_composite_core Sorry, some patches are wrongly sent out, please ignore this thread. I'll use PATCH RESEND to resend and drop unneed patches. Thanks, Peng. > > From: Peng Fan <peng.fan@nxp.com> > > There are several clock slices, current composite code only support bus/ip > clock slices, it could not support core slice. > > So introduce a new API imx8m_clk_hw_composite_core to support core slice. > To core slice, post divider with 3 bits width and no pre divider. Other fields are > same as bus/ip slices. > > Add a flag IMX_COMPOSITE_CORE for the usecase. > > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++---- > drivers/clk/imx/clk.h | 13 +++++++++++-- > 2 files changed, 25 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/imx/clk-composite-8m.c > b/drivers/clk/imx/clk-composite-8m.c > index e0f25983e80f..4174506e8bdd 100644 > --- a/drivers/clk/imx/clk-composite-8m.c > +++ b/drivers/clk/imx/clk-composite-8m.c > @@ -15,6 +15,7 @@ > #define PCG_PREDIV_MAX 8 > > #define PCG_DIV_SHIFT 0 > +#define PCG_CORE_DIV_WIDTH 3 > #define PCG_DIV_WIDTH 6 > #define PCG_DIV_MAX 64 > > @@ -126,6 +127,7 @@ static const struct clk_ops > imx8m_clk_composite_divider_ops = { struct clk_hw > *imx8m_clk_hw_composite_flags(const char *name, > const char * const *parent_names, > int num_parents, void __iomem *reg, > + u32 composite_flags, > unsigned long flags) > { > struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; @@ -133,6 +135,7 > @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > struct clk_divider *div = NULL; > struct clk_gate *gate = NULL; > struct clk_mux *mux = NULL; > + const struct clk_ops *divider_ops; > > mux = kzalloc(sizeof(*mux), GFP_KERNEL); > if (!mux) > @@ -149,8 +152,16 @@ struct clk_hw > *imx8m_clk_hw_composite_flags(const char *name, > > div_hw = &div->hw; > div->reg = reg; > - div->shift = PCG_PREDIV_SHIFT; > - div->width = PCG_PREDIV_WIDTH; > + if (composite_flags & IMX_COMPOSITE_CORE) { > + div->shift = PCG_DIV_SHIFT; > + div->width = PCG_CORE_DIV_WIDTH; > + divider_ops = &clk_divider_ops; > + } else { > + div->shift = PCG_PREDIV_SHIFT; > + div->width = PCG_PREDIV_WIDTH; > + divider_ops = &imx8m_clk_composite_divider_ops; > + } > + > div->lock = &imx_ccm_lock; > div->flags = CLK_DIVIDER_ROUND_CLOSEST; > > @@ -164,8 +175,7 @@ struct clk_hw > *imx8m_clk_hw_composite_flags(const char *name, > > hw = clk_hw_register_composite(NULL, name, parent_names, > num_parents, > mux_hw, &clk_mux_ops, div_hw, > - &imx8m_clk_composite_divider_ops, > - gate_hw, &clk_gate_ops, flags); > + divider_ops, gate_hw, &clk_gate_ops, flags); > if (IS_ERR(hw)) > goto fail; > > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index > b05213b91dcf..f074dd8ec42e 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, > const char *parent_name, > struct clk *div, struct clk *mux, struct clk *pll, > struct clk *step); > > +#define IMX_COMPOSITE_CORE BIT(0) > + > struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > const char * const *parent_names, > int num_parents, > void __iomem *reg, > + u32 composite_flags, > unsigned long flags); > > +#define imx8m_clk_hw_composite_core(name, parent_names, reg) \ > + imx8m_clk_hw_composite_flags(name, parent_names, \ > + ARRAY_SIZE(parent_names), reg, \ > + IMX_COMPOSITE_CORE, \ > + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) > + > #define imx8m_clk_composite_flags(name, parent_names, num_parents, > reg, \ > flags) \ > to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ > - num_parents, reg, flags)) > + num_parents, reg, 0, flags)) > > #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ > imx8m_clk_hw_composite_flags(name, parent_names, \ > - ARRAY_SIZE(parent_names), reg, \ > + ARRAY_SIZE(parent_names), reg, 0, \ > flags | CLK_SET_RATE_NO_REPARENT | > CLK_OPS_PARENT_ENABLE) > > #define __imx8m_clk_composite(name, parent_names, reg, flags) \ > -- > 2.16.4
WARNING: multiple messages have this Message-ID (diff)
From: Peng Fan <peng.fan@nxp.com> To: "sboyd@kernel.org" <sboyd@kernel.org>, "shawnguo@kernel.org" <shawnguo@kernel.org>, "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>, "festevam@gmail.com" <festevam@gmail.com>, Abel Vesa <abel.vesa@nxp.com>, Leonard Crestez <leonard.crestez@nxp.com> Cc: Aisheng Dong <aisheng.dong@nxp.com>, Jacky Bai <ping.bai@nxp.com>, Anson Huang <anson.huang@nxp.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, dl-linux-imx <linux-imx@nxp.com>, "kernel@pengutronix.de" <kernel@pengutronix.de>, "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "l.stach@pengutronix.de" <l.stach@pengutronix.de> Subject: RE: [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Date: Wed, 19 Feb 2020 10:20:17 +0000 [thread overview] Message-ID: <AM0PR04MB4481BEE793A6FEE5588ACEAC88100@AM0PR04MB4481.eurprd04.prod.outlook.com> (raw) In-Reply-To: <1582106022-20926-2-git-send-email-peng.fan@nxp.com> > Subject: [PATCH V3 1/4] clk: imx: composite-8m: add > imx8m_clk_hw_composite_core Sorry, some patches are wrongly sent out, please ignore this thread. I'll use PATCH RESEND to resend and drop unneed patches. Thanks, Peng. > > From: Peng Fan <peng.fan@nxp.com> > > There are several clock slices, current composite code only support bus/ip > clock slices, it could not support core slice. > > So introduce a new API imx8m_clk_hw_composite_core to support core slice. > To core slice, post divider with 3 bits width and no pre divider. Other fields are > same as bus/ip slices. > > Add a flag IMX_COMPOSITE_CORE for the usecase. > > Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/clk/imx/clk-composite-8m.c | 18 ++++++++++++++---- > drivers/clk/imx/clk.h | 13 +++++++++++-- > 2 files changed, 25 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/imx/clk-composite-8m.c > b/drivers/clk/imx/clk-composite-8m.c > index e0f25983e80f..4174506e8bdd 100644 > --- a/drivers/clk/imx/clk-composite-8m.c > +++ b/drivers/clk/imx/clk-composite-8m.c > @@ -15,6 +15,7 @@ > #define PCG_PREDIV_MAX 8 > > #define PCG_DIV_SHIFT 0 > +#define PCG_CORE_DIV_WIDTH 3 > #define PCG_DIV_WIDTH 6 > #define PCG_DIV_MAX 64 > > @@ -126,6 +127,7 @@ static const struct clk_ops > imx8m_clk_composite_divider_ops = { struct clk_hw > *imx8m_clk_hw_composite_flags(const char *name, > const char * const *parent_names, > int num_parents, void __iomem *reg, > + u32 composite_flags, > unsigned long flags) > { > struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw; @@ -133,6 +135,7 > @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > struct clk_divider *div = NULL; > struct clk_gate *gate = NULL; > struct clk_mux *mux = NULL; > + const struct clk_ops *divider_ops; > > mux = kzalloc(sizeof(*mux), GFP_KERNEL); > if (!mux) > @@ -149,8 +152,16 @@ struct clk_hw > *imx8m_clk_hw_composite_flags(const char *name, > > div_hw = &div->hw; > div->reg = reg; > - div->shift = PCG_PREDIV_SHIFT; > - div->width = PCG_PREDIV_WIDTH; > + if (composite_flags & IMX_COMPOSITE_CORE) { > + div->shift = PCG_DIV_SHIFT; > + div->width = PCG_CORE_DIV_WIDTH; > + divider_ops = &clk_divider_ops; > + } else { > + div->shift = PCG_PREDIV_SHIFT; > + div->width = PCG_PREDIV_WIDTH; > + divider_ops = &imx8m_clk_composite_divider_ops; > + } > + > div->lock = &imx_ccm_lock; > div->flags = CLK_DIVIDER_ROUND_CLOSEST; > > @@ -164,8 +175,7 @@ struct clk_hw > *imx8m_clk_hw_composite_flags(const char *name, > > hw = clk_hw_register_composite(NULL, name, parent_names, > num_parents, > mux_hw, &clk_mux_ops, div_hw, > - &imx8m_clk_composite_divider_ops, > - gate_hw, &clk_gate_ops, flags); > + divider_ops, gate_hw, &clk_gate_ops, flags); > if (IS_ERR(hw)) > goto fail; > > diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index > b05213b91dcf..f074dd8ec42e 100644 > --- a/drivers/clk/imx/clk.h > +++ b/drivers/clk/imx/clk.h > @@ -477,20 +477,29 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, > const char *parent_name, > struct clk *div, struct clk *mux, struct clk *pll, > struct clk *step); > > +#define IMX_COMPOSITE_CORE BIT(0) > + > struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > const char * const *parent_names, > int num_parents, > void __iomem *reg, > + u32 composite_flags, > unsigned long flags); > > +#define imx8m_clk_hw_composite_core(name, parent_names, reg) \ > + imx8m_clk_hw_composite_flags(name, parent_names, \ > + ARRAY_SIZE(parent_names), reg, \ > + IMX_COMPOSITE_CORE, \ > + CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) > + > #define imx8m_clk_composite_flags(name, parent_names, num_parents, > reg, \ > flags) \ > to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \ > - num_parents, reg, flags)) > + num_parents, reg, 0, flags)) > > #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \ > imx8m_clk_hw_composite_flags(name, parent_names, \ > - ARRAY_SIZE(parent_names), reg, \ > + ARRAY_SIZE(parent_names), reg, 0, \ > flags | CLK_SET_RATE_NO_REPARENT | > CLK_OPS_PARENT_ENABLE) > > #define __imx8m_clk_composite(name, parent_names, reg, flags) \ > -- > 2.16.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-02-19 10:20 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-19 9:53 [PATCH v3 0/4] clk: imx: imx8m: fix a53 cpu clock peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 10:20 ` Peng Fan [this message] 2020-02-19 10:20 ` Peng Fan 2020-02-19 9:53 ` [PATCH v3 1/4] clk: imx: imx8mq: fix a53 cpu clock peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH v3 2/4] clk: imx: imx8mm: " peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH V3 2/4] clk: imx: imx8mq: use imx8m_clk_hw_composite_core peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH V3 3/4] clk: imx: imx8mm: " peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH v3 3/4] clk: imx: imx8mn: fix a53 cpu clock peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH V3 4/4] clk: imx: imx8mn: use imx8m_clk_hw_composite_core peng.fan 2020-02-19 9:53 ` peng.fan 2020-02-19 9:53 ` [PATCH v3 4/4] clk: imx: imx8mp: fix a53 cpu clock peng.fan 2020-02-19 9:53 ` peng.fan -- strict thread matches above, loose matches on Subject: below -- 2020-01-16 2:15 [PATCH V3 0/4] clk: imx: imx8m: introduce imx8m_clk_hw_composite_core Peng Fan 2020-01-16 2:15 ` [PATCH V3 1/4] clk: imx: composite-8m: add imx8m_clk_hw_composite_core Peng Fan 2020-01-16 2:15 ` Peng Fan 2020-01-20 13:41 ` Leonard Crestez 2020-01-20 13:41 ` Leonard Crestez
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