From: Peng Fan <peng.fan@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH V2 50/51] imx: add dtsi for i.MX8MN
Date: Wed, 10 Jul 2019 08:50:49 +0000 [thread overview]
Message-ID: <AM0PR04MB4481EB3CEBDD5B9B66BAAFBC88F00@AM0PR04MB4481.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20190710104404.0a6ede9f@jawa>
> Subject: Re: [U-Boot] [PATCH V2 50/51] imx: add dtsi for i.MX8MN
>
> Hi Peng,
>
> > > Subject: Re: [U-Boot] [PATCH V2 50/51] imx: add dtsi for i.MX8MN
> > >
> > > Hi Peng,
> > >
> > > > Add dtsi for i.MX8MN
> > >
> > > Please add SHA ID for the exact commit from which you ported DTS
> > > files.
> >
> > The patchset has not been merged into Shawn's tree, I took
> > from Linux patchwork.
>
> So maybe it is in linux-next?
It will first be merged in Shawn's tree, then it will show in Linux-next.
I will check Linux-next when I post v3.
Thanks,
Peng.
>
> My point is that there are real bug introduced by DTS porting (as
> found yesterday for i.MX53). The SHA1 will provide the reference.
>
> >
> > Regards,
> > Peng.
> >
> > >
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > > arch/arm/dts/imx8mn-pinfunc.h | 646
> > > > ++++++++++++++++++++++++++++ arch/arm/dts/imx8mn.dtsi
> > > > | 712 +++++++++++++++++++++++++++++++
> > > > include/dt-bindings/clock/imx8mn-clock.h | 215 ++++++++++ 3 files
> > > > changed, 1573 insertions(+) create mode 100644
> > > > arch/arm/dts/imx8mn-pinfunc.h create mode 100644
> > > > arch/arm/dts/imx8mn.dtsi create mode 100644
> > > > include/dt-bindings/clock/imx8mn-clock.h
> > > >
> > > > diff --git a/arch/arm/dts/imx8mn-pinfunc.h
> > > > b/arch/arm/dts/imx8mn-pinfunc.h new file mode 100644
> > > > index 0000000000..3de8168cf8
> > > > --- /dev/null
> > > > +++ b/arch/arm/dts/imx8mn-pinfunc.h
> > > > @@ -0,0 +1,646 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0+ */
> > > > +/*
> > > > + * Copyright 2019 NXP
> > > > + *
> > > > + */
> > > > +
> > > > +#ifndef __DTS_IMX8MN_PINFUNC_H
> > > > +#define __DTS_IMX8MN_PINFUNC_H
> > > > +
> > > > +/*
> > > > + * The pin function ID is a tuple of
> > > > + * <mux_reg conf_reg input_reg mux_mode input_val>
> > > > + */
> > > > +#define
> > > > MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2
> > > > 0x0020 0x025C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL
> > > > 0x0020 0x025C 0x055C 0x1 0x3 +#define
> > > > MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3
> > > > 0x0024 0x0260 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA
> > > > 0x0024 0x0260 0x056C 0x1 0x3 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0
> > > > 0x0028 0x0290 0x0000 0x0 0x0 +#define
> > > >
> > >
> MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_RO
> O
> > > T
> > > > 0x0028 0x0290 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> > > > 0x0028 0x0290 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
> > > > 0x0028 0x0290 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1
> > > > 0x002C 0x0294 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT
> > > > 0x002C 0x0294 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
> > > > 0x002C 0x0294 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
> > > > 0x002C 0x0294 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2
> > > > 0x0030 0x0298 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> > > > 0x0030 0x0298 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
> > > > 0x0030 0x0298 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3
> > > > 0x0034 0x029C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
> > > > 0x0034 0x029C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
> > > > 0x0034 0x029C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
> > > > 0x0034 0x029C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4
> > > > 0x0038 0x02A0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> > > > 0x0038 0x02A0 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
> > > > 0x0038 0x02A0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
> > > > 0x0038 0x02A0 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5
> > > > 0x003C 0x02A4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO05_M4_NMI
> > > > 0x003C 0x02A4 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY
> > > > 0x003C 0x02A4 0x04BC 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT
> > > > 0x003C 0x02A4 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6
> > > > 0x0040 0x02A8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC
> > > > 0x0040 0x02A8 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B
> > > > 0x0040 0x02A8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3
> > > > 0x0040 0x02A8 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7
> > > > 0x0044 0x02AC 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO
> > > > 0x0044 0x02AC 0x04C0 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP
> > > > 0x0044 0x02AC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4
> > > > 0x0044 0x02AC 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8
> > > > 0x0048 0x02B0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
> > > > 0x0048 0x02B0 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT
> > > > 0x0048 0x02B0 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B
> > > > 0x0048 0x02B0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT
> > > > 0x0048 0x02B0 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9
> > > > 0x004C 0x02B4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> > > > 0x004C 0x02B4 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT
> > > > 0x004C 0x02B4 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B
> > > > 0x004C 0x02B4 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0
> > > > 0x004C 0x02B4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP
> > > > 0x004C 0x02B4 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10
> > > > 0x0050 0x02B8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID
> > > > 0x0050 0x02B8 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT
> > > > 0x0050 0x02B8 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11
> > > > 0x0054 0x02BC 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT
> > > > 0x0054 0x02BC 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT
> > > > 0x0054 0x02BC 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY
> > > > 0x0054 0x02BC 0x04BC 0x5 0x1 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0
> > > > 0x0054 0x02BC 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12
> > > > 0x0058 0x02C0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR
> > > > 0x0058 0x02C0 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1
> > > > 0x0058 0x02C0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1
> > > > 0x0058 0x02C0 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13
> > > > 0x005C 0x02C4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC
> > > > 0x005C 0x02C4 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT
> > > > 0x005C 0x02C4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2
> > > > 0x005C 0x02C4 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14
> > > > 0x0060 0x02C8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B
> > > > 0x0060 0x02C8 0x0598 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT
> > > > 0x0060 0x02C8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
> > > > 0x0060 0x02C8 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15
> > > > 0x0064 0x02CC 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP
> > > > 0x0064 0x02CC 0x05B8 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT
> > > > 0x0064 0x02CC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
> > > > 0x0064 0x02CC 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDC_ENET1_MDC
> > > > 0x0068 0x02D0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0
> > > > 0x0068 0x02D0 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3
> > > > 0x0068 0x02D0 0x0540 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT
> > > > 0x0068 0x02D0 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16
> > > > 0x0068 0x02D0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE
> > > > 0x0068 0x02D0 0x059C 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO
> > > > 0x006C 0x02D4 0x04C0 0x0 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC
> > > > 0x006C 0x02D4 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2
> > > > 0x006C 0x02D4 0x053C 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN
> > > > 0x006C 0x02D4 0x05CC 0x4 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17
> > > > 0x006C 0x02D4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5
> > > > 0x006C 0x02D4 0x0550 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> > > > 0x0070 0x02D8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK
> > > > 0x0070 0x02D8 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1
> > > > 0x0070 0x02D8 0x0538 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK
> > > > 0x0070 0x02D8 0x0568 0x4 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18
> > > > 0x0070 0x02D8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6
> > > > 0x0070 0x02D8 0x0584 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> > > > 0x0074 0x02DC 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK
> > > > 0x0074 0x02DC 0x05A4 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT
> > > > 0x0074 0x02DC 0x05A4 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0
> > > > 0x0074 0x02DC 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3
> > > > 0x0074 0x02DC 0x0540 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19
> > > > 0x0074 0x02DC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7
> > > > 0x0074 0x02DC 0x054C 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> > > > 0x0078 0x02E0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC
> > > > 0x0078 0x02E0 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2
> > > > 0x0078 0x02E0 0x053C 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20
> > > > 0x0078 0x02E0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B
> > > > 0x0078 0x02E0 0x0598 0x6 0x3 +#define
> > > > MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> > > > 0x007C 0x02E4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK
> > > > 0x007C 0x02E4 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1
> > > > 0x007C 0x02E4 0x0538 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21
> > > > 0x007C 0x02E4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TD0_USDHC3_WP
> > > > 0x007C 0x02E4 0x05B8 0x6 0x3 +#define
> > > > MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> > > > 0x0080 0x02E8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK
> > > > 0x0080 0x02E8 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22
> > > > 0x0080 0x02E8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0
> > > > 0x0080 0x02E8 0x05B4 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> > > > 0x0084 0x02EC 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER
> > > > 0x0084 0x02EC 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0
> > > > 0x0084 0x02EC 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23
> > > > 0x0084 0x02EC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1
> > > > 0x0084 0x02EC 0x05B0 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> > > > 0x0088 0x02F0 0x0574 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC
> > > > 0x0088 0x02F0 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3
> > > > 0x0088 0x02F0 0x0540 0x3 0x3 +#define
> > > > MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24
> > > > 0x0088 0x02F0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2
> > > > 0x0088 0x02F0 0x05E4 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> > > > 0x008C 0x02F4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER
> > > > 0x008C 0x02F4 0x05C8 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK
> > > > 0x008C 0x02F4 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2
> > > > 0x008C 0x02F4 0x053C 0x3 0x3 +#define
> > > > MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25
> > > > 0x008C 0x02F4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3
> > > > 0x008C 0x02F4 0x05E0 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> > > > 0x0090 0x02F8 0x057C 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0
> > > > 0x0090 0x02F8 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1
> > > > 0x0090 0x02F8 0x0538 0x3 0x3 +#define
> > > > MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26
> > > > 0x0090 0x02F8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4
> > > > 0x0090 0x02F8 0x0558 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> > > > 0x0094 0x02FC 0x0554 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC
> > > > 0x0094 0x02FC 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0
> > > > 0x0094 0x02FC 0x0534 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27
> > > > 0x0094 0x02FC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B
> > > > 0x0094 0x02FC 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> > > > 0x0098 0x0300 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK
> > > > 0x0098 0x0300 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD2_PDM_CLK
> > > > 0x0098 0x0300 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28
> > > > 0x0098 0x0300 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK
> > > > 0x0098 0x0300 0x05A0 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> > > > 0x009C 0x0304 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK
> > > > 0x009C 0x0304 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN
> > > > 0x009C 0x0304 0x05CC 0x3 0x5 +#define
> > > > MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29
> > > > 0x009C 0x0304 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD
> > > > 0x009C 0x0304 0x05DC 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK
> > > > 0x00A0 0x0308 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_CLK_ENET1_MDC
> > > > 0x00A0 0x0308 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX
> > > > 0x00A0 0x0308 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX
> > > > 0x00A0 0x0308 0x04F4 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0
> > > > 0x00A0 0x0308 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD
> > > > 0x00A4 0x030C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO
> > > > 0x00A4 0x030C 0x04C0 0x1 0x3 +#define
> > > > MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX
> > > > 0x00A4 0x030C 0x04F4 0x4 0x5 +#define
> > > > MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX
> > > > 0x00A4 0x030C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1
> > > > 0x00A4 0x030C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0
> > > > 0x00A8 0x0310 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1
> > > > 0x00A8 0x0310 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B
> > > > 0x00A8 0x0310 0x04F0 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B
> > > > 0x00A8 0x0310 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2
> > > > 0x00A8 0x0310 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1
> > > > 0x00AC 0x0314 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0
> > > > 0x00AC 0x0314 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B
> > > > 0x00AC 0x0314 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B
> > > > 0x00AC 0x0314 0x04F0 0x4 0x5 +#define
> > > > MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3
> > > > 0x00AC 0x0314 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2
> > > > 0x00B0 0x0318 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0
> > > > 0x00B0 0x0318 0x057C 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX
> > > > 0x00B0 0x0318 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX
> > > > 0x00B0 0x0318 0x04FC 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4
> > > > 0x00B0 0x0318 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3
> > > > 0x00B4 0x031C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1
> > > > 0x00B4 0x031C 0x0554 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX
> > > > 0x00B4 0x031C 0x04FC 0x4 0x5 +#define
> > > > MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX
> > > > 0x00B4 0x031C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5
> > > > 0x00B4 0x031C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4
> > > > 0x00B8 0x0320 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL
> > > > 0x00B8 0x0320 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL
> > > > 0x00B8 0x0320 0x055C 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B
> > > > 0x00B8 0x0320 0x04F8 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B
> > > > 0x00B8 0x0320 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6
> > > > 0x00B8 0x0320 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5
> > > > 0x00BC 0x0324 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER
> > > > 0x00BC 0x0324 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA
> > > > 0x00BC 0x0324 0x056C 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B
> > > > 0x00BC 0x0324 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B
> > > > 0x00BC 0x0324 0x04F8 0x4 0x5 +#define
> > > > MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7
> > > > 0x00BC 0x0324 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6
> > > > 0x00C0 0x0328 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL
> > > > 0x00C0 0x0328 0x0574 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL
> > > > 0x00C0 0x0328 0x05D0 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX
> > > > 0x00C0 0x0328 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX
> > > > 0x00C0 0x0328 0x0504 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8
> > > > 0x00C0 0x0328 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7
> > > > 0x00C4 0x032C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER
> > > > 0x00C4 0x032C 0x05C8 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA
> > > > 0x00C4 0x032C 0x0560 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX
> > > > 0x00C4 0x032C 0x0504 0x4 0x5 +#define
> > > > MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX
> > > > 0x00C4 0x032C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9
> > > > 0x00C4 0x032C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
> > > > 0x00C8 0x0330 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK
> > > > 0x00C8 0x0330 0x05A4 0x1 0x1 +#define
> > > >
> MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT
> > > > 0x00C8 0x0330 0x05A4 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL
> > > > 0x00C8 0x0330 0x0588 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B
> > > > 0x00C8 0x0330 0x0500 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B
> > > > 0x00C8 0x0330 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10
> > > > 0x00C8 0x0330 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE
> > > > 0x00CC 0x0334 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA
> > > > 0x00CC 0x0334 0x05BC 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B
> > > > 0x00CC 0x0334 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B
> > > > 0x00CC 0x0334 0x0500 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11
> > > > 0x00CC 0x0334 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B
> > > > 0x00D0 0x0338 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12
> > > > 0x00D0 0x0338 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK
> > > > 0x00D0 0x0338 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK
> > > > 0x00D4 0x033C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC
> > > > 0x00D4 0x033C 0x04E4 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK
> > > > 0x00D4 0x033C 0x0580 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX
> > > > 0x00D4 0x033C 0x050C 0x3 0x4 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX
> > > > 0x00D4 0x033C 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK
> > > > 0x00D4 0x033C 0x0594 0x4 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13
> > > > 0x00D4 0x033C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0
> > > > 0x00D4 0x033C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD
> > > > 0x00D8 0x0340 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK
> > > > 0x00D8 0x0340 0x04D0 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI
> > > > 0x00D8 0x0340 0x0590 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX
> > > > 0x00D8 0x0340 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX
> > > > 0x00D8 0x0340 0x050C 0x3 0x5 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_PDM_CLK
> > > > 0x00D8 0x0340 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14
> > > > 0x00D8 0x0340 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1
> > > > 0x00D8 0x0340 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0
> > > > 0x00DC 0x0344 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0
> > > > 0x00DC 0x0344 0x04D4 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA
> > > > 0x00DC 0x0344 0x058C 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX
> > > > 0x00DC 0x0344 0x04FC 0x3 0x6 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX
> > > > 0x00DC 0x0344 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0
> > > > 0x00DC 0x0344 0x0534 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15
> > > > 0x00DC 0x0344 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2
> > > > 0x00DC 0x0344 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1
> > > > 0x00E0 0x0348 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC
> > > > 0x00E0 0x0348 0x04EC 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL
> > > > 0x00E0 0x0348 0x05D4 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX
> > > > 0x00E0 0x0348 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX
> > > > 0x00E0 0x0348 0x04FC 0x3 0x7 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1
> > > > 0x00E0 0x0348 0x0538 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16
> > > > 0x00E0 0x0348 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT
> > > > 0x00E0 0x0348 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2
> > > > 0x00E4 0x034C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK
> > > > 0x00E4 0x034C 0x04E8 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0
> > > > 0x00E4 0x034C 0x0570 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT
> > > > 0x00E4 0x034C 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2
> > > > 0x00E4 0x034C 0x053C 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17
> > > > 0x00E4 0x034C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP
> > > > 0x00E4 0x034C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3
> > > > 0x00E8 0x0350 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0
> > > > 0x00E8 0x0350 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO
> > > > 0x00E8 0x0350 0x0578 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN
> > > > 0x00E8 0x0350 0x05CC 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3
> > > > 0x00E8 0x0350 0x0540 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18
> > > > 0x00E8 0x0350 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET
> > > > 0x00E8 0x0350 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B
> > > > 0x00EC 0x0354 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19
> > > > 0x00EC 0x0354 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET
> > > > 0x00EC 0x0354 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_WP_USDHC2_WP
> > > > 0x00F0 0x0358 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_WP_GPIO2_IO20
> > > > 0x00F0 0x0358 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI
> > > > 0x00F0 0x0358 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE
> > > > 0x00F4 0x035C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK
> > > > 0x00F4 0x035C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0
> > > > 0x00F4 0x035C 0x0534 0x3 0x3 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX
> > > > 0x00F4 0x035C 0x0504 0x4 0x6 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX
> > > > 0x00F4 0x035C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0
> > > > 0x00F4 0x035C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK
> > > > 0x00F4 0x035C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B
> > > > 0x00F8 0x0360 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> > > > 0x00F8 0x0360 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1
> > > > 0x00F8 0x0360 0x0538 0x3 0x5 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX
> > > > 0x00F8 0x0360 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX
> > > > 0x00F8 0x0360 0x0504 0x4 0x7 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1
> > > > 0x00F8 0x0360 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL
> > > > 0x00F8 0x0360 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B
> > > > 0x00FC 0x0364 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B
> > > > 0x00FC 0x0364 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE
> > > > 0x00FC 0x0364 0x059C 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0
> > > > 0x00FC 0x0364 0x0534 0x3 0x4 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL
> > > > 0x00FC 0x0364 0x05D4 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2
> > > > 0x00FC 0x0364 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0
> > > > 0x00FC 0x0364 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B
> > > > 0x0100 0x0368 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B
> > > > 0x0100 0x0368 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5
> > > > 0x0100 0x0368 0x0550 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1
> > > > 0x0100 0x0368 0x0538 0x3 0x6 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA
> > > > 0x0100 0x0368 0x058C 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3
> > > > 0x0100 0x0368 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1
> > > > 0x0100 0x0368 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B
> > > > 0x0104 0x036C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B
> > > > 0x0104 0x036C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6
> > > > 0x0104 0x036C 0x0584 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2
> > > > 0x0104 0x036C 0x053C 0x3 0x5 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA
> > > > 0x0104 0x036C 0x05BC 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4
> > > > 0x0104 0x036C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2
> > > > 0x0104 0x036C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE
> > > > 0x0108 0x0370 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK
> > > > 0x0108 0x0370 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7
> > > > 0x0108 0x0370 0x054C 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5
> > > > 0x0108 0x0370 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3
> > > > 0x0108 0x0370 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00
> > > > 0x010C 0x0374 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0
> > > > 0x010C 0x0374 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2
> > > > 0x010C 0x0374 0x053C 0x3 0x6 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX
> > > > 0x010C 0x0374 0x050C 0x4 0x6 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX
> > > > 0x010C 0x0374 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6
> > > > 0x010C 0x0374 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4
> > > > 0x010C 0x0374 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01
> > > > 0x0110 0x0378 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1
> > > > 0x0110 0x0378 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3
> > > > 0x0110 0x0378 0x0540 0x3 0x5 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX
> > > > 0x0110 0x0378 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX
> > > > 0x0110 0x0378 0x050C 0x4 0x7 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7
> > > > 0x0110 0x0378 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5
> > > > 0x0110 0x0378 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02
> > > > 0x0114 0x037C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2
> > > > 0x0114 0x037C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B
> > > > 0x0114 0x037C 0x0598 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA
> > > > 0x0114 0x037C 0x058C 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8
> > > > 0x0114 0x037C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6
> > > > 0x0114 0x037C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03
> > > > 0x0118 0x0380 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3
> > > > 0x0118 0x0380 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP
> > > > 0x0118 0x0380 0x05B8 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9
> > > > 0x0118 0x0380 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7
> > > > 0x0118 0x0380 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04
> > > > 0x011C 0x0384 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0
> > > > 0x011C 0x0384 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0
> > > > 0x011C 0x0384 0x05B4 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10
> > > > 0x011C 0x0384 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8
> > > > 0x011C 0x0384 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05
> > > > 0x0120 0x0388 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1
> > > > 0x0120 0x0388 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1
> > > > 0x0120 0x0388 0x05B0 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11
> > > > 0x0120 0x0388 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9
> > > > 0x0120 0x0388 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06
> > > > 0x0124 0x038C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2
> > > > 0x0124 0x038C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2
> > > > 0x0124 0x038C 0x05E4 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12
> > > > 0x0124 0x038C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10
> > > > 0x0124 0x038C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07
> > > > 0x0128 0x0390 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3
> > > > 0x0128 0x0390 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3
> > > > 0x0128 0x0390 0x05E0 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13
> > > > 0x0128 0x0390 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11
> > > > 0x0128 0x0390 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS
> > > > 0x012C 0x0394 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS
> > > > 0x012C 0x0394 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DQS_PDM_CLK
> > > > 0x012C 0x0394 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DQS_I2C3_SCL
> > > > 0x012C 0x0394 0x0588 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14
> > > > 0x012C 0x0394 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12
> > > > 0x012C 0x0394 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B
> > > > 0x0130 0x0398 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS
> > > > 0x0130 0x0398 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4
> > > > 0x0130 0x0398 0x0558 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1
> > > > 0x0130 0x0398 0x0538 0x3 0x7 +#define
> > > > MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15
> > > > 0x0130 0x0398 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13
> > > > 0x0130 0x0398 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B
> > > > 0x0134 0x039C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B
> > > > 0x0134 0x039C 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3
> > > > 0x0134 0x039C 0x0540 0x3 0x6 +#define
> > > > MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL
> > > > 0x0134 0x039C 0x0588 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16
> > > > 0x0134 0x039C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14
> > > > 0x0134 0x039C 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B
> > > > 0x0138 0x03A0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK
> > > > 0x0138 0x03A0 0x05A0 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA
> > > > 0x0138 0x03A0 0x05BC 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17
> > > > 0x0138 0x03A0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15
> > > > 0x0138 0x03A0 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B
> > > > 0x013C 0x03A4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD
> > > > 0x013C 0x03A4 0x05DC 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA
> > > > 0x013C 0x03A4 0x058C 0x4 0x4 +#define
> > > > MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18
> > > > 0x013C 0x03A4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO
> > > > 0x013C 0x03A4 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC
> > > > 0x0140 0x03A8 0x04E4 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19
> > > > 0x0140 0x03A8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK
> > > > 0x0144 0x03AC 0x04D0 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXC_PDM_CLK
> > > > 0x0144 0x03AC 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20
> > > > 0x0144 0x03AC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
> > > > 0x0148 0x03B0 0x04D4 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0
> > > > 0x0148 0x03B0 0x0534 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21
> > > > 0x0148 0x03B0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1
> > > > 0x014C 0x03B4 0x04D8 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
> > > > 0x014C 0x03B4 0x04EC 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1
> > > > 0x014C 0x03B4 0x0538 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22
> > > > 0x014C 0x03B4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2
> > > > 0x0150 0x03B8 0x04DC 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
> > > > 0x0150 0x03B8 0x04E8 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2
> > > > 0x0150 0x03B8 0x053C 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23
> > > > 0x0150 0x03B8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3
> > > > 0x0154 0x03BC 0x04E0 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
> > > > 0x0154 0x03BC 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3
> > > > 0x0154 0x03BC 0x0540 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24
> > > > 0x0154 0x03BC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK
> > > > 0x0158 0x03C0 0x0594 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25
> > > > 0x0158 0x03C0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC
> > > > 0x01B0 0x0418 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC
> > > > 0x01B0 0x0418 0x04EC 0x1 0x2 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1
> > > > 0x01B0 0x0418 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1
> > > > 0x01B0 0x0418 0x05AC 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX
> > > > 0x01B0 0x0418 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX
> > > > 0x01B0 0x0418 0x04F4 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21
> > > > 0x01B0 0x0418 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2
> > > > 0x01B0 0x0418 0x053C 0x6 0x7 +#define
> > > > MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK
> > > > 0x01B4 0x041C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK
> > > > 0x01B4 0x041C 0x04E8 0x1 0x2 +#define
> > > > MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX
> > > > 0x01B4 0x041C 0x04F4 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX
> > > > 0x01B4 0x041C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22
> > > > 0x01B4 0x041C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1
> > > > 0x01B4 0x041C 0x0538 0x6 0x8 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
> > > > 0x01B8 0x0420 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0
> > > > 0x01B8 0x0420 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1
> > > > 0x01B8 0x0420 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B
> > > > 0x01B8 0x0420 0x04F0 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B
> > > > 0x01B8 0x0420 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23
> > > > 0x01B8 0x0420 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3
> > > > 0x01B8 0x0420 0x0540 0x6 0x7 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
> > > > 0x01BC 0x0424 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1
> > > > 0x01BC 0x0424 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1
> > > > 0x01BC 0x0424 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B
> > > > 0x01BC 0x0424 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B
> > > > 0x01BC 0x0424 0x04F0 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24
> > > > 0x01BC 0x0424 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2
> > > > 0x01BC 0x0424 0x053C 0x6 0x8 +#define
> > > > MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
> > > > 0x01C0 0x0428 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2
> > > > 0x01C0 0x0428 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25
> > > > 0x01C0 0x0428 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1
> > > > 0x01C0 0x0428 0x0538 0x6 0x9 +#define
> > > > MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
> > > > 0x01C4 0x042C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3
> > > > 0x01C4 0x042C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26
> > > > 0x01C4 0x042C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4
> > > > 0x01C4 0x042C 0x0540 0x6 0x8 +#define
> > > > MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK
> > > > 0x01C8 0x0430 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK
> > > > 0x01C8 0x0430 0x0594 0x1 0x2 +#define
> > > > MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27
> > > > 0x01C8 0x0430 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK
> > > > 0x01C8 0x0430 0x05C0 0x6 0x1 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC
> > > > 0x01CC 0x0434 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1
> > > > 0x01CC 0x0434 0x05F0 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC
> > > > 0x01CC 0x0434 0x04E4 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1
> > > > 0x01CC 0x0434 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN
> > > > 0x01CC 0x0434 0x05CC 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28
> > > > 0x01CC 0x0434 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0
> > > > 0x01CC 0x0434 0x0534 0x6 0x5 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK
> > > > 0x01D0 0x0438 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK
> > > > 0x01D0 0x0438 0x05E8 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK
> > > > 0x01D0 0x0438 0x04D0 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1
> > > > 0x01D0 0x0438 0x05AC 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B
> > > > 0x01D0 0x0438 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B
> > > > 0x01D0 0x0438 0x04F8 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29
> > > > 0x01D0 0x0438 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXC_PDM_CLK
> > > > 0x01D0 0x0438 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0
> > > > 0x01D4 0x043C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1
> > > > 0x01D4 0x043C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0
> > > > 0x01D4 0x043C 0x04D4 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1
> > > > 0x01D4 0x043C 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B
> > > > 0x01D4 0x043C 0x04F8 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B
> > > > 0x01D4 0x043C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30
> > > > 0x01D4 0x043C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1
> > > > 0x01D4 0x043C 0x0538 0x6 0x10 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC
> > > > 0x01D8 0x0440 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2
> > > > 0x01D8 0x0440 0x05EC 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1
> > > > 0x01D8 0x0440 0x04D8 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1
> > > > 0x01D8 0x0440 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX
> > > > 0x01D8 0x0440 0x04FC 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX
> > > > 0x01D8 0x0440 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31
> > > > 0x01D8 0x0440 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3
> > > > 0x01D8 0x0440 0x0540 0x6 0x9 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK
> > > > 0x01DC 0x0444 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2
> > > > 0x01DC 0x0444 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2
> > > > 0x01DC 0x0444 0x04DC 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1
> > > > 0x01DC 0x0444 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX
> > > > 0x01DC 0x0444 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX
> > > > 0x01DC 0x0444 0x04FC 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0
> > > > 0x01DC 0x0444 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2
> > > > 0x01DC 0x0444 0x053C 0x6 0x9 +#define
> > > > MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0
> > > > 0x01E0 0x0448 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3
> > > > 0x01E0 0x0448 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3
> > > > 0x01E0 0x0448 0x04E0 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK
> > > > 0x01E0 0x0448 0x0568 0x4 0x2 +#define
> > > > MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1
> > > > 0x01E0 0x0448 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5
> > > > 0x01E0 0x0448 0x0000 0x6 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK
> > > > 0x01E4 0x044C 0x05C0 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT
> > > > 0x01E4 0x044C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK
> > > > 0x01E4 0x044C 0x0594 0x2 0x3 +#define
> > > > MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT
> > > > 0x01E4 0x044C 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2
> > > > 0x01E4 0x044C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN
> > > > 0x01E4 0x044C 0x05CC 0x6 0x4 +#define
> > > > MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT
> > > > 0x01E8 0x0450 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT
> > > > 0x01E8 0x0450 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3
> > > > 0x01E8 0x0450 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN
> > > > 0x01EC 0x0454 0x05CC 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT
> > > > 0x01EC 0x0454 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4
> > > > 0x01EC 0x0454 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK
> > > > 0x01F0 0x0458 0x0568 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT
> > > > 0x01F0 0x0458 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
> > > > 0x01F0 0x0458 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
> > > > 0x01F4 0x045C 0x05D8 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX
> > > > 0x01F4 0x045C 0x0504 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX
> > > > 0x01F4 0x045C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL
> > > > 0x01F4 0x045C 0x055C 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC
> > > > 0x01F4 0x045C 0x04DC 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6
> > > > 0x01F4 0x045C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
> > > > 0x01F8 0x0460 0x05A8 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX
> > > > 0x01F8 0x0460 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX
> > > > 0x01F8 0x0460 0x0504 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA
> > > > 0x01F8 0x0460 0x056C 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK
> > > > 0x01F8 0x0460 0x04D0 0x3 0x3 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7
> > > > 0x01F8 0x0460 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
> > > > 0x01FC 0x0464 0x05C4 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B
> > > > 0x01FC 0x0464 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B
> > > > 0x01FC 0x0464 0x0500 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL
> > > > 0x01FC 0x0464 0x05D0 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0
> > > > 0x01FC 0x0464 0x04D4 0x3 0x3 +#define
> > > > MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8
> > > > 0x01FC 0x0464 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0
> > > > 0x0200 0x0468 0x0564 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B
> > > > 0x0200 0x0468 0x0500 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B
> > > > 0x0200 0x0468 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA
> > > > 0x0200 0x0468 0x0560 0x2 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1
> > > > 0x0200 0x0468 0x04D8 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC
> > > > 0x0200 0x0468 0x04EC 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9
> > > > 0x0200 0x0468 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
> > > > 0x0204 0x046C 0x0580 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
> > > > 0x0204 0x046C 0x050C 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX
> > > > 0x0204 0x046C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL
> > > > 0x0204 0x046C 0x0588 0x2 0x4 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2
> > > > 0x0204 0x046C 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK
> > > > 0x0204 0x046C 0x04E8 0x4 0x3 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10
> > > > 0x0204 0x046C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
> > > > 0x0208 0x0470 0x0590 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
> > > > 0x0208 0x0470 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX
> > > > 0x0208 0x0470 0x050C 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA
> > > > 0x0208 0x0470 0x05BC 0x2 0x4 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3
> > > > 0x0208 0x0470 0x04E0 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0
> > > > 0x0208 0x0470 0x0000 0x4 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11
> > > > 0x0208 0x0470 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
> > > > 0x020C 0x0474 0x0578 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
> > > > 0x020C 0x0474 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B
> > > > 0x020C 0x0474 0x0508 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL
> > > > 0x020C 0x0474 0x05D4 0x2 0x3 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK
> > > > 0x020C 0x0474 0x0594 0x3 0x4 +#define
> > > > MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12
> > > > 0x020C 0x0474 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0
> > > > 0x0210 0x0478 0x0570 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
> > > > 0x0210 0x0478 0x0508 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B
> > > > 0x0210 0x0478 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA
> > > > 0x0210 0x0478 0x058C 0x2 0x5 +#define
> > > > MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13
> > > > 0x0210 0x0478 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL
> > > > 0x0214 0x047C 0x055C 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC
> > > > 0x0214 0x047C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK
> > > > 0x0214 0x047C 0x05D8 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14
> > > > 0x0214 0x047C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA
> > > > 0x0218 0x0480 0x056C 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO
> > > > 0x0218 0x0480 0x04C0 0x1 0x2 +#define
> > > > MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI
> > > > 0x0218 0x0480 0x05A8 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15
> > > > 0x0218 0x0480 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL
> > > > 0x021C 0x0484 0x05D0 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN
> > > > 0x021C 0x0484 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B
> > > > 0x021C 0x0484 0x0598 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO
> > > > 0x021C 0x0484 0x05C4 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16
> > > > 0x021C 0x0484 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA
> > > > 0x0220 0x0488 0x0560 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT
> > > > 0x0220 0x0488 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP
> > > > 0x0220 0x0488 0x05B8 0x2 0x1 +#define
> > > > MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0
> > > > 0x0220 0x0488 0x0564 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17
> > > > 0x0220 0x0488 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL
> > > > 0x0224 0x048C 0x0588 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT
> > > > 0x0224 0x048C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK
> > > > 0x0224 0x048C 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK
> > > > 0x0224 0x048C 0x0580 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18
> > > > 0x0224 0x048C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA
> > > > 0x0228 0x0490 0x05BC 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT
> > > > 0x0228 0x0490 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK
> > > > 0x0228 0x0490 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI
> > > > 0x0228 0x0490 0x0590 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19
> > > > 0x0228 0x0490 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL
> > > > 0x022C 0x0494 0x05D4 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT
> > > > 0x022C 0x0494 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO
> > > > 0x022C 0x0494 0x0578 0x3 0x2 +#define
> > > > MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20
> > > > 0x022C 0x0494 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA
> > > > 0x0230 0x0498 0x058C 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT
> > > > 0x0230 0x0498 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0
> > > > 0x0230 0x0498 0x0570 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21
> > > > 0x0230 0x0498 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX
> > > > 0x0234 0x049C 0x04F4 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX
> > > > 0x0234 0x049C 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK
> > > > 0x0234 0x049C 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22
> > > > 0x0234 0x049C 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX
> > > > 0x0238 0x04A0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX
> > > > 0x0238 0x04A0 0x04F4 0x0 0x1 +#define
> > > > MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI
> > > > 0x0238 0x04A0 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23
> > > > 0x0238 0x04A0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX
> > > > 0x023C 0x04A4 0x04FC 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX
> > > > 0x023C 0x04A4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO
> > > > 0x023C 0x04A4 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3
> > > > 0x023C 0x04A4 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24
> > > > 0x023C 0x04A4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX
> > > > 0x0240 0x04A8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX
> > > > 0x0240 0x04A8 0x04FC 0x0 0x1 +#define
> > > > MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0
> > > > 0x0240 0x04A8 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2
> > > > 0x0240 0x04A8 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25
> > > > 0x0240 0x04A8 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX
> > > > 0x0244 0x04AC 0x0504 0x0 0x2 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX
> > > > 0x0244 0x04AC 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B
> > > > 0x0244 0x04AC 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B
> > > > 0x0244 0x04AC 0x04F0 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B
> > > > 0x0244 0x04AC 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2
> > > > 0x0244 0x04AC 0x05EC 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26
> > > > 0x0244 0x04AC 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX
> > > > 0x0248 0x04B0 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX
> > > > 0x0248 0x04B0 0x0504 0x0 0x3 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B
> > > > 0x0248 0x04B0 0x04F0 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B
> > > > 0x0248 0x04B0 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT
> > > > 0x0248 0x04B0 0x0000 0x2 0x0 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_GPT1_CLK
> > > > 0x0248 0x04B0 0x05E8 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27
> > > > 0x0248 0x04B0 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX
> > > > 0x024C 0x04B4 0x050C 0x0 0x2 +#define
> > > > MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX
> > > > 0x024C 0x04B4 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
> > > > 0x024C 0x04B4 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B
> > > > 0x024C 0x04B4 0x04F8 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1
> > > > 0x024C 0x04B4 0x0000 0x3 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28
> > > > 0x024C 0x04B4 0x0000 0x5 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX
> > > > 0x0250 0x04B8 0x0000 0x0 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX
> > > > 0x0250 0x04B8 0x050C 0x0 0x3 +#define
> > > > MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
> > > > 0x0250 0x04B8 0x04F8 0x1 0x1 +#define
> > > > MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B
> > > > 0x0250 0x04B8 0x0000 0x1 0x0 +#define
> > > > MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1
> > > > 0x0250 0x04B8 0x05F0 0x3 0x1 +#define
> > > > MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29
> > > > 0x0250 0x04B8 0x0000 0x5 0x0 + +#endif /*
> __DTS_IMX8MN_PINFUNC_H
> > > */
> > > > diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
> > > > new file mode 100644 index 0000000000..f5eff35986 --- /dev/null
> > > > +++ b/arch/arm/dts/imx8mn.dtsi @@ -0,0 +1,712 @@ +//
> > > > SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*
> > > > + * Copyright 2019 NXP
> > > > + */
> > > > +
> > > > +#include <dt-bindings/clock/imx8mn-clock.h>
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > > +#include <dt-bindings/input/input.h>
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +
> > > > +#include "imx8mn-pinfunc.h"
> > > > +
> > > > +/ {
> > > > + compatible = "fsl,imx8mn";
> > > > + interrupt-parent = <&gic>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > +
> > > > + aliases {
> > > > + ethernet0 = &fec1;
> > > > + gpio0 = &gpio1;
> > > > + gpio1 = &gpio2;
> > > > + gpio2 = &gpio3;
> > > > + gpio3 = &gpio4;
> > > > + gpio4 = &gpio5;
> > > > + i2c0 = &i2c1;
> > > > + i2c1 = &i2c2;
> > > > + i2c2 = &i2c3;
> > > > + i2c3 = &i2c4;
> > > > + mmc0 = &usdhc1;
> > > > + mmc1 = &usdhc2;
> > > > + mmc2 = &usdhc3;
> > > > + serial0 = &uart1;
> > > > + serial1 = &uart2;
> > > > + serial2 = &uart3;
> > > > + serial3 = &uart4;
> > > > + spi0 = &ecspi1;
> > > > + spi1 = &ecspi2;
> > > > + spi2 = &ecspi3;
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + A53_0: cpu at 0 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x0>;
> > > > + clock-latency = <61036>;
> > > > + clocks = <&clk IMX8MN_CLK_ARM>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_1: cpu at 1 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x1>;
> > > > + clock-latency = <61036>;
> > > > + clocks = <&clk IMX8MN_CLK_ARM>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_2: cpu at 2 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x2>;
> > > > + clock-latency = <61036>;
> > > > + clocks = <&clk IMX8MN_CLK_ARM>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_3: cpu at 3 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a53";
> > > > + reg = <0x3>;
> > > > + clock-latency = <61036>;
> > > > + clocks = <&clk IMX8MN_CLK_ARM>;
> > > > + enable-method = "psci";
> > > > + next-level-cache = <&A53_L2>;
> > > > + };
> > > > +
> > > > + A53_L2: l2-cache0 {
> > > > + compatible = "cache";
> > > > + };
> > > > + };
> > > > +
> > > > + memory at 40000000 {
> > > > + device_type = "memory";
> > > > + reg = <0x0 0x40000000 0 0x80000000>;
> > > > + };
> > > > +
> > > > + osc_32k: clock-osc-32k {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <32768>;
> > > > + clock-output-names = "osc_32k";
> > > > + };
> > > > +
> > > > + osc_24m: clock-osc-24m {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <24000000>;
> > > > + clock-output-names = "osc_24m";
> > > > + };
> > > > +
> > > > + clk_ext1: clock-ext1 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <133000000>;
> > > > + clock-output-names = "clk_ext1";
> > > > + };
> > > > +
> > > > + clk_ext2: clock-ext2 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <133000000>;
> > > > + clock-output-names = "clk_ext2";
> > > > + };
> > > > +
> > > > + clk_ext3: clock-ext3 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <133000000>;
> > > > + clock-output-names = "clk_ext3";
> > > > + };
> > > > +
> > > > + clk_ext4: clock-ext4 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency= <133000000>;
> > > > + clock-output-names = "clk_ext4";
> > > > + };
> > > > +
> > > > + psci {
> > > > + compatible = "arm,psci-1.0";
> > > > + method = "smc";
> > > > + };
> > > > +
> > > > + timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>,
> > > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>,
> > > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>,
> > > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6)
> > > > | IRQ_TYPE_LEVEL_LOW)>;
> > > > + clock-frequency = <8000000>;
> > > > + arm,no-tick-in-suspend;
> > > > + };
> > > > +
> > > > + soc at 0 {
> > > > + compatible = "simple-bus";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x0 0x3e000000>;
> > > > +
> > > > + aips1: bus at 30000000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + reg = <0x30000000 0x400000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges;
> > > > +
> > > > + gpio1: gpio at 30200000 {
> > > > + compatible = "fsl,imx8mn-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x30200000 0x10000>;
> > > > + interrupts = <GIC_SPI 64
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 65
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_GPIO1_ROOT>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio2: gpio at 30210000 {
> > > > + compatible = "fsl,imx8mn-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x30210000 0x10000>;
> > > > + interrupts = <GIC_SPI 66
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 67
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_GPIO2_ROOT>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio3: gpio at 30220000 {
> > > > + compatible = "fsl,imx8mn-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x30220000 0x10000>;
> > > > + interrupts = <GIC_SPI 68
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 69
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_GPIO3_ROOT>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio4: gpio at 30230000 {
> > > > + compatible = "fsl,imx8mn-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x30230000 0x10000>;
> > > > + interrupts = <GIC_SPI 70
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 71
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_GPIO4_ROOT>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + gpio5: gpio at 30240000 {
> > > > + compatible = "fsl,imx8mn-gpio",
> > > > "fsl,imx35-gpio";
> > > > + reg = <0x30240000 0x10000>;
> > > > + interrupts = <GIC_SPI 72
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 73
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_GPIO5_ROOT>;
> > > > + gpio-controller;
> > > > + #gpio-cells = <2>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <2>;
> > > > + };
> > > > +
> > > > + wdog1: watchdog at 30280000 {
> > > > + compatible = "fsl,imx8mn-wdt",
> > > > "fsl,imx21-wdt";
> > > > + reg = <0x30280000 0x10000>;
> > > > + interrupts = <GIC_SPI 78
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_WDOG1_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + wdog2: watchdog at 30290000 {
> > > > + compatible = "fsl,imx8mn-wdt",
> > > > "fsl,imx21-wdt";
> > > > + reg = <0x30290000 0x10000>;
> > > > + interrupts = <GIC_SPI 79
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_WDOG2_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + wdog3: watchdog at 302a0000 {
> > > > + compatible = "fsl,imx8mn-wdt",
> > > > "fsl,imx21-wdt";
> > > > + reg = <0x302a0000 0x10000>;
> > > > + interrupts = <GIC_SPI 10
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_WDOG3_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + sdma3: dma-controller at 302b0000 {
> > > > + compatible = "fsl,imx8mn-sdma",
> > > > "fsl,imx7d-sdma";
> > > > + reg = <0x302b0000 0x10000>;
> > > > + interrupts = <GIC_SPI 34
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_SDMA3_ROOT>,
> > > > + <&clk IMX8MN_CLK_SDMA3_ROOT>;
> > > > + clock-names = "ipg", "ahb";
> > > > + #dma-cells = <3>;
> > > > + fsl,sdma-ram-script-name =
> > > > "imx/sdma/sdma-imx7d.bin";
> > > > + };
> > > > +
> > > > + sdma2: dma-controller at 302c0000 {
> > > > + compatible = "fsl,imx8mn-sdma",
> > > > "fsl,imx7d-sdma";
> > > > + reg = <0x302c0000 0x10000>;
> > > > + interrupts = <GIC_SPI 103
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_SDMA2_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_SDMA2_ROOT>;
> > > > + clock-names = "ipg", "ahb";
> > > > + #dma-cells = <3>;
> > > > + fsl,sdma-ram-script-name =
> > > > "imx/sdma/sdma-imx7d.bin";
> > > > + };
> > > > +
> > > > + iomuxc: pinctrl at 30330000 {
> > > > + compatible = "fsl,imx8mn-iomuxc";
> > > > + reg = <0x30330000 0x10000>;
> > > > + };
> > > > +
> > > > + gpr: iomuxc-gpr at 30340000 {
> > > > + compatible =
> > > > "fsl,imx8mn-iomuxc-gpr", "syscon";
> > > > + reg = <0x30340000 0x10000>;
> > > > + };
> > > > +
> > > > + ocotp: ocotp-ctrl at 30350000 {
> > > > + compatible = "fsl,imx8mn-ocotp",
> > > > "fsl,imx7d-ocotp", "syscon";
> > > > + reg = <0x30350000 0x10000>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_OCOTP_ROOT>;
> > > > + };
> > > > +
> > > > + anatop: anatop at 30360000 {
> > > > + compatible = "fsl,imx8mn-anatop",
> > > > "fsl,imx8mm-anatop",
> > > > + "syscon",
> > > > "simple-bus";
> > > > + reg = <0x30360000 0x10000>;
> > > > + };
> > > > +
> > > > + snvs: snvs at 30370000 {
> > > > + compatible =
> > > > "fsl,sec-v4.0-mon","syscon", "simple-mfd";
> > > > + reg = <0x30370000 0x10000>;
> > > > +
> > > > + snvs_rtc: snvs-rtc-lp {
> > > > + compatible =
> > > > "fsl,sec-v4.0-mon-rtc-lp";
> > > > + regmap = <&snvs>;
> > > > + offset = <0x34>;
> > > > + interrupts = <GIC_SPI
> > > > 19 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI
> > > > 20 IRQ_TYPE_LEVEL_HIGH>;
> > > > + clock-names = "snvs-rtc";
> > > > + };
> > > > +
> > > > + snvs_pwrkey: snvs-powerkey {
> > > > + compatible =
> > > > "fsl,sec-v4.0-pwrkey";
> > > > + regmap = <&snvs>;
> > > > + interrupts = <GIC_SPI 4
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + linux,keycode =
> > > > <KEY_POWER>;
> > > > + wakeup-source;
> > > > + status = "disabled";
> > > > + };
> > > > + };
> > > > +
> > > > + clk: clock-controller at 30380000 {
> > > > + compatible = "fsl,imx8mn-ccm";
> > > > + reg = <0x30380000 0x10000>;
> > > > + #clock-cells = <1>;
> > > > + clocks = <&osc_32k>, <&osc_24m>,
> > > > <&clk_ext1>, <&clk_ext2>,
> > > > + <&clk_ext3>,
> > > > <&clk_ext4>;
> > > > + clock-names = "osc_32k",
> > > > "osc_24m", "clk_ext1", "clk_ext2",
> > > > + "clk_ext3",
> > > > "clk_ext4";
> > > > + };
> > > > +
> > > > + src: reset-controller at 30390000 {
> > > > + compatible = "fsl,imx8mn-src",
> > > > "syscon";
> > > > + reg = <0x30390000 0x10000>;
> > > > + interrupts = <GIC_SPI 89
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + aips2: bus at 30400000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + reg = <0x30400000 0x400000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges;
> > > > +
> > > > + pwm1: pwm at 30660000 {
> > > > + compatible = "fsl,imx8mn-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x30660000 0x10000>;
> > > > + interrupts = <GIC_SPI 81
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_PWM1_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_PWM1_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pwm2: pwm at 30670000 {
> > > > + compatible = "fsl,imx8mn-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x30670000 0x10000>;
> > > > + interrupts = <GIC_SPI 82
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_PWM2_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_PWM2_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pwm3: pwm at 30680000 {
> > > > + compatible = "fsl,imx8mn-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x30680000 0x10000>;
> > > > + interrupts = <GIC_SPI 83
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_PWM3_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_PWM3_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pwm4: pwm at 30690000 {
> > > > + compatible = "fsl,imx8mn-pwm",
> > > > "fsl,imx27-pwm";
> > > > + reg = <0x30690000 0x10000>;
> > > > + interrupts = <GIC_SPI 84
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_PWM4_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_PWM4_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + #pwm-cells = <2>;
> > > > + status = "disabled";
> > > > + };
> > > > + };
> > > > +
> > > > + aips3: bus at 30800000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + reg = <0x30800000 0x400000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges;
> > > > +
> > > > + ecspi1: spi at 30820000 {
> > > > + compatible = "fsl,imx8mn-ecspi",
> > > > "fsl,imx51-ecspi";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + reg = <0x30820000 0x10000>;
> > > > + interrupts = <GIC_SPI 31
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_ECSPI1_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_ECSPI1_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + dmas = <&sdma1 0 7 1>, <&sdma1 1
> > > > 7
> > > > 2>;
> > > > + dma-names = "rx", "tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + ecspi2: spi at 30830000 {
> > > > + compatible = "fsl,imx8mn-ecspi",
> > > > "fsl,imx51-ecspi";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + reg = <0x30830000 0x10000>;
> > > > + interrupts = <GIC_SPI 32
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_ECSPI2_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_ECSPI2_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + dmas = <&sdma1 2 7 1>, <&sdma1 3
> > > > 7
> > > > 2>;
> > > > + dma-names = "rx", "tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + ecspi3: spi at 30840000 {
> > > > + compatible = "fsl,imx8mn-ecspi",
> > > > "fsl,imx51-ecspi";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + reg = <0x30840000 0x10000>;
> > > > + interrupts = <GIC_SPI 33
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_ECSPI3_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_ECSPI3_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + dmas = <&sdma1 4 7 1>, <&sdma1 5
> > > > 7
> > > > 2>;
> > > > + dma-names = "rx", "tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart1: serial at 30860000 {
> > > > + compatible = "fsl,imx8mn-uart",
> > > > "fsl,imx6q-uart";
> > > > + reg = <0x30860000 0x10000>;
> > > > + interrupts = <GIC_SPI 26
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_UART1_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_UART1_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + dmas = <&sdma1 22 4 0>, <&sdma1
> > > > 23 4
> > > > 0>;
> > > > + dma-names = "rx", "tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart3: serial at 30880000 {
> > > > + compatible = "fsl,imx8mn-uart",
> > > > "fsl,imx6q-uart";
> > > > + reg = <0x30880000 0x10000>;
> > > > + interrupts = <GIC_SPI 28
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_UART3_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_UART3_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + dmas = <&sdma1 26 4 0>, <&sdma1
> > > > 27 4
> > > > 0>;
> > > > + dma-names = "rx", "tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart2: serial at 30890000 {
> > > > + compatible = "fsl,imx8mn-uart",
> > > > "fsl,imx6q-uart";
> > > > + reg = <0x30890000 0x10000>;
> > > > + interrupts = <GIC_SPI 27
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_UART2_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_UART2_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c1: i2c at 30a20000 {
> > > > + compatible = "fsl,imx8mn-i2c",
> > > > "fsl,imx21-i2c";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + reg = <0x30a20000 0x10000>;
> > > > + interrupts = <GIC_SPI 35
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_I2C1_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c2: i2c at 30a30000 {
> > > > + compatible = "fsl,imx8mn-i2c",
> > > > "fsl,imx21-i2c";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + reg = <0x30a30000 0x10000>;
> > > > + interrupts = <GIC_SPI 36
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_I2C2_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c3: i2c at 30a40000 {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + compatible = "fsl,imx8mn-i2c",
> > > > "fsl,imx21-i2c";
> > > > + reg = <0x30a40000 0x10000>;
> > > > + interrupts = <GIC_SPI 37
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_I2C3_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + i2c4: i2c at 30a50000 {
> > > > + compatible = "fsl,imx8mn-i2c",
> > > > "fsl,imx21-i2c";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > + reg = <0x30a50000 0x10000>;
> > > > + interrupts = <GIC_SPI 38
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_I2C4_ROOT>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart4: serial at 30a60000 {
> > > > + compatible = "fsl,imx8mn-uart",
> > > > "fsl,imx6q-uart";
> > > > + reg = <0x30a60000 0x10000>;
> > > > + interrupts = <GIC_SPI 29
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_UART4_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_UART4_ROOT>;
> > > > + clock-names = "ipg", "per";
> > > > + dmas = <&sdma1 28 4 0>, <&sdma1
> > > > 29 4
> > > > 0>;
> > > > + dma-names = "rx", "tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc1: mmc at 30b40000 {
> > > > + compatible = "fsl,imx8mn-usdhc",
> > > > "fsl,imx7d-usdhc";
> > > > + reg = <0x30b40000 0x10000>;
> > > > + interrupts = <GIC_SPI 22
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk IMX8MN_CLK_DUMMY>,
> > > > + <&clk
> > > > IMX8MN_CLK_NAND_USDHC_BUS>,
> > > > + <&clk
> > > > IMX8MN_CLK_USDHC1_ROOT>;
> > > > + clock-names = "ipg", "ahb",
> > > > "per";
> > > > + assigned-clocks = <&clk
> > > > IMX8MN_CLK_USDHC1>;
> > > > + assigned-clock-rates =
> > > > <400000000>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + fsl,tuning-step= <2>;
> > > > + bus-width = <4>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc2: mmc at 30b50000 {
> > > > + compatible = "fsl,imx8mn-usdhc",
> > > > "fsl,imx7d-usdhc";
> > > > + reg = <0x30b50000 0x10000>;
> > > > + interrupts = <GIC_SPI 23
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk IMX8MN_CLK_DUMMY>,
> > > > + <&clk
> > > > IMX8MN_CLK_NAND_USDHC_BUS>,
> > > > + <&clk
> > > > IMX8MN_CLK_USDHC2_ROOT>;
> > > > + clock-names = "ipg", "ahb",
> > > > "per";
> > > > + fsl,tuning-start-tap = <20>;
> > > > + fsl,tuning-step= <2>;
> > > > + bus-width = <4>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usdhc3: mmc at 30b60000 {
> > > > + compatible = "fsl,imx8mn-usdhc",
> > > > "fsl,imx7d-usdhc";
> > > > + reg = <0x30b60000 0x10000>;
> > > > + interrupts = <GIC_SPI 24
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk IMX8MN_CLK_DUMMY>,
> > > > + <&clk
> > > > IMX8MN_CLK_NAND_USDHC_BUS>,
> > > > + <&clk
> > > > IMX8MN_CLK_USDHC3_ROOT>;
> > > > + clock-names = "ipg", "ahb",
> > > > "per";
> > > > + assigned-clocks = <&clk
> > > > IMX8MN_CLK_USDHC3_ROOT>;
> > > > + assigned-clock-rates =
> > > > <400000000>;
> > > > + fsl,tuning-start-tap = <20>;
> > > > + fsl,tuning-step= <2>;
> > > > + bus-width = <4>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + sdma1: dma-controller at 30bd0000 {
> > > > + compatible = "fsl,imx8mn-sdma",
> > > > "fsl,imx7d-sdma";
> > > > + reg = <0x30bd0000 0x10000>;
> > > > + interrupts = <GIC_SPI 2
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_SDMA1_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_SDMA1_ROOT>;
> > > > + clock-names = "ipg", "ahb";
> > > > + #dma-cells = <3>;
> > > > + fsl,sdma-ram-script-name =
> > > > "imx/sdma/sdma-imx7d.bin";
> > > > + };
> > > > +
> > > > + fec1: ethernet at 30be0000 {
> > > > + compatible = "fsl,imx8mn-fec",
> > > > "fsl,imx6sx-fec";
> > > > + reg = <0x30be0000 0x10000>;
> > > > + interrupts = <GIC_SPI 118
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 119
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 120
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_ENET1_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET1_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET_TIMER>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET_REF>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET_PHY_REF>;
> > > > + clock-names = "ipg", "ahb",
> > > > "ptp",
> > > > + "enet_clk_ref",
> > > > "enet_out";
> > > > + assigned-clocks = <&clk
> > > > IMX8MN_CLK_ENET_AXI>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET_TIMER>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET_REF>,
> > > > + <&clk
> > > > IMX8MN_CLK_ENET_TIMER>;
> > > > + assigned-clock-parents = <&clk
> > > > IMX8MN_SYS_PLL1_266M>,
> > > > + <&clk
> > > > IMX8MN_SYS_PLL2_100M>,
> > > > + <&clk
> > > > IMX8MN_SYS_PLL2_125M>;
> > > > + assigned-clock-rates = <0>, <0>,
> > > > <125000000>, <100000000>;
> > > > + fsl,num-tx-queues = <3>;
> > > > + fsl,num-rx-queues = <3>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + };
> > > > +
> > > > + aips4: bus at 32c00000 {
> > > > + compatible = "fsl,aips-bus",
> > > > "simple-bus";
> > > > + reg = <0x32c00000 0x400000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges;
> > > > +
> > > > + usbotg1: usb at 32e40000 {
> > > > + compatible = "fsl,imx8mn-usb",
> > > > "fsl,imx7d-usb";
> > > > + reg = <0x32e40000 0x200>;
> > > > + interrupts = <GIC_SPI 40
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_USB1_CTRL_ROOT>;
> > > > + clock-names =
> > > > "usb1_ctrl_root_clk";
> > > > + assigned-clocks = <&clk
> > > > IMX8MN_CLK_USB_BUS>,
> > > > + <&clk
> > > > IMX8MN_CLK_USB_CORE_REF>;
> > > > + assigned-clock-parents = <&clk
> > > > IMX8MN_SYS_PLL2_500M>,
> > > > + <&clk
> > > > IMX8MN_SYS_PLL1_100M>;
> > > > + fsl,usbphy = <&usbphynop1>;
> > > > + fsl,usbmisc = <&usbmisc1 0>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usbmisc1: usbmisc at 32e40200 {
> > > > + compatible =
> > > > "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
> > > > + #index-cells = <1>;
> > > > + reg = <0x32e40200 0x200>;
> > > > + };
> > > > +
> > > > + usbotg2: usb at 32e50000 {
> > > > + compatible = "fsl,imx8mn-usb",
> > > > "fsl,imx7d-usb";
> > > > + reg = <0x32e50000 0x200>;
> > > > + interrupts = <GIC_SPI 41
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_USB1_CTRL_ROOT>;
> > > > + clock-names =
> > > > "usb1_ctrl_root_clk";
> > > > + assigned-clocks = <&clk
> > > > IMX8MN_CLK_USB_BUS>,
> > > > + <&clk
> > > > IMX8MN_CLK_USB_CORE_REF>;
> > > > + assigned-clock-parents = <&clk
> > > > IMX8MN_SYS_PLL2_500M>,
> > > > + <&clk
> > > > IMX8MN_SYS_PLL1_100M>;
> > > > + fsl,usbphy = <&usbphynop2>;
> > > > + fsl,usbmisc = <&usbmisc2 0>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + usbmisc2: usbmisc at 32e50200 {
> > > > + compatible =
> > > > "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
> > > > + #index-cells = <1>;
> > > > + reg = <0x32e50200 0x200>;
> > > > + };
> > > > +
> > > > + };
> > > > +
> > > > + dma_apbh: dma-controller at 33000000 {
> > > > + compatible = "fsl,imx7d-dma-apbh",
> > > > "fsl,imx28-dma-apbh";
> > > > + reg = <0x33000000 0x2000>;
> > > > + interrupts = <GIC_SPI 12
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 12
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 12
> > > > IRQ_TYPE_LEVEL_HIGH>,
> > > > + <GIC_SPI 12
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + interrupt-names = "gpmi0", "gpmi1",
> > > > "gpmi2", "gpmi3";
> > > > + #dma-cells = <1>;
> > > > + dma-channels = <4>;
> > > > + clocks = <&clk
> > > > IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
> > > > + };
> > > > +
> > > > + gpmi: nand-controller at 33002000 {
> > > > + compatible = "fsl,imx8mn-gpmi-nand",
> > > > "fsl,imx7d-gpmi-nand";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + reg = <0x33002000 0x2000>, <0x33004000
> > > > 0x4000>;
> > > > + reg-names = "gpmi-nand", "bch";
> > > > + interrupts = <GIC_SPI 14
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + interrupt-names = "bch";
> > > > + clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
> > > > + <&clk
> > > > IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
> > > > + clock-names = "gpmi_io", "gpmi_bch_apb";
> > > > + dmas = <&dma_apbh 0>;
> > > > + dma-names = "rx-tx";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + gic: interrupt-controller at 38800000 {
> > > > + compatible = "arm,gic-v3";
> > > > + reg = <0x38800000 0x10000>,
> > > > + <0x38880000 0xc0000>;
> > > > + #interrupt-cells = <3>;
> > > > + interrupt-controller;
> > > > + interrupts = <GIC_PPI 9
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > + };
> > > > +
> > > > + usbphynop1: usbphynop1 {
> > > > + compatible = "usb-nop-xceiv";
> > > > + clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> > > > + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> > > > + assigned-clock-parents = <&clk
> > > > IMX8MN_SYS_PLL1_100M>;
> > > > + clock-names = "main_clk";
> > > > + };
> > > > +
> > > > + usbphynop2: usbphynop2 {
> > > > + compatible = "usb-nop-xceiv";
> > > > + clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> > > > + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
> > > > + assigned-clock-parents = <&clk
> > > > IMX8MN_SYS_PLL1_100M>;
> > > > + clock-names = "main_clk";
> > > > + };
> > > > +};
> > > > diff --git a/include/dt-bindings/clock/imx8mn-clock.h
> > > > b/include/dt-bindings/clock/imx8mn-clock.h new file mode 100644
> > > > index 0000000000..5255b1c242
> > > > --- /dev/null
> > > > +++ b/include/dt-bindings/clock/imx8mn-clock.h
> > > > @@ -0,0 +1,215 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > > +/*
> > > > + * Copyright 2018-2019 NXP
> > > > + */
> > > > +
> > > > +#ifndef __DT_BINDINGS_CLOCK_IMX8MN_H
> > > > +#define __DT_BINDINGS_CLOCK_IMX8MN_H
> > > > +
> > > > +#define IMX8MN_CLK_DUMMY 0
> > > > +#define IMX8MN_CLK_32K 1
> > > > +#define IMX8MN_CLK_24M 2
> > > > +#define IMX8MN_OSC_HDMI_CLK 3
> > > > +#define IMX8MN_CLK_EXT1 4
> > > > +#define IMX8MN_CLK_EXT2 5
> > > > +#define IMX8MN_CLK_EXT3 6
> > > > +#define IMX8MN_CLK_EXT4 7
> > > > +#define IMX8MN_AUDIO_PLL1_REF_SEL 8
> > > > +#define IMX8MN_AUDIO_PLL2_REF_SEL 9
> > > > +#define IMX8MN_VIDEO_PLL1_REF_SEL 10
> > > > +#define IMX8MN_DRAM_PLL_REF_SEL 11
> > > > +#define IMX8MN_GPU_PLL_REF_SEL 12
> > > > +#define IMX8MN_VPU_PLL_REF_SEL 13
> > > > +#define IMX8MN_ARM_PLL_REF_SEL 14
> > > > +#define IMX8MN_SYS_PLL1_REF_SEL 15
> > > > +#define IMX8MN_SYS_PLL2_REF_SEL 16
> > > > +#define IMX8MN_SYS_PLL3_REF_SEL 17
> > > > +#define IMX8MN_AUDIO_PLL1 18
> > > > +#define IMX8MN_AUDIO_PLL2 19
> > > > +#define IMX8MN_VIDEO_PLL1 20
> > > > +#define IMX8MN_DRAM_PLL 21
> > > > +#define IMX8MN_GPU_PLL 22
> > > > +#define IMX8MN_VPU_PLL 23
> > > > +#define IMX8MN_ARM_PLL 24
> > > > +#define IMX8MN_SYS_PLL1 25
> > > > +#define IMX8MN_SYS_PLL2 26
> > > > +#define IMX8MN_SYS_PLL3 27
> > > > +#define IMX8MN_AUDIO_PLL1_BYPASS 28
> > > > +#define IMX8MN_AUDIO_PLL2_BYPASS 29
> > > > +#define IMX8MN_VIDEO_PLL1_BYPASS 30
> > > > +#define IMX8MN_DRAM_PLL_BYPASS 31
> > > > +#define IMX8MN_GPU_PLL_BYPASS 32
> > > > +#define IMX8MN_VPU_PLL_BYPASS 33
> > > > +#define IMX8MN_ARM_PLL_BYPASS 34
> > > > +#define IMX8MN_SYS_PLL1_BYPASS 35
> > > > +#define IMX8MN_SYS_PLL2_BYPASS 36
> > > > +#define IMX8MN_SYS_PLL3_BYPASS 37
> > > > +#define IMX8MN_AUDIO_PLL1_OUT 38
> > > > +#define IMX8MN_AUDIO_PLL2_OUT 39
> > > > +#define IMX8MN_VIDEO_PLL1_OUT 40
> > > > +#define IMX8MN_DRAM_PLL_OUT 41
> > > > +#define IMX8MN_GPU_PLL_OUT 42
> > > > +#define IMX8MN_VPU_PLL_OUT 43
> > > > +#define IMX8MN_ARM_PLL_OUT 44
> > > > +#define IMX8MN_SYS_PLL1_OUT 45
> > > > +#define IMX8MN_SYS_PLL2_OUT 46
> > > > +#define IMX8MN_SYS_PLL3_OUT 47
> > > > +#define IMX8MN_SYS_PLL1_40M 48
> > > > +#define IMX8MN_SYS_PLL1_80M 49
> > > > +#define IMX8MN_SYS_PLL1_100M 50
> > > > +#define IMX8MN_SYS_PLL1_133M 51
> > > > +#define IMX8MN_SYS_PLL1_160M 52
> > > > +#define IMX8MN_SYS_PLL1_200M 53
> > > > +#define IMX8MN_SYS_PLL1_266M 54
> > > > +#define IMX8MN_SYS_PLL1_400M 55
> > > > +#define IMX8MN_SYS_PLL1_800M 56
> > > > +#define IMX8MN_SYS_PLL2_50M 57
> > > > +#define IMX8MN_SYS_PLL2_100M 58
> > > > +#define IMX8MN_SYS_PLL2_125M 59
> > > > +#define IMX8MN_SYS_PLL2_166M 60
> > > > +#define IMX8MN_SYS_PLL2_200M 61
> > > > +#define IMX8MN_SYS_PLL2_250M 62
> > > > +#define IMX8MN_SYS_PLL2_333M 63
> > > > +#define IMX8MN_SYS_PLL2_500M 64
> > > > +#define IMX8MN_SYS_PLL2_1000M 65
> > > > +
> > > > +/* CORE CLOCK ROOT */
> > > > +#define IMX8MN_CLK_A53_SRC 66
> > > > +#define IMX8MN_CLK_GPU_CORE_SRC 67
> > > > +#define IMX8MN_CLK_GPU_SHADER_SRC 68
> > > > +#define IMX8MN_CLK_A53_CG 69
> > > > +#define IMX8MN_CLK_GPU_CORE_CG 70
> > > > +#define IMX8MN_CLK_GPU_SHADER_CG 71
> > > > +#define IMX8MN_CLK_A53_DIV 72
> > > > +#define IMX8MN_CLK_GPU_CORE_DIV 73
> > > > +#define IMX8MN_CLK_GPU_SHADER_DIV 74
> > > > +
> > > > +/* BUS CLOCK ROOT */
> > > > +#define IMX8MN_CLK_MAIN_AXI 75
> > > > +#define IMX8MN_CLK_ENET_AXI 76
> > > > +#define IMX8MN_CLK_NAND_USDHC_BUS 77
> > > > +#define IMX8MN_CLK_DISP_AXI 78
> > > > +#define IMX8MN_CLK_DISP_APB 79
> > > > +#define IMX8MN_CLK_USB_BUS 80
> > > > +#define IMX8MN_CLK_GPU_AXI 81
> > > > +#define IMX8MN_CLK_GPU_AHB 82
> > > > +#define IMX8MN_CLK_NOC 83
> > > > +#define IMX8MN_CLK_AHB 84
> > > > +#define IMX8MN_CLK_AUDIO_AHB 85
> > > > +
> > > > +/* IPG CLOCK ROOT */
> > > > +#define IMX8MN_CLK_IPG_ROOT 86
> > > > +#define IMX8MN_CLK_IPG_AUDIO_ROOT 87
> > > > +
> > > > +/* IP */
> > > > +#define IMX8MN_CLK_DRAM_CORE 88
> > > > +#define IMX8MN_CLK_DRAM_ALT 89
> > > > +#define IMX8MN_CLK_DRAM_APB 90
> > > > +#define IMX8MN_CLK_DRAM_ALT_ROOT 91
> > > > +#define IMX8MN_CLK_DISP_PIXEL 92
> > > > +#define IMX8MN_CLK_SAI2 93
> > > > +#define IMX8MN_CLK_SAI3 94
> > > > +#define IMX8MN_CLK_SAI5 95
> > > > +#define IMX8MN_CLK_SAI6 96
> > > > +#define IMX8MN_CLK_SPDIF1 97
> > > > +#define IMX8MN_CLK_ENET_REF 98
> > > > +#define IMX8MN_CLK_ENET_TIMER 99
> > > > +#define IMX8MN_CLK_ENET_PHY_REF 100
> > > > +#define IMX8MN_CLK_NAND 101
> > > > +#define IMX8MN_CLK_QSPI 102
> > > > +#define IMX8MN_CLK_USDHC1 103
> > > > +#define IMX8MN_CLK_USDHC2 104
> > > > +#define IMX8MN_CLK_I2C1 105
> > > > +#define IMX8MN_CLK_I2C2 106
> > > > +#define IMX8MN_CLK_I2C3 107
> > > > +#define IMX8MN_CLK_I2C4 118
> > > > +#define IMX8MN_CLK_UART1 119
> > > > +#define IMX8MN_CLK_UART2 110
> > > > +#define IMX8MN_CLK_UART3 111
> > > > +#define IMX8MN_CLK_UART4 112
> > > > +#define IMX8MN_CLK_USB_CORE_REF 113
> > > > +#define IMX8MN_CLK_USB_PHY_REF 114
> > > > +#define IMX8MN_CLK_ECSPI1 115
> > > > +#define IMX8MN_CLK_ECSPI2 116
> > > > +#define IMX8MN_CLK_PWM1 117
> > > > +#define IMX8MN_CLK_PWM2 118
> > > > +#define IMX8MN_CLK_PWM3 119
> > > > +#define IMX8MN_CLK_PWM4 120
> > > > +#define IMX8MN_CLK_WDOG 121
> > > > +#define IMX8MN_CLK_WRCLK 122
> > > > +#define IMX8MN_CLK_CLKO1 123
> > > > +#define IMX8MN_CLK_CLKO2 124
> > > > +#define IMX8MN_CLK_DSI_CORE 125
> > > > +#define IMX8MN_CLK_DSI_PHY_REF 126
> > > > +#define IMX8MN_CLK_DSI_DBI 127
> > > > +#define IMX8MN_CLK_USDHC3 128
> > > > +#define IMX8MN_CLK_CAMERA_PIXEL 129
> > > > +#define IMX8MN_CLK_CSI1_PHY_REF 130
> > > > +#define IMX8MN_CLK_CSI2_PHY_REF 131
> > > > +#define IMX8MN_CLK_CSI2_ESC 132
> > > > +#define IMX8MN_CLK_ECSPI3 133
> > > > +#define IMX8MN_CLK_PDM 134
> > > > +#define IMX8MN_CLK_SAI7 135
> > > > +
> > > > +#define IMX8MN_CLK_ECSPI1_ROOT 136
> > > > +#define IMX8MN_CLK_ECSPI2_ROOT 137
> > > > +#define IMX8MN_CLK_ECSPI3_ROOT 138
> > > > +#define IMX8MN_CLK_ENET1_ROOT 139
> > > > +#define IMX8MN_CLK_GPIO1_ROOT 140
> > > > +#define IMX8MN_CLK_GPIO2_ROOT 141
> > > > +#define IMX8MN_CLK_GPIO3_ROOT 142
> > > > +#define IMX8MN_CLK_GPIO4_ROOT 143
> > > > +#define IMX8MN_CLK_GPIO5_ROOT 144
> > > > +#define IMX8MN_CLK_I2C1_ROOT 145
> > > > +#define IMX8MN_CLK_I2C2_ROOT 146
> > > > +#define IMX8MN_CLK_I2C3_ROOT 147
> > > > +#define IMX8MN_CLK_I2C4_ROOT 148
> > > > +#define IMX8MN_CLK_MU_ROOT 149
> > > > +#define IMX8MN_CLK_OCOTP_ROOT 150
> > > > +#define IMX8MN_CLK_PWM1_ROOT 151
> > > > +#define IMX8MN_CLK_PWM2_ROOT 152
> > > > +#define IMX8MN_CLK_PWM3_ROOT 153
> > > > +#define IMX8MN_CLK_PWM4_ROOT 154
> > > > +#define IMX8MN_CLK_QSPI_ROOT 155
> > > > +#define IMX8MN_CLK_NAND_ROOT 156
> > > > +#define IMX8MN_CLK_SAI2_ROOT 157
> > > > +#define IMX8MN_CLK_SAI2_IPG 158
> > > > +#define IMX8MN_CLK_SAI3_ROOT 159
> > > > +#define IMX8MN_CLK_SAI3_IPG 160
> > > > +#define IMX8MN_CLK_SAI5_ROOT 161
> > > > +#define IMX8MN_CLK_SAI5_IPG 162
> > > > +#define IMX8MN_CLK_SAI6_ROOT 163
> > > > +#define IMX8MN_CLK_SAI6_IPG 164
> > > > +#define IMX8MN_CLK_SAI7_ROOT 165
> > > > +#define IMX8MN_CLK_SAI7_IPG 166
> > > > +#define IMX8MN_CLK_SDMA1_ROOT 167
> > > > +#define IMX8MN_CLK_SDMA2_ROOT 168
> > > > +#define IMX8MN_CLK_UART1_ROOT 169
> > > > +#define IMX8MN_CLK_UART2_ROOT 170
> > > > +#define IMX8MN_CLK_UART3_ROOT 171
> > > > +#define IMX8MN_CLK_UART4_ROOT 172
> > > > +#define IMX8MN_CLK_USB1_CTRL_ROOT 173
> > > > +#define IMX8MN_CLK_USDHC1_ROOT 174
> > > > +#define IMX8MN_CLK_USDHC2_ROOT 175
> > > > +#define IMX8MN_CLK_WDOG1_ROOT 176
> > > > +#define IMX8MN_CLK_WDOG2_ROOT 177
> > > > +#define IMX8MN_CLK_WDOG3_ROOT 178
> > > > +#define IMX8MN_CLK_GPU_BUS_ROOT 179
> > > > +#define IMX8MN_CLK_ASRC_ROOT 180
> > > > +#define IMX8MN_CLK_GPU3D_ROOT 181
> > > > +#define IMX8MN_CLK_PDM_ROOT 182
> > > > +#define IMX8MN_CLK_PDM_IPG 183
> > > > +#define IMX8MN_CLK_DISP_AXI_ROOT 184
> > > > +#define IMX8MN_CLK_DISP_APB_ROOT 185
> > > > +#define IMX8MN_CLK_DISP_PIXEL_ROOT 186
> > > > +#define IMX8MN_CLK_CAMERA_PIXEL_ROOT 187
> > > > +#define IMX8MN_CLK_USDHC3_ROOT 188
> > > > +#define IMX8MN_CLK_SDMA3_ROOT 189
> > > > +#define IMX8MN_CLK_TMU_ROOT 190
> > > > +#define IMX8MN_CLK_ARM 191
> > > > +#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
> > > > +#define IMX8MN_CLK_GPU_CORE_ROOT 193
> > > > +
> > > > +#define IMX8MN_CLK_END 194
> > > > +
> > > > +#endif
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH, Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
>
>
>
>
> Best regards,
>
> Lukasz Majewski
>
> --
>
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de
next prev parent reply other threads:[~2019-07-10 8:50 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 1:38 [U-Boot] [PATCH V2 00/51] Support i.MX8MM/N Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 01/51] linux: compat: guard PAGE_SIZE Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 02/51] dm: clk: ignore default settings when node not valid Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 03/51] pinctrl: imx: use devfdt_get_addr_size_index Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 04/51] i2c: mxc: add CONFIG_CLK support Peng Fan
2019-07-10 8:03 ` Lukasz Majewski
2019-07-10 8:19 ` Peng Fan
2019-07-10 14:10 ` Schrempf Frieder
2019-07-11 6:43 ` Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 05/51] tools: imx8m_image: align spl bin image size Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 06/51] ddr: imx8m: fix ddr firmware location when enable SPL OF Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 07/51] tools: imx8mimage: fix HDMI/FIT parsing Peng Fan
2019-07-08 1:38 ` [U-Boot] [PATCH V2 08/51] imx8m: add image cfg for i.MX8MM lpddr4 Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 09/51] imx: add IMX8MQ kconfig entry Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 10/51] imx: add IMX8MM " Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 11/51] imx: imx8mm: add clock bindings header Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 12/51] imx: add i.MX8MM cpu type Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 13/51] imx: spl: add spl_board_boot_device for i.MX8MM Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 14/51] imx8m: update imx-regs " Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 15/51] imx: add get_cpu_rev support " Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 16/51] imx8m: rename clock to clock_imx8mq Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 17/51] imx8m: restructure clock.h Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 18/51] imx8m: add clk support for i.MX8MM Peng Fan
2019-07-08 9:07 ` Lukasz Majewski
2019-07-08 9:32 ` Peng Fan
2019-07-08 10:13 ` Lukasz Majewski
2019-07-10 0:49 ` Peng Fan
2019-07-10 7:22 ` Lukasz Majewski
2019-07-10 8:22 ` Peng Fan
2019-07-10 8:47 ` Lukasz Majewski
2019-07-08 1:39 ` [U-Boot] [PATCH V2 19/51] imx8m: soc: probe clk before relocation Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 20/51] imx8m: add pin header for i.MX8MM Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 21/51] imx: add i.MX8MM PE property Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 22/51] imx8m: Fix MMU table issue for OPTEE memory Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 23/51] imx8m: set BYPASS ID SWAP to avoid AXI bus errors Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 24/51] imx8m: Configure trustzone region 0 for non-secure access Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 25/51] imx8m: soc: enable SCTR clock before timer init Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 26/51] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 27/51] clk: imx: add Kconfig entry for i.MX8MM Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 28/51] clk: imx: add i.MX8MM clk driver Peng Fan
2019-07-10 14:22 ` Schrempf Frieder
2019-07-08 1:39 ` [U-Boot] [PATCH V2 29/51] imx: add i.MX8MM EVK board support Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 30/51] ddr: imx8m: Fix ddr4 driver build issue Peng Fan
2019-07-08 1:39 ` [U-Boot] [PATCH V2 31/51] imx8mq: Update the ddrc QoS setting for B1 chip Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 32/51] driver: ddr: Refine the ddr init driver on imx8m Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 33/51] ddr: imx8m: Fix the ddr init hang on imx8mq Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 34/51] imx: add i.MX8MN kconfig entry Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 35/51] imx8mn: support get_cpu_rev Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 36/51] imx8m: add clk support for i.MX8MN Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 37/51] imx8mn: set BYPASS ID SWAP to avoid AXI bus errors Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 38/51] imx: add i.MX8MN PE property Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 39/51] imx8mn: add pin header Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 40/51] imx: spl: use spl_board_boot_device for i.MX8MN Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 41/51] spl: pass args to board_return_to_bootrom Peng Fan
2019-07-10 6:23 ` Kever Yang
2019-07-10 8:09 ` Philipp Tomsich
2019-07-08 1:40 ` [U-Boot] [PATCH V2 42/51] imx: add rom api support Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 43/51] imx: cpu: restrict get_boot_device Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 44/51] imx8mn: add get_boot_device Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 45/51] tools: imx8mimage: add ROM VERSION Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 46/51] pinctrl: imx8m: support i.MX8MN Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 47/51] tools: imx8m_image: support ddr4 firmware Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 48/51] clk: imx: add i.MX8MN clk support Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 49/51] imx8m: add i.MX8MN ddr4 image cfg file Peng Fan
2019-07-08 1:40 ` [U-Boot] [PATCH V2 50/51] imx: add dtsi for i.MX8MN Peng Fan
2019-07-10 8:08 ` Lukasz Majewski
2019-07-10 8:09 ` Peng Fan
2019-07-10 8:44 ` Lukasz Majewski
2019-07-10 8:50 ` Peng Fan [this message]
2019-07-08 1:40 ` [U-Boot] [PATCH V2 51/51] imx: add i.MX8MN DDR4 board support Peng Fan
2019-07-10 8:34 ` Lukasz Majewski
2019-07-10 10:05 ` Peng Fan
2019-07-10 12:18 ` Lukasz Majewski
2019-07-08 8:47 ` [U-Boot] [PATCH V2 00/51] Support i.MX8MM/N Schrempf Frieder
2019-07-08 8:49 ` Peng Fan
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