* [Patch v4 1/9] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` [Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format York Sun
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Doug Thompson,
mchehab, linux-kernel
On e500v1, read fault exception enable (RFXE) controls whether
assertion of core_fault_in causes a machine check interrupt.
Assertion of core_fault_in can result from uncorrectable data
error, such as an L2 multi-bit ECC error. It can also occur from
a system error if logic on the integrated device signals a fault
for nonfatal errors. RFXE bit is cleared out of reset, and should
be left clear for normal operation. Assertion of core_fault_in does
not cause a machine check.
RFXE is set specifically for RIO (Rapid IO) and PCI for book E to
catch the errors by machine check. With this bit set, EDAC driver
can't get the interrupt in case of uncorrectable error. So this
bit is cleared in favor of EDAC. However, the benefit of catching
such uncorrectable error doesn't outweigh the other errors which
may hang the system. Beside, e500v2 has different errors masked
by RFXE, and e500mc doesn't support this bit. It is more reasonable
to leave RFXE as is in EDAC driver, and leave the uncorrectable
errors triggering machine check for e500v1.
Signed-off-by: York Sun <york.sun@nxp.com>
Suggested-by: Scott Wood <oss@buserror.net>
---
Change log
v4: Fix typo in commit message
v3: Revise commit message
v2: new patch in this set
drivers/edac/mpc85xx_edac.c | 40 ----------------------------------------
1 file changed, 40 deletions(-)
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index ca63d0d..fdc3d9b 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -46,9 +46,6 @@ static u32 orig_pci_err_en;
#endif
static u32 orig_l2_err_disable;
-#ifdef CONFIG_FSL_SOC_BOOKE
-static u32 orig_hid1[2];
-#endif
/************************ MC SYSFS parts ***********************************/
@@ -1225,14 +1222,6 @@ static struct platform_driver mpc85xx_mc_err_driver = {
},
};
-#ifdef CONFIG_FSL_SOC_BOOKE
-static void __init mpc85xx_mc_clear_rfxe(void *data)
-{
- orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
- mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
-}
-#endif
-
static struct platform_driver * const drivers[] = {
&mpc85xx_mc_err_driver,
&mpc85xx_l2_err_driver,
@@ -1263,42 +1252,13 @@ static int __init mpc85xx_mc_init(void)
if (res)
printk(KERN_WARNING EDAC_MOD_STR "drivers fail to register\n");
-#ifdef CONFIG_FSL_SOC_BOOKE
- pvr = mfspr(SPRN_PVR);
-
- if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
- (PVR_VER(pvr) == PVR_VER_E500V2)) {
- /*
- * need to clear HID1[RFXE] to disable machine check int
- * so we can catch it
- */
- if (edac_op_state == EDAC_OPSTATE_INT)
- on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
- }
-#endif
-
return 0;
}
module_init(mpc85xx_mc_init);
-#ifdef CONFIG_FSL_SOC_BOOKE
-static void __exit mpc85xx_mc_restore_hid1(void *data)
-{
- mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
-}
-#endif
-
static void __exit mpc85xx_mc_exit(void)
{
-#ifdef CONFIG_FSL_SOC_BOOKE
- u32 pvr = mfspr(SPRN_PVR);
-
- if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
- (PVR_VER(pvr) == PVR_VER_E500V2)) {
- on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
- }
-#endif
platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
}
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
2016-08-09 21:55 ` [Patch v4 1/9] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1 York Sun
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx York Sun
` (5 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Doug Thompson,
mchehab, linux-kernel
Replace printk with more preferred pr_err/pr_warn/pr_info format.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: no change
v3: no change
v2: Reordered patch. Change more printk statement than v1 patch.
drivers/edac/mpc85xx_edac.c | 72 ++++++++++++++++++++++-----------------------
1 file changed, 35 insertions(+), 37 deletions(-)
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index fdc3d9b..c0b0951 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -157,18 +157,18 @@ static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
return;
}
- printk(KERN_ERR "PCI error(s) detected\n");
- printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
+ pr_err("PCI error(s) detected\n");
+ pr_err("PCI/X ERR_DR register: %#08x\n", err_detect);
- printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
+ pr_err("PCI/X ERR_ATTRIB register: %#08x\n",
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
- printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
+ pr_err("PCI/X ERR_ADDR register: %#08x\n",
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
- printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
+ pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n",
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
- printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
+ pr_err("PCI/X ERR_DL register: %#08x\n",
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
- printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
+ pr_err("PCI/X ERR_DH register: %#08x\n",
in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
/* clear error bits */
@@ -294,7 +294,7 @@ static int mpc85xx_pci_err_probe(struct platform_device *op)
res = of_address_to_resource(of_node, 0, &r);
if (res) {
- printk(KERN_ERR "%s: Unable to get resource for "
+ pr_err("%s: Unable to get resource for "
"PCI err regs\n", __func__);
goto err;
}
@@ -304,7 +304,7 @@ static int mpc85xx_pci_err_probe(struct platform_device *op)
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
pdata->name)) {
- printk(KERN_ERR "%s: Error while requesting mem region\n",
+ pr_err("%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
@@ -312,7 +312,7 @@ static int mpc85xx_pci_err_probe(struct platform_device *op)
pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
if (!pdata->pci_vbase) {
- printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
+ pr_err("%s: Unable to setup PCI err regs\n", __func__);
res = -ENOMEM;
goto err;
}
@@ -353,15 +353,14 @@ static int mpc85xx_pci_err_probe(struct platform_device *op)
IRQF_SHARED,
"[EDAC] PCI err", pci);
if (res < 0) {
- printk(KERN_ERR
- "%s: Unable to request irq %d for "
+ pr_err("%s: Unable to request irq %d for "
"MPC85xx PCI err\n", __func__, pdata->irq);
irq_dispose_mapping(pdata->irq);
res = -ENODEV;
goto err2;
}
- printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
+ pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n",
pdata->irq);
}
@@ -383,7 +382,7 @@ static int mpc85xx_pci_err_probe(struct platform_device *op)
devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
edac_dbg(3, "success\n");
- printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
+ pr_info(EDAC_MOD_STR " PCI err registered\n");
return 0;
@@ -526,17 +525,17 @@ static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
if (!(err_detect & L2_EDE_MASK))
return;
- printk(KERN_ERR "ECC Error in CPU L2 cache\n");
- printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
- printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
+ pr_err("ECC Error in CPU L2 cache\n");
+ pr_err("L2 Error Detect Register: 0x%08x\n", err_detect);
+ pr_err("L2 Error Capture Data High Register: 0x%08x\n",
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
- printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
+ pr_err("L2 Error Capture Data Lo Register: 0x%08x\n",
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
- printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
+ pr_err("L2 Error Syndrome Register: 0x%08x\n",
in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
- printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
+ pr_err("L2 Error Attributes Capture Register: 0x%08x\n",
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
- printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
+ pr_err("L2 Error Address Capture Register: 0x%08x\n",
in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
/* clear error detect register */
@@ -593,7 +592,7 @@ static int mpc85xx_l2_err_probe(struct platform_device *op)
res = of_address_to_resource(op->dev.of_node, 0, &r);
if (res) {
- printk(KERN_ERR "%s: Unable to get resource for "
+ pr_err("%s: Unable to get resource for "
"L2 err regs\n", __func__);
goto err;
}
@@ -603,7 +602,7 @@ static int mpc85xx_l2_err_probe(struct platform_device *op)
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
pdata->name)) {
- printk(KERN_ERR "%s: Error while requesting mem region\n",
+ pr_err("%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
@@ -611,7 +610,7 @@ static int mpc85xx_l2_err_probe(struct platform_device *op)
pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
if (!pdata->l2_vbase) {
- printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
+ pr_err("%s: Unable to setup L2 err regs\n", __func__);
res = -ENOMEM;
goto err;
}
@@ -643,15 +642,14 @@ static int mpc85xx_l2_err_probe(struct platform_device *op)
mpc85xx_l2_isr, IRQF_SHARED,
"[EDAC] L2 err", edac_dev);
if (res < 0) {
- printk(KERN_ERR
- "%s: Unable to request irq %d for "
+ pr_err("%s: Unable to request irq %d for "
"MPC85xx L2 err\n", __func__, pdata->irq);
irq_dispose_mapping(pdata->irq);
res = -ENODEV;
goto err2;
}
- printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
+ pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n",
pdata->irq);
edac_dev->op_state = OP_RUNNING_INTERRUPT;
@@ -662,7 +660,7 @@ static int mpc85xx_l2_err_probe(struct platform_device *op)
devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
edac_dbg(3, "success\n");
- printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
+ pr_info(EDAC_MOD_STR " L2 err registered\n");
return 0;
@@ -1064,14 +1062,14 @@ static int mpc85xx_mc_err_probe(struct platform_device *op)
res = of_address_to_resource(op->dev.of_node, 0, &r);
if (res) {
- printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
+ pr_err("%s: Unable to get resource for MC err regs\n",
__func__);
goto err;
}
if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
pdata->name)) {
- printk(KERN_ERR "%s: Error while requesting mem region\n",
+ pr_err("%s: Error while requesting mem region\n",
__func__);
res = -EBUSY;
goto err;
@@ -1079,7 +1077,7 @@ static int mpc85xx_mc_err_probe(struct platform_device *op)
pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
if (!pdata->mc_vbase) {
- printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
+ pr_err("%s: Unable to setup MC err regs\n", __func__);
res = -ENOMEM;
goto err;
}
@@ -1087,7 +1085,7 @@ static int mpc85xx_mc_err_probe(struct platform_device *op)
sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
if (!(sdram_ctl & DSC_ECC_EN)) {
/* no ECC */
- printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
+ pr_warn("%s: No ECC DIMMs discovered\n", __func__);
res = -ENODEV;
goto err;
}
@@ -1140,20 +1138,20 @@ static int mpc85xx_mc_err_probe(struct platform_device *op)
IRQF_SHARED,
"[EDAC] MC err", mci);
if (res < 0) {
- printk(KERN_ERR "%s: Unable to request irq %d for "
+ pr_err("%s: Unable to request irq %d for "
"MPC85xx DRAM ERR\n", __func__, pdata->irq);
irq_dispose_mapping(pdata->irq);
res = -ENODEV;
goto err2;
}
- printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
+ pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
pdata->irq);
}
devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
edac_dbg(3, "success\n");
- printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
+ pr_info(EDAC_MOD_STR " MC err registered\n");
return 0;
@@ -1235,7 +1233,7 @@ static int __init mpc85xx_mc_init(void)
int res = 0;
u32 __maybe_unused pvr = 0;
- printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
+ pr_info("Freescale(R) MPC85xx EDAC driver, "
"(C) 2006 Montavista Software\n");
/* make sure error reporting method is sane */
@@ -1250,7 +1248,7 @@ static int __init mpc85xx_mc_init(void)
res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
if (res)
- printk(KERN_WARNING EDAC_MOD_STR "drivers fail to register\n");
+ pr_warn(EDAC_MOD_STR "drivers fail to register\n");
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
2016-08-09 21:55 ` [Patch v4 1/9] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1 York Sun
2016-08-09 21:55 ` [Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format York Sun
@ 2016-08-09 21:55 ` York Sun
2016-08-11 13:36 ` Borislav Petkov
2016-08-09 21:55 ` [Patch v4 4/9] driver/edac/fsl_ddr: Rename macros and names York Sun
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Doug Thompson,
mchehab, linux-kernel
The mpc85xx compatible DDR controllers are used on ARM-based SoCs.
Separate the DDR part from mpc85xx EDAC driver and prepare to support
both architecture.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Change comment in file header
Use lower case "fsl_ddr_edac" for EDAC_MOD_STR
Drop exporting probe and remove symbols
v3: Fix compiling errors and warnings caused by patch ordering
v2: Reordered patch
Separate FSL DDR commont code as shared object, not another driver
This patch is generated with "git format-patch -M40 -C40" to show
copy-and-delete.
drivers/edac/Makefile | 5 +-
drivers/edac/{mpc85xx_edac.c => fsl_ddr_edac.c} | 701 +-----------------------
drivers/edac/{mpc85xx_edac.h => fsl_ddr_edac.h} | 110 +---
drivers/edac/mpc85xx_edac.c | 559 +------------------
drivers/edac/mpc85xx_edac.h | 66 ---
5 files changed, 28 insertions(+), 1413 deletions(-)
copy drivers/edac/{mpc85xx_edac.c => fsl_ddr_edac.c} (43%)
copy drivers/edac/{mpc85xx_edac.h => fsl_ddr_edac.h} (43%)
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index f9e4a3e..ee047a4 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -50,7 +50,10 @@ amd64_edac_mod-$(CONFIG_EDAC_AMD64_ERROR_INJECTION) += amd64_edac_inj.o
obj-$(CONFIG_EDAC_AMD64) += amd64_edac_mod.o
obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
-obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac.o
+
+mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
+obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
+
obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL) += cell_edac.o
obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/fsl_ddr_edac.c
similarity index 43%
copy from drivers/edac/mpc85xx_edac.c
copy to drivers/edac/fsl_ddr_edac.c
index c0b0951..ca7636f 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -1,5 +1,9 @@
/*
- * Freescale MPC85xx Memory Controller kernel module
+ * Freescale Memory Controller kernel module
+ *
+ * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
+ * ARM-based Layerscape SoCs including LS2xxx. Originally split
+ * out from mpc85xx_edac EDAC driver.
*
* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
*
@@ -20,33 +24,20 @@
#include <linux/edac.h>
#include <linux/smp.h>
#include <linux/gfp.h>
-#include <linux/fsl/edac.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include "edac_module.h"
#include "edac_core.h"
-#include "mpc85xx_edac.h"
+#include "fsl_ddr_edac.h"
+
+#define EDAC_MOD_STR "fsl_ddr_edac"
-static int edac_dev_idx;
-#ifdef CONFIG_PCI
-static int edac_pci_idx;
-#endif
static int edac_mc_idx;
static u32 orig_ddr_err_disable;
static u32 orig_ddr_err_sbe;
-/*
- * PCI Err defines
- */
-#ifdef CONFIG_PCI
-static u32 orig_pci_err_cap_dr;
-static u32 orig_pci_err_en;
-#endif
-
-static u32 orig_l2_err_disable;
-
/************************ MC SYSFS parts ***********************************/
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
@@ -141,589 +132,6 @@ static struct attribute *mpc85xx_dev_attrs[] = {
ATTRIBUTE_GROUPS(mpc85xx_dev);
-/**************************** PCI Err device ***************************/
-#ifdef CONFIG_PCI
-
-static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
-{
- struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
- u32 err_detect;
-
- err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
-
- /* master aborts can happen during PCI config cycles */
- if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
- return;
- }
-
- pr_err("PCI error(s) detected\n");
- pr_err("PCI/X ERR_DR register: %#08x\n", err_detect);
-
- pr_err("PCI/X ERR_ATTRIB register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
- pr_err("PCI/X ERR_ADDR register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
- pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
- pr_err("PCI/X ERR_DL register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
- pr_err("PCI/X ERR_DH register: %#08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
-
- /* clear error bits */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
-
- if (err_detect & PCI_EDE_PERR_MASK)
- edac_pci_handle_pe(pci, pci->ctl_name);
-
- if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
- edac_pci_handle_npe(pci, pci->ctl_name);
-}
-
-static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
-{
- struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
- u32 err_detect;
-
- err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
-
- pr_err("PCIe error(s) detected\n");
- pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
- pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR));
- pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
- pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
- pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
- pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
- in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
-
- /* clear error bits */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
-}
-
-static int mpc85xx_pcie_find_capability(struct device_node *np)
-{
- struct pci_controller *hose;
-
- if (!np)
- return -EINVAL;
-
- hose = pci_find_hose_for_OF_device(np);
-
- return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
-}
-
-static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
-{
- struct edac_pci_ctl_info *pci = dev_id;
- struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
- u32 err_detect;
-
- err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
-
- if (!err_detect)
- return IRQ_NONE;
-
- if (pdata->is_pcie)
- mpc85xx_pcie_check(pci);
- else
- mpc85xx_pci_check(pci);
-
- return IRQ_HANDLED;
-}
-
-static int mpc85xx_pci_err_probe(struct platform_device *op)
-{
- struct edac_pci_ctl_info *pci;
- struct mpc85xx_pci_pdata *pdata;
- struct mpc85xx_edac_pci_plat_data *plat_data;
- struct device_node *of_node;
- struct resource r;
- int res = 0;
-
- if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
- return -ENOMEM;
-
- pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
- if (!pci)
- return -ENOMEM;
-
- /* make sure error reporting method is sane */
- switch (edac_op_state) {
- case EDAC_OPSTATE_POLL:
- case EDAC_OPSTATE_INT:
- break;
- default:
- edac_op_state = EDAC_OPSTATE_INT;
- break;
- }
-
- pdata = pci->pvt_info;
- pdata->name = "mpc85xx_pci_err";
- pdata->irq = NO_IRQ;
-
- plat_data = op->dev.platform_data;
- if (!plat_data) {
- dev_err(&op->dev, "no platform data");
- res = -ENXIO;
- goto err;
- }
- of_node = plat_data->of_node;
-
- if (mpc85xx_pcie_find_capability(of_node) > 0)
- pdata->is_pcie = true;
-
- dev_set_drvdata(&op->dev, pci);
- pci->dev = &op->dev;
- pci->mod_name = EDAC_MOD_STR;
- pci->ctl_name = pdata->name;
- pci->dev_name = dev_name(&op->dev);
-
- if (edac_op_state == EDAC_OPSTATE_POLL) {
- if (pdata->is_pcie)
- pci->edac_check = mpc85xx_pcie_check;
- else
- pci->edac_check = mpc85xx_pci_check;
- }
-
- pdata->edac_idx = edac_pci_idx++;
-
- res = of_address_to_resource(of_node, 0, &r);
- if (res) {
- pr_err("%s: Unable to get resource for "
- "PCI err regs\n", __func__);
- goto err;
- }
-
- /* we only need the error registers */
- r.start += 0xe00;
-
- if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
- pdata->name)) {
- pr_err("%s: Error while requesting mem region\n",
- __func__);
- res = -EBUSY;
- goto err;
- }
-
- pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
- if (!pdata->pci_vbase) {
- pr_err("%s: Unable to setup PCI err regs\n", __func__);
- res = -ENOMEM;
- goto err;
- }
-
- if (pdata->is_pcie) {
- orig_pci_err_cap_dr =
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
- orig_pci_err_en =
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
- } else {
- orig_pci_err_cap_dr =
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
-
- /* PCI master abort is expected during config cycles */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
-
- orig_pci_err_en =
- in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
-
- /* disable master abort reporting */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
- }
-
- /* clear error bits */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
-
- if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
- edac_dbg(3, "failed edac_pci_add_device()\n");
- goto err;
- }
-
- if (edac_op_state == EDAC_OPSTATE_INT) {
- pdata->irq = irq_of_parse_and_map(of_node, 0);
- res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_pci_isr,
- IRQF_SHARED,
- "[EDAC] PCI err", pci);
- if (res < 0) {
- pr_err("%s: Unable to request irq %d for "
- "MPC85xx PCI err\n", __func__, pdata->irq);
- irq_dispose_mapping(pdata->irq);
- res = -ENODEV;
- goto err2;
- }
-
- pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n",
- pdata->irq);
- }
-
- if (pdata->is_pcie) {
- /*
- * Enable all PCIe error interrupt & error detect except invalid
- * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
- * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
- * detection enable bit. Because PCIe bus code to initialize and
- * configure these PCIe devices on booting will use some invalid
- * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
- * notice information. So disable this detect to fix ugly print.
- */
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
- & ~PEX_ERR_ICCAIE_EN_BIT);
- out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
- | PEX_ERR_ICCAD_DISR_BIT);
- }
-
- devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
- edac_dbg(3, "success\n");
- pr_info(EDAC_MOD_STR " PCI err registered\n");
-
- return 0;
-
-err2:
- edac_pci_del_device(&op->dev);
-err:
- edac_pci_free_ctl_info(pci);
- devres_release_group(&op->dev, mpc85xx_pci_err_probe);
- return res;
-}
-
-static const struct platform_device_id mpc85xx_pci_err_match[] = {
- {
- .name = "mpc85xx-pci-edac"
- },
- {}
-};
-
-static struct platform_driver mpc85xx_pci_err_driver = {
- .probe = mpc85xx_pci_err_probe,
- .id_table = mpc85xx_pci_err_match,
- .driver = {
- .name = "mpc85xx_pci_err",
- .suppress_bind_attrs = true,
- },
-};
-#endif /* CONFIG_PCI */
-
-/**************************** L2 Err device ***************************/
-
-/************************ L2 SYSFS parts ***********************************/
-
-static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
- *edac_dev, char *data)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- return sprintf(data, "0x%08x",
- in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
-}
-
-static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
- *edac_dev, char *data)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- return sprintf(data, "0x%08x",
- in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
-}
-
-static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
- *edac_dev, char *data)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- return sprintf(data, "0x%08x",
- in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
-}
-
-static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
- *edac_dev, const char *data,
- size_t count)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- if (isdigit(*data)) {
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
- simple_strtoul(data, NULL, 0));
- return count;
- }
- return 0;
-}
-
-static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
- *edac_dev, const char *data,
- size_t count)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- if (isdigit(*data)) {
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
- simple_strtoul(data, NULL, 0));
- return count;
- }
- return 0;
-}
-
-static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
- *edac_dev, const char *data,
- size_t count)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- if (isdigit(*data)) {
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
- simple_strtoul(data, NULL, 0));
- return count;
- }
- return 0;
-}
-
-static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
- {
- .attr = {
- .name = "inject_data_hi",
- .mode = (S_IRUGO | S_IWUSR)
- },
- .show = mpc85xx_l2_inject_data_hi_show,
- .store = mpc85xx_l2_inject_data_hi_store},
- {
- .attr = {
- .name = "inject_data_lo",
- .mode = (S_IRUGO | S_IWUSR)
- },
- .show = mpc85xx_l2_inject_data_lo_show,
- .store = mpc85xx_l2_inject_data_lo_store},
- {
- .attr = {
- .name = "inject_ctrl",
- .mode = (S_IRUGO | S_IWUSR)
- },
- .show = mpc85xx_l2_inject_ctrl_show,
- .store = mpc85xx_l2_inject_ctrl_store},
-
- /* End of list */
- {
- .attr = {.name = NULL}
- }
-};
-
-static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
- *edac_dev)
-{
- edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
-}
-
-/***************************** L2 ops ***********************************/
-
-static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
-{
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- u32 err_detect;
-
- err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
-
- if (!(err_detect & L2_EDE_MASK))
- return;
-
- pr_err("ECC Error in CPU L2 cache\n");
- pr_err("L2 Error Detect Register: 0x%08x\n", err_detect);
- pr_err("L2 Error Capture Data High Register: 0x%08x\n",
- in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
- pr_err("L2 Error Capture Data Lo Register: 0x%08x\n",
- in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
- pr_err("L2 Error Syndrome Register: 0x%08x\n",
- in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
- pr_err("L2 Error Attributes Capture Register: 0x%08x\n",
- in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
- pr_err("L2 Error Address Capture Register: 0x%08x\n",
- in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
-
- /* clear error detect register */
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
-
- if (err_detect & L2_EDE_CE_MASK)
- edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
-
- if (err_detect & L2_EDE_UE_MASK)
- edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
-}
-
-static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
-{
- struct edac_device_ctl_info *edac_dev = dev_id;
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
- u32 err_detect;
-
- err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
-
- if (!(err_detect & L2_EDE_MASK))
- return IRQ_NONE;
-
- mpc85xx_l2_check(edac_dev);
-
- return IRQ_HANDLED;
-}
-
-static int mpc85xx_l2_err_probe(struct platform_device *op)
-{
- struct edac_device_ctl_info *edac_dev;
- struct mpc85xx_l2_pdata *pdata;
- struct resource r;
- int res;
-
- if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
- return -ENOMEM;
-
- edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
- "cpu", 1, "L", 1, 2, NULL, 0,
- edac_dev_idx);
- if (!edac_dev) {
- devres_release_group(&op->dev, mpc85xx_l2_err_probe);
- return -ENOMEM;
- }
-
- pdata = edac_dev->pvt_info;
- pdata->name = "mpc85xx_l2_err";
- pdata->irq = NO_IRQ;
- edac_dev->dev = &op->dev;
- dev_set_drvdata(edac_dev->dev, edac_dev);
- edac_dev->ctl_name = pdata->name;
- edac_dev->dev_name = pdata->name;
-
- res = of_address_to_resource(op->dev.of_node, 0, &r);
- if (res) {
- pr_err("%s: Unable to get resource for "
- "L2 err regs\n", __func__);
- goto err;
- }
-
- /* we only need the error registers */
- r.start += 0xe00;
-
- if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
- pdata->name)) {
- pr_err("%s: Error while requesting mem region\n",
- __func__);
- res = -EBUSY;
- goto err;
- }
-
- pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
- if (!pdata->l2_vbase) {
- pr_err("%s: Unable to setup L2 err regs\n", __func__);
- res = -ENOMEM;
- goto err;
- }
-
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
-
- orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
-
- /* clear the err_dis */
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
-
- edac_dev->mod_name = EDAC_MOD_STR;
-
- if (edac_op_state == EDAC_OPSTATE_POLL)
- edac_dev->edac_check = mpc85xx_l2_check;
-
- mpc85xx_set_l2_sysfs_attributes(edac_dev);
-
- pdata->edac_idx = edac_dev_idx++;
-
- if (edac_device_add_device(edac_dev) > 0) {
- edac_dbg(3, "failed edac_device_add_device()\n");
- goto err;
- }
-
- if (edac_op_state == EDAC_OPSTATE_INT) {
- pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
- res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_l2_isr, IRQF_SHARED,
- "[EDAC] L2 err", edac_dev);
- if (res < 0) {
- pr_err("%s: Unable to request irq %d for "
- "MPC85xx L2 err\n", __func__, pdata->irq);
- irq_dispose_mapping(pdata->irq);
- res = -ENODEV;
- goto err2;
- }
-
- pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n",
- pdata->irq);
-
- edac_dev->op_state = OP_RUNNING_INTERRUPT;
-
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
- }
-
- devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
-
- edac_dbg(3, "success\n");
- pr_info(EDAC_MOD_STR " L2 err registered\n");
-
- return 0;
-
-err2:
- edac_device_del_device(&op->dev);
-err:
- devres_release_group(&op->dev, mpc85xx_l2_err_probe);
- edac_device_free_ctl_info(edac_dev);
- return res;
-}
-
-static int mpc85xx_l2_err_remove(struct platform_device *op)
-{
- struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
- struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
-
- edac_dbg(0, "\n");
-
- if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
- irq_dispose_mapping(pdata->irq);
- }
-
- out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
- edac_device_del_device(&op->dev);
- edac_device_free_ctl_info(edac_dev);
- return 0;
-}
-
-static const struct of_device_id mpc85xx_l2_err_of_match[] = {
-/* deprecate the fsl,85.. forms in the future, 2.6.30? */
- { .compatible = "fsl,8540-l2-cache-controller", },
- { .compatible = "fsl,8541-l2-cache-controller", },
- { .compatible = "fsl,8544-l2-cache-controller", },
- { .compatible = "fsl,8548-l2-cache-controller", },
- { .compatible = "fsl,8555-l2-cache-controller", },
- { .compatible = "fsl,8568-l2-cache-controller", },
- { .compatible = "fsl,mpc8536-l2-cache-controller", },
- { .compatible = "fsl,mpc8540-l2-cache-controller", },
- { .compatible = "fsl,mpc8541-l2-cache-controller", },
- { .compatible = "fsl,mpc8544-l2-cache-controller", },
- { .compatible = "fsl,mpc8548-l2-cache-controller", },
- { .compatible = "fsl,mpc8555-l2-cache-controller", },
- { .compatible = "fsl,mpc8560-l2-cache-controller", },
- { .compatible = "fsl,mpc8568-l2-cache-controller", },
- { .compatible = "fsl,mpc8569-l2-cache-controller", },
- { .compatible = "fsl,mpc8572-l2-cache-controller", },
- { .compatible = "fsl,p1020-l2-cache-controller", },
- { .compatible = "fsl,p1021-l2-cache-controller", },
- { .compatible = "fsl,p2020-l2-cache-controller", },
- {},
-};
-MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
-
-static struct platform_driver mpc85xx_l2_err_driver = {
- .probe = mpc85xx_l2_err_probe,
- .remove = mpc85xx_l2_err_remove,
- .driver = {
- .name = "mpc85xx_l2_err",
- .of_match_table = mpc85xx_l2_err_of_match,
- },
-};
-
/**************************** MC Err device ***************************/
/*
@@ -1026,7 +434,7 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
}
}
-static int mpc85xx_mc_err_probe(struct platform_device *op)
+int mpc85xx_mc_err_probe(struct platform_device *op)
{
struct mem_ctl_info *mci;
struct edac_mc_layer layers[2];
@@ -1096,7 +504,6 @@ static int mpc85xx_mc_err_probe(struct platform_device *op)
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->mod_name = EDAC_MOD_STR;
- mci->mod_ver = MPC85XX_REVISION;
if (edac_op_state == EDAC_OPSTATE_POLL)
mci->edac_check = mpc85xx_mc_check;
@@ -1138,8 +545,8 @@ static int mpc85xx_mc_err_probe(struct platform_device *op)
IRQF_SHARED,
"[EDAC] MC err", mci);
if (res < 0) {
- pr_err("%s: Unable to request irq %d for "
- "MPC85xx DRAM ERR\n", __func__, pdata->irq);
+ pr_err("%s: Unable to request irq %d for MPC85xx DRAM ERR\n",
+ __func__, pdata->irq);
irq_dispose_mapping(pdata->irq);
res = -ENODEV;
goto err2;
@@ -1163,7 +570,7 @@ err:
return res;
}
-static int mpc85xx_mc_err_remove(struct platform_device *op)
+int mpc85xx_mc_err_remove(struct platform_device *op)
{
struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
@@ -1183,87 +590,3 @@ static int mpc85xx_mc_err_remove(struct platform_device *op)
edac_mc_free(mci);
return 0;
}
-
-static const struct of_device_id mpc85xx_mc_err_of_match[] = {
-/* deprecate the fsl,85.. forms in the future, 2.6.30? */
- { .compatible = "fsl,8540-memory-controller", },
- { .compatible = "fsl,8541-memory-controller", },
- { .compatible = "fsl,8544-memory-controller", },
- { .compatible = "fsl,8548-memory-controller", },
- { .compatible = "fsl,8555-memory-controller", },
- { .compatible = "fsl,8568-memory-controller", },
- { .compatible = "fsl,mpc8536-memory-controller", },
- { .compatible = "fsl,mpc8540-memory-controller", },
- { .compatible = "fsl,mpc8541-memory-controller", },
- { .compatible = "fsl,mpc8544-memory-controller", },
- { .compatible = "fsl,mpc8548-memory-controller", },
- { .compatible = "fsl,mpc8555-memory-controller", },
- { .compatible = "fsl,mpc8560-memory-controller", },
- { .compatible = "fsl,mpc8568-memory-controller", },
- { .compatible = "fsl,mpc8569-memory-controller", },
- { .compatible = "fsl,mpc8572-memory-controller", },
- { .compatible = "fsl,mpc8349-memory-controller", },
- { .compatible = "fsl,p1020-memory-controller", },
- { .compatible = "fsl,p1021-memory-controller", },
- { .compatible = "fsl,p2020-memory-controller", },
- { .compatible = "fsl,qoriq-memory-controller", },
- {},
-};
-MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
-
-static struct platform_driver mpc85xx_mc_err_driver = {
- .probe = mpc85xx_mc_err_probe,
- .remove = mpc85xx_mc_err_remove,
- .driver = {
- .name = "mpc85xx_mc_err",
- .of_match_table = mpc85xx_mc_err_of_match,
- },
-};
-
-static struct platform_driver * const drivers[] = {
- &mpc85xx_mc_err_driver,
- &mpc85xx_l2_err_driver,
-#ifdef CONFIG_PCI
- &mpc85xx_pci_err_driver,
-#endif
-};
-
-static int __init mpc85xx_mc_init(void)
-{
- int res = 0;
- u32 __maybe_unused pvr = 0;
-
- pr_info("Freescale(R) MPC85xx EDAC driver, "
- "(C) 2006 Montavista Software\n");
-
- /* make sure error reporting method is sane */
- switch (edac_op_state) {
- case EDAC_OPSTATE_POLL:
- case EDAC_OPSTATE_INT:
- break;
- default:
- edac_op_state = EDAC_OPSTATE_INT;
- break;
- }
-
- res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
- if (res)
- pr_warn(EDAC_MOD_STR "drivers fail to register\n");
-
- return 0;
-}
-
-module_init(mpc85xx_mc_init);
-
-static void __exit mpc85xx_mc_exit(void)
-{
- platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
-}
-
-module_exit(mpc85xx_mc_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Montavista Software, Inc.");
-module_param(edac_op_state, int, 0444);
-MODULE_PARM_DESC(edac_op_state,
- "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/fsl_ddr_edac.h
similarity index 43%
copy from drivers/edac/mpc85xx_edac.h
copy to drivers/edac/fsl_ddr_edac.h
index 9352e88..2f2c2b1 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -1,5 +1,10 @@
/*
- * Freescale MPC85xx Memory Controller kernel module
+ * Freescale Memory Controller kernel module
+ *
+ * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
+ * ARM-based Layerscape SoCs including LS2xxx. Originally split
+ * out from mpc85xx_edac EDAC driver.
+ *
* Author: Dave Jiang <djiang@mvista.com>
*
* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
@@ -8,17 +13,11 @@
* or implied.
*
*/
-#ifndef _MPC85XX_EDAC_H_
-#define _MPC85XX_EDAC_H_
-
-#define MPC85XX_REVISION " Ver: 2.0.0"
-#define EDAC_MOD_STR "MPC85xx_edac"
-
-#define mpc85xx_printk(level, fmt, arg...) \
- edac_printk(level, "MPC85xx", fmt, ##arg)
+#ifndef _FSL_DDR_EDAC_H_
+#define _FSL_DDR_EDAC_H_
#define mpc85xx_mc_printk(mci, level, fmt, arg...) \
- edac_mc_chipset_printk(mci, level, "MPC85xx", fmt, ##arg)
+ edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
/*
* DRAM error defines
@@ -76,99 +75,12 @@
#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
-/*
- * L2 Err defines
- */
-#define MPC85XX_L2_ERRINJHI 0x0000
-#define MPC85XX_L2_ERRINJLO 0x0004
-#define MPC85XX_L2_ERRINJCTL 0x0008
-#define MPC85XX_L2_CAPTDATAHI 0x0020
-#define MPC85XX_L2_CAPTDATALO 0x0024
-#define MPC85XX_L2_CAPTECC 0x0028
-#define MPC85XX_L2_ERRDET 0x0040
-#define MPC85XX_L2_ERRDIS 0x0044
-#define MPC85XX_L2_ERRINTEN 0x0048
-#define MPC85XX_L2_ERRATTR 0x004c
-#define MPC85XX_L2_ERRADDR 0x0050
-#define MPC85XX_L2_ERRCTL 0x0058
-
-/* Error Interrupt Enable */
-#define L2_EIE_L2CFGINTEN 0x1
-#define L2_EIE_SBECCINTEN 0x4
-#define L2_EIE_MBECCINTEN 0x8
-#define L2_EIE_TPARINTEN 0x10
-#define L2_EIE_MASK (L2_EIE_L2CFGINTEN | L2_EIE_SBECCINTEN | \
- L2_EIE_MBECCINTEN | L2_EIE_TPARINTEN)
-
-/* Error Detect */
-#define L2_EDE_L2CFGERR 0x1
-#define L2_EDE_SBECCERR 0x4
-#define L2_EDE_MBECCERR 0x8
-#define L2_EDE_TPARERR 0x10
-#define L2_EDE_MULL2ERR 0x80000000
-
-#define L2_EDE_CE_MASK L2_EDE_SBECCERR
-#define L2_EDE_UE_MASK (L2_EDE_L2CFGERR | L2_EDE_MBECCERR | \
- L2_EDE_TPARERR)
-#define L2_EDE_MASK (L2_EDE_L2CFGERR | L2_EDE_SBECCERR | \
- L2_EDE_MBECCERR | L2_EDE_TPARERR | L2_EDE_MULL2ERR)
-
-/*
- * PCI Err defines
- */
-#define PCI_EDE_TOE 0x00000001
-#define PCI_EDE_SCM 0x00000002
-#define PCI_EDE_IRMSV 0x00000004
-#define PCI_EDE_ORMSV 0x00000008
-#define PCI_EDE_OWMSV 0x00000010
-#define PCI_EDE_TGT_ABRT 0x00000020
-#define PCI_EDE_MST_ABRT 0x00000040
-#define PCI_EDE_TGT_PERR 0x00000080
-#define PCI_EDE_MST_PERR 0x00000100
-#define PCI_EDE_RCVD_SERR 0x00000200
-#define PCI_EDE_ADDR_PERR 0x00000400
-#define PCI_EDE_MULTI_ERR 0x80000000
-
-#define PCI_EDE_PERR_MASK (PCI_EDE_TGT_PERR | PCI_EDE_MST_PERR | \
- PCI_EDE_ADDR_PERR)
-
-#define MPC85XX_PCI_ERR_DR 0x0000
-#define MPC85XX_PCI_ERR_CAP_DR 0x0004
-#define MPC85XX_PCI_ERR_EN 0x0008
-#define PEX_ERR_ICCAIE_EN_BIT 0x00020000
-#define MPC85XX_PCI_ERR_ATTRIB 0x000c
-#define MPC85XX_PCI_ERR_ADDR 0x0010
-#define PEX_ERR_ICCAD_DISR_BIT 0x00020000
-#define MPC85XX_PCI_ERR_EXT_ADDR 0x0014
-#define MPC85XX_PCI_ERR_DL 0x0018
-#define MPC85XX_PCI_ERR_DH 0x001c
-#define MPC85XX_PCI_GAS_TIMR 0x0020
-#define MPC85XX_PCI_PCIX_TIMR 0x0024
-#define MPC85XX_PCIE_ERR_CAP_R0 0x0028
-#define MPC85XX_PCIE_ERR_CAP_R1 0x002c
-#define MPC85XX_PCIE_ERR_CAP_R2 0x0030
-#define MPC85XX_PCIE_ERR_CAP_R3 0x0034
-
struct mpc85xx_mc_pdata {
char *name;
int edac_idx;
void __iomem *mc_vbase;
int irq;
};
-
-struct mpc85xx_l2_pdata {
- char *name;
- int edac_idx;
- void __iomem *l2_vbase;
- int irq;
-};
-
-struct mpc85xx_pci_pdata {
- char *name;
- bool is_pcie;
- int edac_idx;
- void __iomem *pci_vbase;
- int irq;
-};
-
+int mpc85xx_mc_err_probe(struct platform_device *op);
+int mpc85xx_mc_err_remove(struct platform_device *op);
#endif
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index c0b0951..af9ce77 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -27,15 +27,12 @@
#include "edac_module.h"
#include "edac_core.h"
#include "mpc85xx_edac.h"
+#include "fsl_ddr_edac.h"
static int edac_dev_idx;
#ifdef CONFIG_PCI
static int edac_pci_idx;
#endif
-static int edac_mc_idx;
-
-static u32 orig_ddr_err_disable;
-static u32 orig_ddr_err_sbe;
/*
* PCI Err defines
@@ -47,100 +44,6 @@ static u32 orig_pci_err_en;
static u32 orig_l2_err_disable;
-/************************ MC SYSFS parts ***********************************/
-
-#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
-
-static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
- struct device_attribute *mattr,
- char *data)
-{
- struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase +
- MPC85XX_MC_DATA_ERR_INJECT_HI));
-}
-
-static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
- struct device_attribute *mattr,
- char *data)
-{
- struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase +
- MPC85XX_MC_DATA_ERR_INJECT_LO));
-}
-
-static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
- struct device_attribute *mattr,
- char *data)
-{
- struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
-}
-
-static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
- struct device_attribute *mattr,
- const char *data, size_t count)
-{
- struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
- simple_strtoul(data, NULL, 0));
- return count;
- }
- return 0;
-}
-
-static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
- struct device_attribute *mattr,
- const char *data, size_t count)
-{
- struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
- simple_strtoul(data, NULL, 0));
- return count;
- }
- return 0;
-}
-
-static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
- struct device_attribute *mattr,
- const char *data, size_t count)
-{
- struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
- simple_strtoul(data, NULL, 0));
- return count;
- }
- return 0;
-}
-
-DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
- mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
-DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
- mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
-DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
- mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
-
-static struct attribute *mpc85xx_dev_attrs[] = {
- &dev_attr_inject_data_hi.attr,
- &dev_attr_inject_data_lo.attr,
- &dev_attr_inject_ctrl.attr,
- NULL
-};
-
-ATTRIBUTE_GROUPS(mpc85xx_dev);
-
/**************************** PCI Err device ***************************/
#ifdef CONFIG_PCI
@@ -724,466 +627,6 @@ static struct platform_driver mpc85xx_l2_err_driver = {
},
};
-/**************************** MC Err device ***************************/
-
-/*
- * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
- * MPC8572 User's Manual. Each line represents a syndrome bit column as a
- * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
- * below correspond to Freescale's manuals.
- */
-static unsigned int ecc_table[16] = {
- /* MSB LSB */
- /* [0:31] [32:63] */
- 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
- 0x00ff00ff, 0x00fff0ff,
- 0x0f0f0f0f, 0x0f0fff00,
- 0x11113333, 0x7777000f,
- 0x22224444, 0x8888222f,
- 0x44448888, 0xffff4441,
- 0x8888ffff, 0x11118882,
- 0xffff1111, 0x22221114, /* Syndrome bit 0 */
-};
-
-/*
- * Calculate the correct ECC value for a 64-bit value specified by high:low
- */
-static u8 calculate_ecc(u32 high, u32 low)
-{
- u32 mask_low;
- u32 mask_high;
- int bit_cnt;
- u8 ecc = 0;
- int i;
- int j;
-
- for (i = 0; i < 8; i++) {
- mask_high = ecc_table[i * 2];
- mask_low = ecc_table[i * 2 + 1];
- bit_cnt = 0;
-
- for (j = 0; j < 32; j++) {
- if ((mask_high >> j) & 1)
- bit_cnt ^= (high >> j) & 1;
- if ((mask_low >> j) & 1)
- bit_cnt ^= (low >> j) & 1;
- }
-
- ecc |= bit_cnt << i;
- }
-
- return ecc;
-}
-
-/*
- * Create the syndrome code which is generated if the data line specified by
- * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
- * User's Manual and 9-61 in the MPC8572 User's Manual.
- */
-static u8 syndrome_from_bit(unsigned int bit) {
- int i;
- u8 syndrome = 0;
-
- /*
- * Cycle through the upper or lower 32-bit portion of each value in
- * ecc_table depending on if 'bit' is in the upper or lower half of
- * 64-bit data.
- */
- for (i = bit < 32; i < 16; i += 2)
- syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
-
- return syndrome;
-}
-
-/*
- * Decode data and ecc syndrome to determine what went wrong
- * Note: This can only decode single-bit errors
- */
-static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
- int *bad_data_bit, int *bad_ecc_bit)
-{
- int i;
- u8 syndrome;
-
- *bad_data_bit = -1;
- *bad_ecc_bit = -1;
-
- /*
- * Calculate the ECC of the captured data and XOR it with the captured
- * ECC to find an ECC syndrome value we can search for
- */
- syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
-
- /* Check if a data line is stuck... */
- for (i = 0; i < 64; i++) {
- if (syndrome == syndrome_from_bit(i)) {
- *bad_data_bit = i;
- return;
- }
- }
-
- /* If data is correct, check ECC bits for errors... */
- for (i = 0; i < 8; i++) {
- if ((syndrome >> i) & 0x1) {
- *bad_ecc_bit = i;
- return;
- }
- }
-}
-
-#define make64(high, low) (((u64)(high) << 32) | (low))
-
-static void mpc85xx_mc_check(struct mem_ctl_info *mci)
-{
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- struct csrow_info *csrow;
- u32 bus_width;
- u32 err_detect;
- u32 syndrome;
- u64 err_addr;
- u32 pfn;
- int row_index;
- u32 cap_high;
- u32 cap_low;
- int bad_data_bit;
- int bad_ecc_bit;
-
- err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
- if (!err_detect)
- return;
-
- mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
- err_detect);
-
- /* no more processing if not ECC bit errors */
- if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
- return;
- }
-
- syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
-
- /* Mask off appropriate bits of syndrome based on bus width */
- bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
- DSC_DBW_MASK) ? 32 : 64;
- if (bus_width == 64)
- syndrome &= 0xff;
- else
- syndrome &= 0xffff;
-
- err_addr = make64(
- in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS),
- in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS));
- pfn = err_addr >> PAGE_SHIFT;
-
- for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
- csrow = mci->csrows[row_index];
- if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
- break;
- }
-
- cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
- cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
-
- /*
- * Analyze single-bit errors on 64-bit wide buses
- * TODO: Add support for 32-bit wide buses
- */
- if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
- sbe_ecc_decode(cap_high, cap_low, syndrome,
- &bad_data_bit, &bad_ecc_bit);
-
- if (bad_data_bit != -1)
- mpc85xx_mc_printk(mci, KERN_ERR,
- "Faulty Data bit: %d\n", bad_data_bit);
- if (bad_ecc_bit != -1)
- mpc85xx_mc_printk(mci, KERN_ERR,
- "Faulty ECC bit: %d\n", bad_ecc_bit);
-
- mpc85xx_mc_printk(mci, KERN_ERR,
- "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
- cap_high ^ (1 << (bad_data_bit - 32)),
- cap_low ^ (1 << bad_data_bit),
- syndrome ^ (1 << bad_ecc_bit));
- }
-
- mpc85xx_mc_printk(mci, KERN_ERR,
- "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
- cap_high, cap_low, syndrome);
- mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
- mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
-
- /* we are out of range */
- if (row_index == mci->nr_csrows)
- mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
-
- if (err_detect & DDR_EDE_SBE)
- edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
- pfn, err_addr & ~PAGE_MASK, syndrome,
- row_index, 0, -1,
- mci->ctl_name, "");
-
- if (err_detect & DDR_EDE_MBE)
- edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
- pfn, err_addr & ~PAGE_MASK, syndrome,
- row_index, 0, -1,
- mci->ctl_name, "");
-
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
-}
-
-static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
-{
- struct mem_ctl_info *mci = dev_id;
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- u32 err_detect;
-
- err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
- if (!err_detect)
- return IRQ_NONE;
-
- mpc85xx_mc_check(mci);
-
- return IRQ_HANDLED;
-}
-
-static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
-{
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
- struct csrow_info *csrow;
- struct dimm_info *dimm;
- u32 sdram_ctl;
- u32 sdtype;
- enum mem_type mtype;
- u32 cs_bnds;
- int index;
-
- sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
-
- sdtype = sdram_ctl & DSC_SDTYPE_MASK;
- if (sdram_ctl & DSC_RD_EN) {
- switch (sdtype) {
- case DSC_SDTYPE_DDR:
- mtype = MEM_RDDR;
- break;
- case DSC_SDTYPE_DDR2:
- mtype = MEM_RDDR2;
- break;
- case DSC_SDTYPE_DDR3:
- mtype = MEM_RDDR3;
- break;
- default:
- mtype = MEM_UNKNOWN;
- break;
- }
- } else {
- switch (sdtype) {
- case DSC_SDTYPE_DDR:
- mtype = MEM_DDR;
- break;
- case DSC_SDTYPE_DDR2:
- mtype = MEM_DDR2;
- break;
- case DSC_SDTYPE_DDR3:
- mtype = MEM_DDR3;
- break;
- default:
- mtype = MEM_UNKNOWN;
- break;
- }
- }
-
- for (index = 0; index < mci->nr_csrows; index++) {
- u32 start;
- u32 end;
-
- csrow = mci->csrows[index];
- dimm = csrow->channels[0]->dimm;
-
- cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
- (index * MPC85XX_MC_CS_BNDS_OFS));
-
- start = (cs_bnds & 0xffff0000) >> 16;
- end = (cs_bnds & 0x0000ffff);
-
- if (start == end)
- continue; /* not populated */
-
- start <<= (24 - PAGE_SHIFT);
- end <<= (24 - PAGE_SHIFT);
- end |= (1 << (24 - PAGE_SHIFT)) - 1;
-
- csrow->first_page = start;
- csrow->last_page = end;
-
- dimm->nr_pages = end + 1 - start;
- dimm->grain = 8;
- dimm->mtype = mtype;
- dimm->dtype = DEV_UNKNOWN;
- if (sdram_ctl & DSC_X32_EN)
- dimm->dtype = DEV_X32;
- dimm->edac_mode = EDAC_SECDED;
- }
-}
-
-static int mpc85xx_mc_err_probe(struct platform_device *op)
-{
- struct mem_ctl_info *mci;
- struct edac_mc_layer layers[2];
- struct mpc85xx_mc_pdata *pdata;
- struct resource r;
- u32 sdram_ctl;
- int res;
-
- if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
- return -ENOMEM;
-
- layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
- layers[0].size = 4;
- layers[0].is_virt_csrow = true;
- layers[1].type = EDAC_MC_LAYER_CHANNEL;
- layers[1].size = 1;
- layers[1].is_virt_csrow = false;
- mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
- sizeof(*pdata));
- if (!mci) {
- devres_release_group(&op->dev, mpc85xx_mc_err_probe);
- return -ENOMEM;
- }
-
- pdata = mci->pvt_info;
- pdata->name = "mpc85xx_mc_err";
- pdata->irq = NO_IRQ;
- mci->pdev = &op->dev;
- pdata->edac_idx = edac_mc_idx++;
- dev_set_drvdata(mci->pdev, mci);
- mci->ctl_name = pdata->name;
- mci->dev_name = pdata->name;
-
- res = of_address_to_resource(op->dev.of_node, 0, &r);
- if (res) {
- pr_err("%s: Unable to get resource for MC err regs\n",
- __func__);
- goto err;
- }
-
- if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
- pdata->name)) {
- pr_err("%s: Error while requesting mem region\n",
- __func__);
- res = -EBUSY;
- goto err;
- }
-
- pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
- if (!pdata->mc_vbase) {
- pr_err("%s: Unable to setup MC err regs\n", __func__);
- res = -ENOMEM;
- goto err;
- }
-
- sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
- if (!(sdram_ctl & DSC_ECC_EN)) {
- /* no ECC */
- pr_warn("%s: No ECC DIMMs discovered\n", __func__);
- res = -ENODEV;
- goto err;
- }
-
- edac_dbg(3, "init mci\n");
- mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
- MEM_FLAG_DDR | MEM_FLAG_DDR2;
- mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
- mci->edac_cap = EDAC_FLAG_SECDED;
- mci->mod_name = EDAC_MOD_STR;
- mci->mod_ver = MPC85XX_REVISION;
-
- if (edac_op_state == EDAC_OPSTATE_POLL)
- mci->edac_check = mpc85xx_mc_check;
-
- mci->ctl_page_to_phys = NULL;
-
- mci->scrub_mode = SCRUB_SW_SRC;
-
- mpc85xx_init_csrows(mci);
-
- /* store the original error disable bits */
- orig_ddr_err_disable =
- in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
-
- /* clear all error bits */
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
-
- if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) {
- edac_dbg(3, "failed edac_mc_add_mc()\n");
- goto err;
- }
-
- if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
- DDR_EIE_MBEE | DDR_EIE_SBEE);
-
- /* store the original error management threshold */
- orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
- MPC85XX_MC_ERR_SBE) & 0xff0000;
-
- /* set threshold to 1 error per interrupt */
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
-
- /* register interrupts */
- pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
- res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_mc_isr,
- IRQF_SHARED,
- "[EDAC] MC err", mci);
- if (res < 0) {
- pr_err("%s: Unable to request irq %d for "
- "MPC85xx DRAM ERR\n", __func__, pdata->irq);
- irq_dispose_mapping(pdata->irq);
- res = -ENODEV;
- goto err2;
- }
-
- pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
- pdata->irq);
- }
-
- devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
- edac_dbg(3, "success\n");
- pr_info(EDAC_MOD_STR " MC err registered\n");
-
- return 0;
-
-err2:
- edac_mc_del_mc(&op->dev);
-err:
- devres_release_group(&op->dev, mpc85xx_mc_err_probe);
- edac_mc_free(mci);
- return res;
-}
-
-static int mpc85xx_mc_err_remove(struct platform_device *op)
-{
- struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
-
- edac_dbg(0, "\n");
-
- if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
- irq_dispose_mapping(pdata->irq);
- }
-
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
- orig_ddr_err_disable);
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
-
- edac_mc_del_mc(&op->dev);
- edac_mc_free(mci);
- return 0;
-}
-
static const struct of_device_id mpc85xx_mc_err_of_match[] = {
/* deprecate the fsl,85.. forms in the future, 2.6.30? */
{ .compatible = "fsl,8540-memory-controller", },
diff --git a/drivers/edac/mpc85xx_edac.h b/drivers/edac/mpc85xx_edac.h
index 9352e88..3f6fb16 100644
--- a/drivers/edac/mpc85xx_edac.h
+++ b/drivers/edac/mpc85xx_edac.h
@@ -17,65 +17,6 @@
#define mpc85xx_printk(level, fmt, arg...) \
edac_printk(level, "MPC85xx", fmt, ##arg)
-#define mpc85xx_mc_printk(mci, level, fmt, arg...) \
- edac_mc_chipset_printk(mci, level, "MPC85xx", fmt, ##arg)
-
-/*
- * DRAM error defines
- */
-
-/* DDR_SDRAM_CFG */
-#define MPC85XX_MC_DDR_SDRAM_CFG 0x0110
-#define MPC85XX_MC_CS_BNDS_0 0x0000
-#define MPC85XX_MC_CS_BNDS_1 0x0008
-#define MPC85XX_MC_CS_BNDS_2 0x0010
-#define MPC85XX_MC_CS_BNDS_3 0x0018
-#define MPC85XX_MC_CS_BNDS_OFS 0x0008
-
-#define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00
-#define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04
-#define MPC85XX_MC_ECC_ERR_INJECT 0x0e08
-#define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20
-#define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24
-#define MPC85XX_MC_CAPTURE_ECC 0x0e28
-#define MPC85XX_MC_ERR_DETECT 0x0e40
-#define MPC85XX_MC_ERR_DISABLE 0x0e44
-#define MPC85XX_MC_ERR_INT_EN 0x0e48
-#define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c
-#define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50
-#define MPC85XX_MC_CAPTURE_EXT_ADDRESS 0x0e54
-#define MPC85XX_MC_ERR_SBE 0x0e58
-
-#define DSC_MEM_EN 0x80000000
-#define DSC_ECC_EN 0x20000000
-#define DSC_RD_EN 0x10000000
-#define DSC_DBW_MASK 0x00180000
-#define DSC_DBW_32 0x00080000
-#define DSC_DBW_64 0x00000000
-
-#define DSC_SDTYPE_MASK 0x07000000
-
-#define DSC_SDTYPE_DDR 0x02000000
-#define DSC_SDTYPE_DDR2 0x03000000
-#define DSC_SDTYPE_DDR3 0x07000000
-#define DSC_X32_EN 0x00000020
-
-/* Err_Int_En */
-#define DDR_EIE_MSEE 0x1 /* memory select */
-#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
-#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
-
-/* Err_Detect */
-#define DDR_EDE_MSE 0x1 /* memory select */
-#define DDR_EDE_SBE 0x4 /* single-bit ECC error */
-#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
-#define DDR_EDE_MME 0x80000000 /* multiple memory errors */
-
-/* Err_Disable */
-#define DDR_EDI_MSED 0x1 /* memory select disable */
-#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
-#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
-
/*
* L2 Err defines
*/
@@ -149,13 +90,6 @@
#define MPC85XX_PCIE_ERR_CAP_R2 0x0030
#define MPC85XX_PCIE_ERR_CAP_R3 0x0034
-struct mpc85xx_mc_pdata {
- char *name;
- int edac_idx;
- void __iomem *mc_vbase;
- int irq;
-};
-
struct mpc85xx_l2_pdata {
char *name;
int edac_idx;
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
2016-08-09 21:55 ` [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx York Sun
@ 2016-08-11 13:36 ` Borislav Petkov
2016-08-11 15:05 ` york sun
2016-08-11 20:13 ` york sun
0 siblings, 2 replies; 20+ messages in thread
From: Borislav Petkov @ 2016-08-11 13:36 UTC (permalink / raw)
To: York Sun
Cc: linux-edac, morbidrsa, oss, stuart.yoder, Doug Thompson, mchehab,
linux-kernel
On Tue, Aug 09, 2016 at 02:55:40PM -0700, York Sun wrote:
> The mpc85xx compatible DDR controllers are used on ARM-based SoCs.
> Separate the DDR part from mpc85xx EDAC driver and prepare to support
> both architecture.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
> Change log
> v4: Change comment in file header
> Use lower case "fsl_ddr_edac" for EDAC_MOD_STR
> Drop exporting probe and remove symbols
> v3: Fix compiling errors and warnings caused by patch ordering
> v2: Reordered patch
> Separate FSL DDR commont code as shared object, not another driver
> This patch is generated with "git format-patch -M40 -C40" to show
> copy-and-delete.
This patch doesn't apply this way:
$ git apply --check -v < /tmp/03-driver-edac-fsl-ddr-separate_fsl_ddr_edac_driver_from_mpc85xx.patch
...
error: patch failed: drivers/edac/mpc85xx_edac.c:724
error: drivers/edac/mpc85xx_edac.c: patch does not apply
Checking patch drivers/edac/mpc85xx_edac.h...
$ patch -p1 --dry-run -F10 -i /tmp/03-driver-edac-fsl-ddr-separate_fsl_ddr_edac_driver_from_mpc85xx.patch
checking file drivers/edac/Makefile
checking file drivers/edac/fsl_ddr_edac.c (copied from drivers/edac/mpc85xx_edac.c)
Hunk #3 FAILED at 132.
Hunk #4 succeeded at 1012 (offset -5 lines).
Hunk #5 succeeded at 1080 (offset -7 lines).
Hunk #6 FAILED at 1128.
Hunk #7 succeeded at 1145 (offset -8 lines).
Hunk #8 FAILED at 1173.
3 out of 8 hunks FAILED
checking file drivers/edac/fsl_ddr_edac.h (copied from drivers/edac/mpc85xx_edac.h)
checking file drivers/edac/mpc85xx_edac.c
Hunk #3 FAILED at 627.
1 out of 3 hunks FAILED
checking file drivers/edac/mpc85xx_edac.h
$ git am -i /tmp/york.sun.03
Applying: driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
error: patch failed: drivers/edac/mpc85xx_edac.c:141
error: drivers/edac/mpc85xx_edac.c: patch does not apply
error: patch failed: drivers/edac/mpc85xx_edac.c:724
error: drivers/edac/mpc85xx_edac.c: patch does not apply
Patch failed at 0001 driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am -i --continue".
If you prefer to skip this patch, run "git am -i --skip" instead.
To restore the original branch and stop patching, run "git am -i --abort".
Please regenerate it against:
http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git#edac-for-4.9
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
2016-08-11 13:36 ` Borislav Petkov
@ 2016-08-11 15:05 ` york sun
2016-08-11 20:13 ` york sun
1 sibling, 0 replies; 20+ messages in thread
From: york sun @ 2016-08-11 15:05 UTC (permalink / raw)
To: Borislav Petkov
Cc: linux-edac, morbidrsa, oss, Stuart Yoder, Doug Thompson, mchehab,
linux-kernel
On 08/11/2016 06:36 AM, Borislav Petkov wrote:
>
> Please regenerate it against:
>
> http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git#edac-for-4.9
>
Will do.
York
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
2016-08-11 13:36 ` Borislav Petkov
2016-08-11 15:05 ` york sun
@ 2016-08-11 20:13 ` york sun
1 sibling, 0 replies; 20+ messages in thread
From: york sun @ 2016-08-11 20:13 UTC (permalink / raw)
To: Borislav Petkov
Cc: linux-edac, morbidrsa, oss, Stuart Yoder, Doug Thompson, mchehab,
linux-kernel
On 08/11/2016 06:36 AM, Borislav Petkov wrote:
> On Tue, Aug 09, 2016 at 02:55:40PM -0700, York Sun wrote:
>> The mpc85xx compatible DDR controllers are used on ARM-based SoCs.
>> Separate the DDR part from mpc85xx EDAC driver and prepare to support
>> both architecture.
>>
>> Signed-off-by: York Sun <york.sun@nxp.com>
>>
>> ---
>> Change log
>> v4: Change comment in file header
>> Use lower case "fsl_ddr_edac" for EDAC_MOD_STR
>> Drop exporting probe and remove symbols
>> v3: Fix compiling errors and warnings caused by patch ordering
>> v2: Reordered patch
>> Separate FSL DDR commont code as shared object, not another driver
>> This patch is generated with "git format-patch -M40 -C40" to show
>> copy-and-delete.
>
> This patch doesn't apply this way:
>
> $ git apply --check -v < /tmp/03-driver-edac-fsl-ddr-separate_fsl_ddr_edac_driver_from_mpc85xx.patch
> ...
>
> error: patch failed: drivers/edac/mpc85xx_edac.c:724
> error: drivers/edac/mpc85xx_edac.c: patch does not apply
> Checking patch drivers/edac/mpc85xx_edac.h...
>
> $ patch -p1 --dry-run -F10 -i /tmp/03-driver-edac-fsl-ddr-separate_fsl_ddr_edac_driver_from_mpc85xx.patch
> checking file drivers/edac/Makefile
> checking file drivers/edac/fsl_ddr_edac.c (copied from drivers/edac/mpc85xx_edac.c)
> Hunk #3 FAILED at 132.
> Hunk #4 succeeded at 1012 (offset -5 lines).
> Hunk #5 succeeded at 1080 (offset -7 lines).
> Hunk #6 FAILED at 1128.
> Hunk #7 succeeded at 1145 (offset -8 lines).
> Hunk #8 FAILED at 1173.
> 3 out of 8 hunks FAILED
> checking file drivers/edac/fsl_ddr_edac.h (copied from drivers/edac/mpc85xx_edac.h)
> checking file drivers/edac/mpc85xx_edac.c
> Hunk #3 FAILED at 627.
> 1 out of 3 hunks FAILED
> checking file drivers/edac/mpc85xx_edac.h
>
> $ git am -i /tmp/york.sun.03
> Applying: driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
> error: patch failed: drivers/edac/mpc85xx_edac.c:141
> error: drivers/edac/mpc85xx_edac.c: patch does not apply
> error: patch failed: drivers/edac/mpc85xx_edac.c:724
> error: drivers/edac/mpc85xx_edac.c: patch does not apply
> Patch failed at 0001 driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx
> The copy of the patch that failed is found in: .git/rebase-apply/patch
> When you have resolved this problem, run "git am -i --continue".
> If you prefer to skip this patch, run "git am -i --skip" instead.
> To restore the original branch and stop patching, run "git am -i --abort".
>
> Please regenerate it against:
>
> http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git#edac-for-4.9
>
Boris,
I checked your edac-for-4.9 branch. There are two minor changes when you
apply the "Replace printk with proper pr_* format". I will send out a
single "Patch v5 3/9".
York
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Patch v4 4/9] driver/edac/fsl_ddr: Rename macros and names
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
` (2 preceding siblings ...)
2016-08-09 21:55 ` [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx York Sun
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` [Patch v4 5/9] driver/edac/fsl_ddr: Add DDR types York Sun
` (3 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Doug Thompson,
mchehab, linux-kernel
Use generic names for macros, variables and functions.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Replace MPC85XX_MC_* with FSL_MC_*
v3: Absort changes from reording patches
v2: Separated from "House cleaning" patch of v1
drivers/edac/fsl_ddr_edac.c | 166 ++++++++++++++++++++++----------------------
drivers/edac/fsl_ddr_edac.h | 43 ++++++------
drivers/edac/mpc85xx_edac.c | 4 +-
3 files changed, 105 insertions(+), 108 deletions(-)
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index ca7636f..2675833 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -42,74 +42,74 @@ static u32 orig_ddr_err_sbe;
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
-static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
- struct device_attribute *mattr,
- char *data)
+static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
+ struct device_attribute *mattr,
+ char *data)
{
struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
in_be32(pdata->mc_vbase +
- MPC85XX_MC_DATA_ERR_INJECT_HI));
+ FSL_MC_DATA_ERR_INJECT_HI));
}
-static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
- struct device_attribute *mattr,
+static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
+ struct device_attribute *mattr,
char *data)
{
struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
in_be32(pdata->mc_vbase +
- MPC85XX_MC_DATA_ERR_INJECT_LO));
+ FSL_MC_DATA_ERR_INJECT_LO));
}
-static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
- struct device_attribute *mattr,
+static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
+ struct device_attribute *mattr,
char *data)
{
struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
+ in_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
}
-static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
- struct device_attribute *mattr,
+static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
+ struct device_attribute *mattr,
const char *data, size_t count)
{
struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
+ out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
simple_strtoul(data, NULL, 0));
return count;
}
return 0;
}
-static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
- struct device_attribute *mattr,
+static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
+ struct device_attribute *mattr,
const char *data, size_t count)
{
struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
+ out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
simple_strtoul(data, NULL, 0));
return count;
}
return 0;
}
-static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
- struct device_attribute *mattr,
+static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
+ struct device_attribute *mattr,
const char *data, size_t count)
{
struct mem_ctl_info *mci = to_mci(dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
+ out_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
simple_strtoul(data, NULL, 0));
return count;
}
@@ -117,20 +117,20 @@ static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
}
DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
- mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
+ fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
- mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
+ fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
- mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
+ fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
-static struct attribute *mpc85xx_dev_attrs[] = {
+static struct attribute *fsl_ddr_dev_attrs[] = {
&dev_attr_inject_data_hi.attr,
&dev_attr_inject_data_lo.attr,
&dev_attr_inject_ctrl.attr,
NULL
};
-ATTRIBUTE_GROUPS(mpc85xx_dev);
+ATTRIBUTE_GROUPS(fsl_ddr_dev);
/**************************** MC Err device ***************************/
@@ -241,9 +241,9 @@ static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
#define make64(high, low) (((u64)(high) << 32) | (low))
-static void mpc85xx_mc_check(struct mem_ctl_info *mci)
+static void fsl_mc_check(struct mem_ctl_info *mci)
{
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
struct csrow_info *csrow;
u32 bus_width;
u32 err_detect;
@@ -256,23 +256,23 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
int bad_data_bit;
int bad_ecc_bit;
- err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
+ err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
if (!err_detect)
return;
- mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
- err_detect);
+ fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
+ err_detect);
/* no more processing if not ECC bit errors */
if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
return;
}
- syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
+ syndrome = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
/* Mask off appropriate bits of syndrome based on bus width */
- bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
+ bus_width = (in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
DSC_DBW_MASK) ? 32 : 64;
if (bus_width == 64)
syndrome &= 0xff;
@@ -280,8 +280,8 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
syndrome &= 0xffff;
err_addr = make64(
- in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS),
- in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS));
+ in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
+ in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
pfn = err_addr >> PAGE_SHIFT;
for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
@@ -290,8 +290,8 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
break;
}
- cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
- cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
+ cap_high = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
+ cap_low = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
/*
* Analyze single-bit errors on 64-bit wide buses
@@ -302,28 +302,28 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
&bad_data_bit, &bad_ecc_bit);
if (bad_data_bit != -1)
- mpc85xx_mc_printk(mci, KERN_ERR,
+ fsl_mc_printk(mci, KERN_ERR,
"Faulty Data bit: %d\n", bad_data_bit);
if (bad_ecc_bit != -1)
- mpc85xx_mc_printk(mci, KERN_ERR,
+ fsl_mc_printk(mci, KERN_ERR,
"Faulty ECC bit: %d\n", bad_ecc_bit);
- mpc85xx_mc_printk(mci, KERN_ERR,
+ fsl_mc_printk(mci, KERN_ERR,
"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
cap_high ^ (1 << (bad_data_bit - 32)),
cap_low ^ (1 << bad_data_bit),
syndrome ^ (1 << bad_ecc_bit));
}
- mpc85xx_mc_printk(mci, KERN_ERR,
+ fsl_mc_printk(mci, KERN_ERR,
"Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
cap_high, cap_low, syndrome);
- mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
- mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
+ fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
+ fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
/* we are out of range */
if (row_index == mci->nr_csrows)
- mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
+ fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
if (err_detect & DDR_EDE_SBE)
edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
@@ -337,27 +337,27 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
row_index, 0, -1,
mci->ctl_name, "");
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
}
-static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
+static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
{
struct mem_ctl_info *mci = dev_id;
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
u32 err_detect;
- err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
+ err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
if (!err_detect)
return IRQ_NONE;
- mpc85xx_mc_check(mci);
+ fsl_mc_check(mci);
return IRQ_HANDLED;
}
-static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
+static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
{
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
struct csrow_info *csrow;
struct dimm_info *dimm;
u32 sdram_ctl;
@@ -366,7 +366,7 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
u32 cs_bnds;
int index;
- sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
+ sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
if (sdram_ctl & DSC_RD_EN) {
@@ -408,8 +408,8 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
csrow = mci->csrows[index];
dimm = csrow->channels[0]->dimm;
- cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
- (index * MPC85XX_MC_CS_BNDS_OFS));
+ cs_bnds = in_be32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
+ (index * FSL_MC_CS_BNDS_OFS));
start = (cs_bnds & 0xffff0000) >> 16;
end = (cs_bnds & 0x0000ffff);
@@ -434,16 +434,16 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
}
}
-int mpc85xx_mc_err_probe(struct platform_device *op)
+int fsl_mc_err_probe(struct platform_device *op)
{
struct mem_ctl_info *mci;
struct edac_mc_layer layers[2];
- struct mpc85xx_mc_pdata *pdata;
+ struct fsl_mc_pdata *pdata;
struct resource r;
u32 sdram_ctl;
int res;
- if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
+ if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
return -ENOMEM;
layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
@@ -455,12 +455,12 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
sizeof(*pdata));
if (!mci) {
- devres_release_group(&op->dev, mpc85xx_mc_err_probe);
+ devres_release_group(&op->dev, fsl_mc_err_probe);
return -ENOMEM;
}
pdata = mci->pvt_info;
- pdata->name = "mpc85xx_mc_err";
+ pdata->name = "fsl_mc_err";
pdata->irq = NO_IRQ;
mci->pdev = &op->dev;
pdata->edac_idx = edac_mc_idx++;
@@ -490,7 +490,7 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
goto err;
}
- sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
+ sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
if (!(sdram_ctl & DSC_ECC_EN)) {
/* no ECC */
pr_warn("%s: No ECC DIMMs discovered\n", __func__);
@@ -506,46 +506,46 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
mci->mod_name = EDAC_MOD_STR;
if (edac_op_state == EDAC_OPSTATE_POLL)
- mci->edac_check = mpc85xx_mc_check;
+ mci->edac_check = fsl_mc_check;
mci->ctl_page_to_phys = NULL;
mci->scrub_mode = SCRUB_SW_SRC;
- mpc85xx_init_csrows(mci);
+ fsl_ddr_init_csrows(mci);
/* store the original error disable bits */
orig_ddr_err_disable =
- in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
+ in_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
/* clear all error bits */
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
- if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) {
+ if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
edac_dbg(3, "failed edac_mc_add_mc()\n");
goto err;
}
if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
DDR_EIE_MBEE | DDR_EIE_SBEE);
/* store the original error management threshold */
orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
- MPC85XX_MC_ERR_SBE) & 0xff0000;
+ FSL_MC_ERR_SBE) & 0xff0000;
/* set threshold to 1 error per interrupt */
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
/* register interrupts */
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
res = devm_request_irq(&op->dev, pdata->irq,
- mpc85xx_mc_isr,
+ fsl_mc_isr,
IRQF_SHARED,
"[EDAC] MC err", mci);
if (res < 0) {
- pr_err("%s: Unable to request irq %d for MPC85xx DRAM ERR\n",
+ pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
__func__, pdata->irq);
irq_dispose_mapping(pdata->irq);
res = -ENODEV;
@@ -556,7 +556,7 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
pdata->irq);
}
- devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
+ devres_remove_group(&op->dev, fsl_mc_err_probe);
edac_dbg(3, "success\n");
pr_info(EDAC_MOD_STR " MC err registered\n");
@@ -565,26 +565,26 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
err2:
edac_mc_del_mc(&op->dev);
err:
- devres_release_group(&op->dev, mpc85xx_mc_err_probe);
+ devres_release_group(&op->dev, fsl_mc_err_probe);
edac_mc_free(mci);
return res;
}
-int mpc85xx_mc_err_remove(struct platform_device *op)
+int fsl_mc_err_remove(struct platform_device *op)
{
struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
- struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
+ struct fsl_mc_pdata *pdata = mci->pvt_info;
edac_dbg(0, "\n");
if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
irq_dispose_mapping(pdata->irq);
}
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
orig_ddr_err_disable);
- out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
+ out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
edac_mc_del_mc(&op->dev);
edac_mc_free(mci);
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 2f2c2b1..1eccc62 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -16,7 +16,7 @@
#ifndef _FSL_DDR_EDAC_H_
#define _FSL_DDR_EDAC_H_
-#define mpc85xx_mc_printk(mci, level, fmt, arg...) \
+#define fsl_mc_printk(mci, level, fmt, arg...) \
edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
/*
@@ -24,26 +24,23 @@
*/
/* DDR_SDRAM_CFG */
-#define MPC85XX_MC_DDR_SDRAM_CFG 0x0110
-#define MPC85XX_MC_CS_BNDS_0 0x0000
-#define MPC85XX_MC_CS_BNDS_1 0x0008
-#define MPC85XX_MC_CS_BNDS_2 0x0010
-#define MPC85XX_MC_CS_BNDS_3 0x0018
-#define MPC85XX_MC_CS_BNDS_OFS 0x0008
+#define FSL_MC_DDR_SDRAM_CFG 0x0110
+#define FSL_MC_CS_BNDS_0 0x0000
+#define FSL_MC_CS_BNDS_OFS 0x0008
-#define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00
-#define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04
-#define MPC85XX_MC_ECC_ERR_INJECT 0x0e08
-#define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20
-#define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24
-#define MPC85XX_MC_CAPTURE_ECC 0x0e28
-#define MPC85XX_MC_ERR_DETECT 0x0e40
-#define MPC85XX_MC_ERR_DISABLE 0x0e44
-#define MPC85XX_MC_ERR_INT_EN 0x0e48
-#define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c
-#define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50
-#define MPC85XX_MC_CAPTURE_EXT_ADDRESS 0x0e54
-#define MPC85XX_MC_ERR_SBE 0x0e58
+#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
+#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
+#define FSL_MC_ECC_ERR_INJECT 0x0e08
+#define FSL_MC_CAPTURE_DATA_HI 0x0e20
+#define FSL_MC_CAPTURE_DATA_LO 0x0e24
+#define FSL_MC_CAPTURE_ECC 0x0e28
+#define FSL_MC_ERR_DETECT 0x0e40
+#define FSL_MC_ERR_DISABLE 0x0e44
+#define FSL_MC_ERR_INT_EN 0x0e48
+#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
+#define FSL_MC_CAPTURE_ADDRESS 0x0e50
+#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
+#define FSL_MC_ERR_SBE 0x0e58
#define DSC_MEM_EN 0x80000000
#define DSC_ECC_EN 0x20000000
@@ -75,12 +72,12 @@
#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
-struct mpc85xx_mc_pdata {
+struct fsl_mc_pdata {
char *name;
int edac_idx;
void __iomem *mc_vbase;
int irq;
};
-int mpc85xx_mc_err_probe(struct platform_device *op);
-int mpc85xx_mc_err_remove(struct platform_device *op);
+int fsl_mc_err_probe(struct platform_device *op);
+int fsl_mc_err_remove(struct platform_device *op);
#endif
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index af9ce77..c4c677c 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -655,8 +655,8 @@ static const struct of_device_id mpc85xx_mc_err_of_match[] = {
MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
static struct platform_driver mpc85xx_mc_err_driver = {
- .probe = mpc85xx_mc_err_probe,
- .remove = mpc85xx_mc_err_remove,
+ .probe = fsl_mc_err_probe,
+ .remove = fsl_mc_err_remove,
.driver = {
.name = "mpc85xx_mc_err",
.of_match_table = mpc85xx_mc_err_of_match,
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 5/9] driver/edac/fsl_ddr: Add DDR types
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
` (3 preceding siblings ...)
2016-08-09 21:55 ` [Patch v4 4/9] driver/edac/fsl_ddr: Rename macros and names York Sun
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` York Sun
` (2 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Doug Thompson,
mchehab, linux-kernel
The compatible DDR controllers may support DDR, DDR2, DDR3, DDR4. An
individual controller doesn't support all of them. EDAC driver reads
the controller to determine which mode is running.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Drop DSC_SDTYPE_DDR* macros, use naked numbers as suggested
Update commit message.
v3: no change
v2: no change
drivers/edac/fsl_ddr_edac.c | 24 ++++++++++++++++--------
drivers/edac/fsl_ddr_edac.h | 4 ----
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 2675833..46b00e1 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -371,30 +371,36 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
if (sdram_ctl & DSC_RD_EN) {
switch (sdtype) {
- case DSC_SDTYPE_DDR:
+ case 0x02000000:
mtype = MEM_RDDR;
break;
- case DSC_SDTYPE_DDR2:
+ case 0x03000000:
mtype = MEM_RDDR2;
break;
- case DSC_SDTYPE_DDR3:
+ case 0x07000000:
mtype = MEM_RDDR3;
break;
+ case 0x05000000:
+ mtype = MEM_RDDR4;
+ break;
default:
mtype = MEM_UNKNOWN;
break;
}
} else {
switch (sdtype) {
- case DSC_SDTYPE_DDR:
+ case 0x02000000:
mtype = MEM_DDR;
break;
- case DSC_SDTYPE_DDR2:
+ case 0x03000000:
mtype = MEM_DDR2;
break;
- case DSC_SDTYPE_DDR3:
+ case 0x07000000:
mtype = MEM_DDR3;
break;
+ case 0x05000000:
+ mtype = MEM_DDR4;
+ break;
default:
mtype = MEM_UNKNOWN;
break;
@@ -499,8 +505,10 @@ int fsl_mc_err_probe(struct platform_device *op)
}
edac_dbg(3, "init mci\n");
- mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
- MEM_FLAG_DDR | MEM_FLAG_DDR2;
+ mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
+ MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
+ MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
+ MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
mci->edac_cap = EDAC_FLAG_SECDED;
mci->mod_name = EDAC_MOD_STR;
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 1eccc62..4ccee29 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -50,10 +50,6 @@
#define DSC_DBW_64 0x00000000
#define DSC_SDTYPE_MASK 0x07000000
-
-#define DSC_SDTYPE_DDR 0x02000000
-#define DSC_SDTYPE_DDR2 0x03000000
-#define DSC_SDTYPE_DDR3 0x07000000
#define DSC_X32_EN 0x00000020
/* Err_Int_En */
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` [Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format York Sun
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Rob Herring,
Mark Rutland, Doug Thompson, mchehab, devicetree, linux-kernel
Get endianness from device tree. Both big endian and little endian
are supported. Default to big endian for backward compatibility to
MPC85xx.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Absorb name changes by "Rename macros and names"
Drop testing for big-endian as suggested
Use of_property_read_bool() as suggested
v3: no change
v2: Separated from "Add support for ARM-based SoCs" patch
.../fsl/ddr.txt} | 2 +
drivers/edac/fsl_ddr_edac.c | 96 +++++++++++++---------
2 files changed, 58 insertions(+), 40 deletions(-)
rename Documentation/devicetree/bindings/{powerpc/fsl/mem-ctrlr.txt => memory-controllers/fsl/ddr.txt} (86%)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt
similarity index 86%
rename from Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt
index f87856f..dde6d83 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt
@@ -7,6 +7,8 @@ Properties:
"fsl,qoriq-memory-controller".
- reg : Address and size of DDR controller registers
- interrupts : Error interrupt of DDR controller
+- little-endian : Specifies little-endian access to registers
+ If omitted, big-endian will be used.
Example 1:
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 46b00e1..6d4dd84 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -13,7 +13,6 @@
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
- *
*/
#include <linux/module.h>
#include <linux/init.h>
@@ -37,6 +36,20 @@ static int edac_mc_idx;
static u32 orig_ddr_err_disable;
static u32 orig_ddr_err_sbe;
+static bool little_endian;
+
+static inline u32 ddr_in32(void __iomem *addr)
+{
+ return little_endian ? ioread32(addr) : ioread32be(addr);
+}
+
+static inline void ddr_out32(void __iomem *addr, u32 value)
+{
+ if (little_endian)
+ iowrite32(value, addr);
+ else
+ iowrite32be(value, addr);
+}
/************************ MC SYSFS parts ***********************************/
@@ -49,8 +62,7 @@ static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase +
- FSL_MC_DATA_ERR_INJECT_HI));
+ ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
}
static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
@@ -60,8 +72,7 @@ static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase +
- FSL_MC_DATA_ERR_INJECT_LO));
+ ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
}
static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
@@ -71,7 +82,7 @@ static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
+ ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
}
static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
@@ -81,8 +92,8 @@ static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
- simple_strtoul(data, NULL, 0));
+ ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
+ simple_strtoul(data, NULL, 0));
return count;
}
return 0;
@@ -95,8 +106,8 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
- simple_strtoul(data, NULL, 0));
+ ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
+ simple_strtoul(data, NULL, 0));
return count;
}
return 0;
@@ -109,8 +120,8 @@ static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
- simple_strtoul(data, NULL, 0));
+ ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
+ simple_strtoul(data, NULL, 0));
return count;
}
return 0;
@@ -256,7 +267,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
int bad_data_bit;
int bad_ecc_bit;
- err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
+ err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
if (!err_detect)
return;
@@ -265,23 +276,23 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
/* no more processing if not ECC bit errors */
if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
return;
}
- syndrome = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
+ syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
/* Mask off appropriate bits of syndrome based on bus width */
- bus_width = (in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
- DSC_DBW_MASK) ? 32 : 64;
+ bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
+ DSC_DBW_MASK) ? 32 : 64;
if (bus_width == 64)
syndrome &= 0xff;
else
syndrome &= 0xffff;
err_addr = make64(
- in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
- in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
+ ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
+ ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
pfn = err_addr >> PAGE_SHIFT;
for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
@@ -290,8 +301,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
break;
}
- cap_high = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
- cap_low = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
+ cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
+ cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
/*
* Analyze single-bit errors on 64-bit wide buses
@@ -337,7 +348,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
row_index, 0, -1,
mci->ctl_name, "");
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
}
static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
@@ -346,7 +357,7 @@ static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
struct fsl_mc_pdata *pdata = mci->pvt_info;
u32 err_detect;
- err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
+ err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
if (!err_detect)
return IRQ_NONE;
@@ -366,7 +377,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
u32 cs_bnds;
int index;
- sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
+ sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
if (sdram_ctl & DSC_RD_EN) {
@@ -414,8 +425,8 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
csrow = mci->csrows[index];
dimm = csrow->channels[0]->dimm;
- cs_bnds = in_be32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
- (index * FSL_MC_CS_BNDS_OFS));
+ cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
+ (index * FSL_MC_CS_BNDS_OFS));
start = (cs_bnds & 0xffff0000) >> 16;
end = (cs_bnds & 0x0000ffff);
@@ -474,6 +485,12 @@ int fsl_mc_err_probe(struct platform_device *op)
mci->ctl_name = pdata->name;
mci->dev_name = pdata->name;
+ /*
+ * Get the endianness of DDR controller registers.
+ * Default is big endian.
+ */
+ little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
+
res = of_address_to_resource(op->dev.of_node, 0, &r);
if (res) {
pr_err("%s: Unable to get resource for MC err regs\n",
@@ -496,7 +513,7 @@ int fsl_mc_err_probe(struct platform_device *op)
goto err;
}
- sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
+ sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
if (!(sdram_ctl & DSC_ECC_EN)) {
/* no ECC */
pr_warn("%s: No ECC DIMMs discovered\n", __func__);
@@ -523,12 +540,11 @@ int fsl_mc_err_probe(struct platform_device *op)
fsl_ddr_init_csrows(mci);
/* store the original error disable bits */
- orig_ddr_err_disable =
- in_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
+ orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
/* clear all error bits */
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
edac_dbg(3, "failed edac_mc_add_mc()\n");
@@ -536,15 +552,15 @@ int fsl_mc_err_probe(struct platform_device *op)
}
if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
- DDR_EIE_MBEE | DDR_EIE_SBEE);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
+ DDR_EIE_MBEE | DDR_EIE_SBEE);
/* store the original error management threshold */
- orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
- FSL_MC_ERR_SBE) & 0xff0000;
+ orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
+ FSL_MC_ERR_SBE) & 0xff0000;
/* set threshold to 1 error per interrupt */
- out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
/* register interrupts */
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
@@ -586,13 +602,13 @@ int fsl_mc_err_remove(struct platform_device *op)
edac_dbg(0, "\n");
if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
irq_dispose_mapping(pdata->irq);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
}
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
- orig_ddr_err_disable);
- out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
+ orig_ddr_err_disable);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
edac_mc_del_mc(&op->dev);
edac_mc_free(mci);
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian
@ 2016-08-09 21:55 ` York Sun
0 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Rob Herring,
Mark Rutland, Doug Thompson, mchehab, devicetree, linux-kernel
Get endianness from device tree. Both big endian and little endian
are supported. Default to big endian for backward compatibility to
MPC85xx.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Absorb name changes by "Rename macros and names"
Drop testing for big-endian as suggested
Use of_property_read_bool() as suggested
v3: no change
v2: Separated from "Add support for ARM-based SoCs" patch
.../fsl/ddr.txt} | 2 +
drivers/edac/fsl_ddr_edac.c | 96 +++++++++++++---------
2 files changed, 58 insertions(+), 40 deletions(-)
rename Documentation/devicetree/bindings/{powerpc/fsl/mem-ctrlr.txt => memory-controllers/fsl/ddr.txt} (86%)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt
similarity index 86%
rename from Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt
rename to Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt
index f87856f..dde6d83 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ddr.txt
@@ -7,6 +7,8 @@ Properties:
"fsl,qoriq-memory-controller".
- reg : Address and size of DDR controller registers
- interrupts : Error interrupt of DDR controller
+- little-endian : Specifies little-endian access to registers
+ If omitted, big-endian will be used.
Example 1:
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 46b00e1..6d4dd84 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -13,7 +13,6 @@
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
- *
*/
#include <linux/module.h>
#include <linux/init.h>
@@ -37,6 +36,20 @@ static int edac_mc_idx;
static u32 orig_ddr_err_disable;
static u32 orig_ddr_err_sbe;
+static bool little_endian;
+
+static inline u32 ddr_in32(void __iomem *addr)
+{
+ return little_endian ? ioread32(addr) : ioread32be(addr);
+}
+
+static inline void ddr_out32(void __iomem *addr, u32 value)
+{
+ if (little_endian)
+ iowrite32(value, addr);
+ else
+ iowrite32be(value, addr);
+}
/************************ MC SYSFS parts ***********************************/
@@ -49,8 +62,7 @@ static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase +
- FSL_MC_DATA_ERR_INJECT_HI));
+ ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
}
static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
@@ -60,8 +72,7 @@ static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase +
- FSL_MC_DATA_ERR_INJECT_LO));
+ ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
}
static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
@@ -71,7 +82,7 @@ static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
return sprintf(data, "0x%08x",
- in_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
+ ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
}
static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
@@ -81,8 +92,8 @@ static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
- simple_strtoul(data, NULL, 0));
+ ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
+ simple_strtoul(data, NULL, 0));
return count;
}
return 0;
@@ -95,8 +106,8 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
- simple_strtoul(data, NULL, 0));
+ ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
+ simple_strtoul(data, NULL, 0));
return count;
}
return 0;
@@ -109,8 +120,8 @@ static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
struct mem_ctl_info *mci = to_mci(dev);
struct fsl_mc_pdata *pdata = mci->pvt_info;
if (isdigit(*data)) {
- out_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
- simple_strtoul(data, NULL, 0));
+ ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
+ simple_strtoul(data, NULL, 0));
return count;
}
return 0;
@@ -256,7 +267,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
int bad_data_bit;
int bad_ecc_bit;
- err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
+ err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
if (!err_detect)
return;
@@ -265,23 +276,23 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
/* no more processing if not ECC bit errors */
if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
return;
}
- syndrome = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
+ syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
/* Mask off appropriate bits of syndrome based on bus width */
- bus_width = (in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
- DSC_DBW_MASK) ? 32 : 64;
+ bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
+ DSC_DBW_MASK) ? 32 : 64;
if (bus_width == 64)
syndrome &= 0xff;
else
syndrome &= 0xffff;
err_addr = make64(
- in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
- in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
+ ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
+ ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
pfn = err_addr >> PAGE_SHIFT;
for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
@@ -290,8 +301,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
break;
}
- cap_high = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
- cap_low = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
+ cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
+ cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
/*
* Analyze single-bit errors on 64-bit wide buses
@@ -337,7 +348,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
row_index, 0, -1,
mci->ctl_name, "");
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
}
static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
@@ -346,7 +357,7 @@ static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
struct fsl_mc_pdata *pdata = mci->pvt_info;
u32 err_detect;
- err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
+ err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
if (!err_detect)
return IRQ_NONE;
@@ -366,7 +377,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
u32 cs_bnds;
int index;
- sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
+ sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
sdtype = sdram_ctl & DSC_SDTYPE_MASK;
if (sdram_ctl & DSC_RD_EN) {
@@ -414,8 +425,8 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
csrow = mci->csrows[index];
dimm = csrow->channels[0]->dimm;
- cs_bnds = in_be32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
- (index * FSL_MC_CS_BNDS_OFS));
+ cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
+ (index * FSL_MC_CS_BNDS_OFS));
start = (cs_bnds & 0xffff0000) >> 16;
end = (cs_bnds & 0x0000ffff);
@@ -474,6 +485,12 @@ int fsl_mc_err_probe(struct platform_device *op)
mci->ctl_name = pdata->name;
mci->dev_name = pdata->name;
+ /*
+ * Get the endianness of DDR controller registers.
+ * Default is big endian.
+ */
+ little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
+
res = of_address_to_resource(op->dev.of_node, 0, &r);
if (res) {
pr_err("%s: Unable to get resource for MC err regs\n",
@@ -496,7 +513,7 @@ int fsl_mc_err_probe(struct platform_device *op)
goto err;
}
- sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
+ sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
if (!(sdram_ctl & DSC_ECC_EN)) {
/* no ECC */
pr_warn("%s: No ECC DIMMs discovered\n", __func__);
@@ -523,12 +540,11 @@ int fsl_mc_err_probe(struct platform_device *op)
fsl_ddr_init_csrows(mci);
/* store the original error disable bits */
- orig_ddr_err_disable =
- in_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
+ orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
/* clear all error bits */
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
edac_dbg(3, "failed edac_mc_add_mc()\n");
@@ -536,15 +552,15 @@ int fsl_mc_err_probe(struct platform_device *op)
}
if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
- DDR_EIE_MBEE | DDR_EIE_SBEE);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
+ DDR_EIE_MBEE | DDR_EIE_SBEE);
/* store the original error management threshold */
- orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
- FSL_MC_ERR_SBE) & 0xff0000;
+ orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
+ FSL_MC_ERR_SBE) & 0xff0000;
/* set threshold to 1 error per interrupt */
- out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
/* register interrupts */
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
@@ -586,13 +602,13 @@ int fsl_mc_err_remove(struct platform_device *op)
edac_dbg(0, "\n");
if (edac_op_state == EDAC_OPSTATE_INT) {
- out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
irq_dispose_mapping(pdata->irq);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
}
- out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
- orig_ddr_err_disable);
- out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
+ orig_ddr_err_disable);
+ ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
edac_mc_del_mc(&op->dev);
edac_mc_free(mci);
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian
2016-08-09 21:55 ` York Sun
(?)
@ 2016-08-10 22:26 ` Rob Herring
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2016-08-10 22:26 UTC (permalink / raw)
To: York Sun
Cc: linux-edac, morbidrsa, oss, stuart.yoder, bp, Mark Rutland,
Doug Thompson, mchehab, devicetree, linux-kernel
On Tue, Aug 09, 2016 at 02:55:43PM -0700, York Sun wrote:
> Get endianness from device tree. Both big endian and little endian
> are supported. Default to big endian for backward compatibility to
> MPC85xx.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
> Change log
> v4: Absorb name changes by "Rename macros and names"
> Drop testing for big-endian as suggested
> Use of_property_read_bool() as suggested
> v3: no change
> v2: Separated from "Add support for ARM-based SoCs" patch
>
> .../fsl/ddr.txt} | 2 +
> drivers/edac/fsl_ddr_edac.c | 96 +++++++++++++---------
> 2 files changed, 58 insertions(+), 40 deletions(-)
> rename Documentation/devicetree/bindings/{powerpc/fsl/mem-ctrlr.txt => memory-controllers/fsl/ddr.txt} (86%)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian
@ 2016-08-12 7:41 ` Borislav Petkov
0 siblings, 0 replies; 20+ messages in thread
From: Borislav Petkov @ 2016-08-12 7:41 UTC (permalink / raw)
To: York Sun
Cc: linux-edac, morbidrsa, oss, stuart.yoder, Rob Herring,
Mark Rutland, Doug Thompson, mchehab, devicetree, linux-kernel
On Tue, Aug 09, 2016 at 02:55:43PM -0700, York Sun wrote:
> Get endianness from device tree. Both big endian and little endian
> are supported. Default to big endian for backward compatibility to
> MPC85xx.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
> Change log
> v4: Absorb name changes by "Rename macros and names"
> Drop testing for big-endian as suggested
> Use of_property_read_bool() as suggested
> v3: no change
> v2: Separated from "Add support for ARM-based SoCs" patch
>
> .../fsl/ddr.txt} | 2 +
> drivers/edac/fsl_ddr_edac.c | 96 +++++++++++++---------
> 2 files changed, 58 insertions(+), 40 deletions(-)
> rename Documentation/devicetree/bindings/{powerpc/fsl/mem-ctrlr.txt => memory-controllers/fsl/ddr.txt} (86%)
...
> @@ -95,8 +106,8 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
> struct mem_ctl_info *mci = to_mci(dev);
> struct fsl_mc_pdata *pdata = mci->pvt_info;
> if (isdigit(*data)) {
> - out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
> - simple_strtoul(data, NULL, 0));
> + ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
> + simple_strtoul(data, NULL, 0));
> return count;
> }
> return 0;
WARNING: simple_strtoul is obsolete, use kstrtoul instead
#122: FILE: drivers/edac/fsl_ddr_edac.c:96:
+ simple_strtoul(data, NULL, 0));
Please send a fix ontop.
Thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian
@ 2016-08-12 7:41 ` Borislav Petkov
0 siblings, 0 replies; 20+ messages in thread
From: Borislav Petkov @ 2016-08-12 7:41 UTC (permalink / raw)
To: York Sun
Cc: linux-edac-u79uwXL29TY76Z2rM5mHXA,
morbidrsa-Re5JQEeQqe8AvxtiuMwx3w, oss-fOR+EgIDQEHk1uMJSBkQmQ,
stuart.yoder-3arQi8VN3Tc, Rob Herring, Mark Rutland,
Doug Thompson, mchehab-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Tue, Aug 09, 2016 at 02:55:43PM -0700, York Sun wrote:
> Get endianness from device tree. Both big endian and little endian
> are supported. Default to big endian for backward compatibility to
> MPC85xx.
>
> Signed-off-by: York Sun <york.sun-3arQi8VN3Tc@public.gmane.org>
>
> ---
> Change log
> v4: Absorb name changes by "Rename macros and names"
> Drop testing for big-endian as suggested
> Use of_property_read_bool() as suggested
> v3: no change
> v2: Separated from "Add support for ARM-based SoCs" patch
>
> .../fsl/ddr.txt} | 2 +
> drivers/edac/fsl_ddr_edac.c | 96 +++++++++++++---------
> 2 files changed, 58 insertions(+), 40 deletions(-)
> rename Documentation/devicetree/bindings/{powerpc/fsl/mem-ctrlr.txt => memory-controllers/fsl/ddr.txt} (86%)
...
> @@ -95,8 +106,8 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
> struct mem_ctl_info *mci = to_mci(dev);
> struct fsl_mc_pdata *pdata = mci->pvt_info;
> if (isdigit(*data)) {
> - out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
> - simple_strtoul(data, NULL, 0));
> + ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
> + simple_strtoul(data, NULL, 0));
> return count;
> }
> return 0;
WARNING: simple_strtoul is obsolete, use kstrtoul instead
#122: FILE: drivers/edac/fsl_ddr_edac.c:96:
+ simple_strtoul(data, NULL, 0));
Please send a fix ontop.
Thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Patch v4 7/9] driver/edac/fsl_ddr: Fix kernel warning when module is removed
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
` (5 preceding siblings ...)
2016-08-09 21:55 ` York Sun
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` York Sun
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Doug Thompson,
mchehab, linux-kernel
When compiled as a module, removing this module causes kernel
warnings when irq_dispose_mapping() is called. Instead of calling
irq_of_parse_and_map(), using platform_get_irq() to acquire the
IRQ number.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Absorb name changes by "Rename macros and names"
v3: no change
v2: no change
drivers/edac/fsl_ddr_edac.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index 6d4dd84..d8ce1f6 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -563,7 +563,7 @@ int fsl_mc_err_probe(struct platform_device *op)
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
/* register interrupts */
- pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
+ pdata->irq = platform_get_irq(op, 0);
res = devm_request_irq(&op->dev, pdata->irq,
fsl_mc_isr,
IRQF_SHARED,
@@ -571,7 +571,6 @@ int fsl_mc_err_probe(struct platform_device *op)
if (res < 0) {
pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
__func__, pdata->irq);
- irq_dispose_mapping(pdata->irq);
res = -ENODEV;
goto err2;
}
@@ -602,7 +601,6 @@ int fsl_mc_err_remove(struct platform_device *op)
edac_dbg(0, "\n");
if (edac_op_state == EDAC_OPSTATE_INT) {
- irq_dispose_mapping(pdata->irq);
ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support
[not found] <1470779760-16483-1-git-send-email-york.sun@nxp.com>
@ 2016-08-09 21:55 ` York Sun
2016-08-09 21:55 ` [Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format York Sun
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-edac
Cc: morbidrsa, oss, stuart.yoder, bp, York Sun, Catalin Marinas,
Will Deacon, Doug Thompson, mchehab, linux-arm-kernel,
linux-kernel
Add DDR EDAC for ARM-based compatible controllers. Both big-endian
and little-endian are supported, as specified in device tree.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Drop adding atomic_scrub() for arm64
Drop NO_IRQ
v3: no change
v2: Create new driver using shared DDR object
arch/arm64/Kconfig.platforms | 1 +
drivers/edac/Kconfig | 7 +++++
drivers/edac/Makefile | 3 ++
drivers/edac/fsl_ddr_edac.c | 2 +-
drivers/edac/layerscape_edac.c | 67 ++++++++++++++++++++++++++++++++++++++++++
5 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 drivers/edac/layerscape_edac.c
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 7ef1d05..185a215 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -41,6 +41,7 @@ config ARCH_EXYNOS
config ARCH_LAYERSCAPE
bool "ARMv8 based Freescale Layerscape SoC family"
+ select EDAC_SUPPORT
help
This enables support for the Freescale Layerscape SoC family.
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 6ca7474..f1ac4e2 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -258,6 +258,13 @@ config EDAC_MPC85XX
Support for error detection and correction on the Freescale
MPC8349, MPC8560, MPC8540, MPC8548, T4240
+config EDAC_LAYERSCAPE
+ tristate "Freescale Layerscape DDR"
+ depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
+ help
+ Support for error detection and correction on Freescale memory
+ controllers on Layerscape SoCs.
+
config EDAC_MV64X60
tristate "Marvell MV64x60"
depends on EDAC_MM_EDAC && MV64X60
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index ee047a4..910dc83 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -54,6 +54,9 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
+layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
+obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
+
obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL) += cell_edac.o
obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index d8ce1f6..afade14 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -26,6 +26,7 @@
#include <linux/of_platform.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include "edac_module.h"
#include "edac_core.h"
#include "fsl_ddr_edac.h"
@@ -478,7 +479,6 @@ int fsl_mc_err_probe(struct platform_device *op)
pdata = mci->pvt_info;
pdata->name = "fsl_mc_err";
- pdata->irq = NO_IRQ;
mci->pdev = &op->dev;
pdata->edac_idx = edac_mc_idx++;
dev_set_drvdata(mci->pdev, mci);
diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c
new file mode 100644
index 0000000..6ba771d
--- /dev/null
+++ b/drivers/edac/layerscape_edac.c
@@ -0,0 +1,67 @@
+/*
+ * Freescale Memory Controller kernel module
+ *
+ * Derived from mpc85xx_edac.c
+ * Author: Dave Jiang <djiang@mvista.com>
+ *
+ * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include "edac_core.h"
+#include "fsl_ddr_edac.h"
+
+static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
+ { .compatible = "fsl,qoriq-memory-controller", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
+
+static struct platform_driver fsl_ddr_mc_err_driver = {
+ .probe = fsl_mc_err_probe,
+ .remove = fsl_mc_err_remove,
+ .driver = {
+ .name = "fsl_ddr_mc_err",
+ .of_match_table = fsl_ddr_mc_err_of_match,
+ },
+};
+
+static int __init fsl_ddr_mc_init(void)
+{
+ int res = 0;
+
+ /* make sure error reporting method is sane */
+ switch (edac_op_state) {
+ case EDAC_OPSTATE_POLL:
+ case EDAC_OPSTATE_INT:
+ break;
+ default:
+ edac_op_state = EDAC_OPSTATE_INT;
+ break;
+ }
+
+ res = platform_driver_register(&fsl_ddr_mc_err_driver);
+ if (res) {
+ pr_err("Layerscape EDAC: MC fails to register\n");
+ return res;
+ }
+
+ return 0;
+}
+
+module_init(fsl_ddr_mc_init);
+
+static void __exit fsl_ddr_mc_exit(void)
+{
+ platform_driver_unregister(&fsl_ddr_mc_err_driver);
+}
+
+module_exit(fsl_ddr_mc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Montavista Software, Inc.");
+module_param(edac_op_state, int, 0444);
+MODULE_PARM_DESC(edac_op_state,
+ "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support
@ 2016-08-09 21:55 ` York Sun
0 siblings, 0 replies; 20+ messages in thread
From: York Sun @ 2016-08-09 21:55 UTC (permalink / raw)
To: linux-arm-kernel
Add DDR EDAC for ARM-based compatible controllers. Both big-endian
and little-endian are supported, as specified in device tree.
Signed-off-by: York Sun <york.sun@nxp.com>
---
Change log
v4: Drop adding atomic_scrub() for arm64
Drop NO_IRQ
v3: no change
v2: Create new driver using shared DDR object
arch/arm64/Kconfig.platforms | 1 +
drivers/edac/Kconfig | 7 +++++
drivers/edac/Makefile | 3 ++
drivers/edac/fsl_ddr_edac.c | 2 +-
drivers/edac/layerscape_edac.c | 67 ++++++++++++++++++++++++++++++++++++++++++
5 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 drivers/edac/layerscape_edac.c
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 7ef1d05..185a215 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -41,6 +41,7 @@ config ARCH_EXYNOS
config ARCH_LAYERSCAPE
bool "ARMv8 based Freescale Layerscape SoC family"
+ select EDAC_SUPPORT
help
This enables support for the Freescale Layerscape SoC family.
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 6ca7474..f1ac4e2 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -258,6 +258,13 @@ config EDAC_MPC85XX
Support for error detection and correction on the Freescale
MPC8349, MPC8560, MPC8540, MPC8548, T4240
+config EDAC_LAYERSCAPE
+ tristate "Freescale Layerscape DDR"
+ depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
+ help
+ Support for error detection and correction on Freescale memory
+ controllers on Layerscape SoCs.
+
config EDAC_MV64X60
tristate "Marvell MV64x60"
depends on EDAC_MM_EDAC && MV64X60
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index ee047a4..910dc83 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -54,6 +54,9 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
+layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
+obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
+
obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
obj-$(CONFIG_EDAC_CELL) += cell_edac.o
obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index d8ce1f6..afade14 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -26,6 +26,7 @@
#include <linux/of_platform.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include "edac_module.h"
#include "edac_core.h"
#include "fsl_ddr_edac.h"
@@ -478,7 +479,6 @@ int fsl_mc_err_probe(struct platform_device *op)
pdata = mci->pvt_info;
pdata->name = "fsl_mc_err";
- pdata->irq = NO_IRQ;
mci->pdev = &op->dev;
pdata->edac_idx = edac_mc_idx++;
dev_set_drvdata(mci->pdev, mci);
diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c
new file mode 100644
index 0000000..6ba771d
--- /dev/null
+++ b/drivers/edac/layerscape_edac.c
@@ -0,0 +1,67 @@
+/*
+ * Freescale Memory Controller kernel module
+ *
+ * Derived from mpc85xx_edac.c
+ * Author: Dave Jiang <djiang@mvista.com>
+ *
+ * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#include "edac_core.h"
+#include "fsl_ddr_edac.h"
+
+static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
+ { .compatible = "fsl,qoriq-memory-controller", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
+
+static struct platform_driver fsl_ddr_mc_err_driver = {
+ .probe = fsl_mc_err_probe,
+ .remove = fsl_mc_err_remove,
+ .driver = {
+ .name = "fsl_ddr_mc_err",
+ .of_match_table = fsl_ddr_mc_err_of_match,
+ },
+};
+
+static int __init fsl_ddr_mc_init(void)
+{
+ int res = 0;
+
+ /* make sure error reporting method is sane */
+ switch (edac_op_state) {
+ case EDAC_OPSTATE_POLL:
+ case EDAC_OPSTATE_INT:
+ break;
+ default:
+ edac_op_state = EDAC_OPSTATE_INT;
+ break;
+ }
+
+ res = platform_driver_register(&fsl_ddr_mc_err_driver);
+ if (res) {
+ pr_err("Layerscape EDAC: MC fails to register\n");
+ return res;
+ }
+
+ return 0;
+}
+
+module_init(fsl_ddr_mc_init);
+
+static void __exit fsl_ddr_mc_exit(void)
+{
+ platform_driver_unregister(&fsl_ddr_mc_err_driver);
+}
+
+module_exit(fsl_ddr_mc_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Montavista Software, Inc.");
+module_param(edac_op_state, int, 0444);
+MODULE_PARM_DESC(edac_op_state,
+ "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
--
2.7.4
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support
2016-08-09 21:55 ` York Sun
@ 2016-08-12 9:12 ` Borislav Petkov
-1 siblings, 0 replies; 20+ messages in thread
From: Borislav Petkov @ 2016-08-12 9:12 UTC (permalink / raw)
To: York Sun
Cc: linux-edac, morbidrsa, oss, stuart.yoder, Catalin Marinas,
Will Deacon, Doug Thompson, mchehab, linux-arm-kernel,
linux-kernel
On Tue, Aug 09, 2016 at 02:55:45PM -0700, York Sun wrote:
> Add DDR EDAC for ARM-based compatible controllers. Both big-endian
> and little-endian are supported, as specified in device tree.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
> Change log
> v4: Drop adding atomic_scrub() for arm64
> Drop NO_IRQ
> v3: no change
> v2: Create new driver using shared DDR object
>
> arch/arm64/Kconfig.platforms | 1 +
> drivers/edac/Kconfig | 7 +++++
> drivers/edac/Makefile | 3 ++
> drivers/edac/fsl_ddr_edac.c | 2 +-
> drivers/edac/layerscape_edac.c | 67 ++++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 79 insertions(+), 1 deletion(-)
> create mode 100644 drivers/edac/layerscape_edac.c
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 7ef1d05..185a215 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -41,6 +41,7 @@ config ARCH_EXYNOS
>
> config ARCH_LAYERSCAPE
> bool "ARMv8 based Freescale Layerscape SoC family"
> + select EDAC_SUPPORT
> help
> This enables support for the Freescale Layerscape SoC family.
>
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 6ca7474..f1ac4e2 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -258,6 +258,13 @@ config EDAC_MPC85XX
> Support for error detection and correction on the Freescale
> MPC8349, MPC8560, MPC8540, MPC8548, T4240
>
> +config EDAC_LAYERSCAPE
> + tristate "Freescale Layerscape DDR"
> + depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
> + help
> + Support for error detection and correction on Freescale memory
> + controllers on Layerscape SoCs.
> +
> config EDAC_MV64X60
> tristate "Marvell MV64x60"
> depends on EDAC_MM_EDAC && MV64X60
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index ee047a4..910dc83 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -54,6 +54,9 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
> mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
> obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
>
> +layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
> +obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
> +
> obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
> obj-$(CONFIG_EDAC_CELL) += cell_edac.o
> obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
> diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
> index d8ce1f6..afade14 100644
> --- a/drivers/edac/fsl_ddr_edac.c
> +++ b/drivers/edac/fsl_ddr_edac.c
> @@ -26,6 +26,7 @@
>
> #include <linux/of_platform.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include "edac_module.h"
> #include "edac_core.h"
> #include "fsl_ddr_edac.h"
> @@ -478,7 +479,6 @@ int fsl_mc_err_probe(struct platform_device *op)
>
> pdata = mci->pvt_info;
> pdata->name = "fsl_mc_err";
> - pdata->irq = NO_IRQ;
> mci->pdev = &op->dev;
> pdata->edac_idx = edac_mc_idx++;
> dev_set_drvdata(mci->pdev, mci);
> diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c
> new file mode 100644
> index 0000000..6ba771d
> --- /dev/null
> +++ b/drivers/edac/layerscape_edac.c
> @@ -0,0 +1,67 @@
> +/*
> + * Freescale Memory Controller kernel module
> + *
> + * Derived from mpc85xx_edac.c
Up to here is fine...
> + * Author: Dave Jiang <djiang@mvista.com>
> + *
> + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
> + * the terms of the GNU General Public License version 2. This program
> + * is licensed "as is" without any warranty of any kind, whether express
> + * or implied.
> + */
... but I'm not sure about this. This is a new driver which you are
adding and not Dave. You probably could say
"Author: York Sun <york.sun@nxp.com>
(c) NXP ...
Derived from mpc85xx_edac.c, (c) Montavista ..."
so that we have both copyright tags in there.
> +
> +#include "edac_core.h"
> +#include "fsl_ddr_edac.h"
> +
> +static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
> + { .compatible = "fsl,qoriq-memory-controller", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
> +
> +static struct platform_driver fsl_ddr_mc_err_driver = {
> + .probe = fsl_mc_err_probe,
> + .remove = fsl_mc_err_remove,
> + .driver = {
> + .name = "fsl_ddr_mc_err",
> + .of_match_table = fsl_ddr_mc_err_of_match,
> + },
> +};
> +
> +static int __init fsl_ddr_mc_init(void)
> +{
> + int res = 0;
No need to init it since it is going to be overwritten anyway.
> +
> + /* make sure error reporting method is sane */
> + switch (edac_op_state) {
> + case EDAC_OPSTATE_POLL:
> + case EDAC_OPSTATE_INT:
> + break;
> + default:
> + edac_op_state = EDAC_OPSTATE_INT;
> + break;
> + }
> +
> + res = platform_driver_register(&fsl_ddr_mc_err_driver);
> + if (res) {
> + pr_err("Layerscape EDAC: MC fails to register\n");
This is done with pr_fmt(). Grep the tree for examples.
You could define EDAC_MOD_STR like the rest of the drivers do.
> + return res;
> + }
> +
> + return 0;
> +}
> +
> +module_init(fsl_ddr_mc_init);
> +
> +static void __exit fsl_ddr_mc_exit(void)
> +{
> + platform_driver_unregister(&fsl_ddr_mc_err_driver);
> +}
> +
> +module_exit(fsl_ddr_mc_exit);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Montavista Software, Inc.");
See above.
> +module_param(edac_op_state, int, 0444);
> +MODULE_PARM_DESC(edac_op_state,
> + "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
> --
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 20+ messages in thread* [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support
@ 2016-08-12 9:12 ` Borislav Petkov
0 siblings, 0 replies; 20+ messages in thread
From: Borislav Petkov @ 2016-08-12 9:12 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 09, 2016 at 02:55:45PM -0700, York Sun wrote:
> Add DDR EDAC for ARM-based compatible controllers. Both big-endian
> and little-endian are supported, as specified in device tree.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
>
> ---
> Change log
> v4: Drop adding atomic_scrub() for arm64
> Drop NO_IRQ
> v3: no change
> v2: Create new driver using shared DDR object
>
> arch/arm64/Kconfig.platforms | 1 +
> drivers/edac/Kconfig | 7 +++++
> drivers/edac/Makefile | 3 ++
> drivers/edac/fsl_ddr_edac.c | 2 +-
> drivers/edac/layerscape_edac.c | 67 ++++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 79 insertions(+), 1 deletion(-)
> create mode 100644 drivers/edac/layerscape_edac.c
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 7ef1d05..185a215 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -41,6 +41,7 @@ config ARCH_EXYNOS
>
> config ARCH_LAYERSCAPE
> bool "ARMv8 based Freescale Layerscape SoC family"
> + select EDAC_SUPPORT
> help
> This enables support for the Freescale Layerscape SoC family.
>
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 6ca7474..f1ac4e2 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -258,6 +258,13 @@ config EDAC_MPC85XX
> Support for error detection and correction on the Freescale
> MPC8349, MPC8560, MPC8540, MPC8548, T4240
>
> +config EDAC_LAYERSCAPE
> + tristate "Freescale Layerscape DDR"
> + depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
> + help
> + Support for error detection and correction on Freescale memory
> + controllers on Layerscape SoCs.
> +
> config EDAC_MV64X60
> tristate "Marvell MV64x60"
> depends on EDAC_MM_EDAC && MV64X60
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index ee047a4..910dc83 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -54,6 +54,9 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
> mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
> obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
>
> +layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
> +obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
> +
> obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
> obj-$(CONFIG_EDAC_CELL) += cell_edac.o
> obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
> diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
> index d8ce1f6..afade14 100644
> --- a/drivers/edac/fsl_ddr_edac.c
> +++ b/drivers/edac/fsl_ddr_edac.c
> @@ -26,6 +26,7 @@
>
> #include <linux/of_platform.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include "edac_module.h"
> #include "edac_core.h"
> #include "fsl_ddr_edac.h"
> @@ -478,7 +479,6 @@ int fsl_mc_err_probe(struct platform_device *op)
>
> pdata = mci->pvt_info;
> pdata->name = "fsl_mc_err";
> - pdata->irq = NO_IRQ;
> mci->pdev = &op->dev;
> pdata->edac_idx = edac_mc_idx++;
> dev_set_drvdata(mci->pdev, mci);
> diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c
> new file mode 100644
> index 0000000..6ba771d
> --- /dev/null
> +++ b/drivers/edac/layerscape_edac.c
> @@ -0,0 +1,67 @@
> +/*
> + * Freescale Memory Controller kernel module
> + *
> + * Derived from mpc85xx_edac.c
Up to here is fine...
> + * Author: Dave Jiang <djiang@mvista.com>
> + *
> + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
> + * the terms of the GNU General Public License version 2. This program
> + * is licensed "as is" without any warranty of any kind, whether express
> + * or implied.
> + */
... but I'm not sure about this. This is a new driver which you are
adding and not Dave. You probably could say
"Author: York Sun <york.sun@nxp.com>
(c) NXP ...
Derived from mpc85xx_edac.c, (c) Montavista ..."
so that we have both copyright tags in there.
> +
> +#include "edac_core.h"
> +#include "fsl_ddr_edac.h"
> +
> +static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
> + { .compatible = "fsl,qoriq-memory-controller", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
> +
> +static struct platform_driver fsl_ddr_mc_err_driver = {
> + .probe = fsl_mc_err_probe,
> + .remove = fsl_mc_err_remove,
> + .driver = {
> + .name = "fsl_ddr_mc_err",
> + .of_match_table = fsl_ddr_mc_err_of_match,
> + },
> +};
> +
> +static int __init fsl_ddr_mc_init(void)
> +{
> + int res = 0;
No need to init it since it is going to be overwritten anyway.
> +
> + /* make sure error reporting method is sane */
> + switch (edac_op_state) {
> + case EDAC_OPSTATE_POLL:
> + case EDAC_OPSTATE_INT:
> + break;
> + default:
> + edac_op_state = EDAC_OPSTATE_INT;
> + break;
> + }
> +
> + res = platform_driver_register(&fsl_ddr_mc_err_driver);
> + if (res) {
> + pr_err("Layerscape EDAC: MC fails to register\n");
This is done with pr_fmt(). Grep the tree for examples.
You could define EDAC_MOD_STR like the rest of the drivers do.
> + return res;
> + }
> +
> + return 0;
> +}
> +
> +module_init(fsl_ddr_mc_init);
> +
> +static void __exit fsl_ddr_mc_exit(void)
> +{
> + platform_driver_unregister(&fsl_ddr_mc_err_driver);
> +}
> +
> +module_exit(fsl_ddr_mc_exit);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Montavista Software, Inc.");
See above.
> +module_param(edac_op_state, int, 0444);
> +MODULE_PARM_DESC(edac_op_state,
> + "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
> --
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
--
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support
2016-08-12 9:12 ` Borislav Petkov
@ 2016-08-23 16:46 ` york sun
-1 siblings, 0 replies; 20+ messages in thread
From: york sun @ 2016-08-23 16:46 UTC (permalink / raw)
To: Borislav Petkov
Cc: linux-edac, morbidrsa, oss, Stuart Yoder, Catalin Marinas,
Will Deacon, Doug Thompson, mchehab, linux-arm-kernel,
linux-kernel
On 08/12/2016 02:13 AM, Borislav Petkov wrote:
> On Tue, Aug 09, 2016 at 02:55:45PM -0700, York Sun wrote:
>> Add DDR EDAC for ARM-based compatible controllers. Both big-endian
>> and little-endian are supported, as specified in device tree.
>>
>> Signed-off-by: York Sun <york.sun@nxp.com>
>>
>> ---
>> Change log
>> v4: Drop adding atomic_scrub() for arm64
>> Drop NO_IRQ
>> v3: no change
>> v2: Create new driver using shared DDR object
>>
>> arch/arm64/Kconfig.platforms | 1 +
>> drivers/edac/Kconfig | 7 +++++
>> drivers/edac/Makefile | 3 ++
>> drivers/edac/fsl_ddr_edac.c | 2 +-
>> drivers/edac/layerscape_edac.c | 67 ++++++++++++++++++++++++++++++++++++++++++
>> 5 files changed, 79 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/edac/layerscape_edac.c
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 7ef1d05..185a215 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -41,6 +41,7 @@ config ARCH_EXYNOS
>>
>> config ARCH_LAYERSCAPE
>> bool "ARMv8 based Freescale Layerscape SoC family"
>> + select EDAC_SUPPORT
>> help
>> This enables support for the Freescale Layerscape SoC family.
>>
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 6ca7474..f1ac4e2 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -258,6 +258,13 @@ config EDAC_MPC85XX
>> Support for error detection and correction on the Freescale
>> MPC8349, MPC8560, MPC8540, MPC8548, T4240
>>
>> +config EDAC_LAYERSCAPE
>> + tristate "Freescale Layerscape DDR"
>> + depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
>> + help
>> + Support for error detection and correction on Freescale memory
>> + controllers on Layerscape SoCs.
>> +
>> config EDAC_MV64X60
>> tristate "Marvell MV64x60"
>> depends on EDAC_MM_EDAC && MV64X60
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> index ee047a4..910dc83 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -54,6 +54,9 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
>> mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
>> obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
>>
>> +layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
>> +obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
>> +
>> obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
>> obj-$(CONFIG_EDAC_CELL) += cell_edac.o
>> obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
>> diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
>> index d8ce1f6..afade14 100644
>> --- a/drivers/edac/fsl_ddr_edac.c
>> +++ b/drivers/edac/fsl_ddr_edac.c
>> @@ -26,6 +26,7 @@
>>
>> #include <linux/of_platform.h>
>> #include <linux/of_device.h>
>> +#include <linux/of_address.h>
>> #include "edac_module.h"
>> #include "edac_core.h"
>> #include "fsl_ddr_edac.h"
>> @@ -478,7 +479,6 @@ int fsl_mc_err_probe(struct platform_device *op)
>>
>> pdata = mci->pvt_info;
>> pdata->name = "fsl_mc_err";
>> - pdata->irq = NO_IRQ;
>> mci->pdev = &op->dev;
>> pdata->edac_idx = edac_mc_idx++;
>> dev_set_drvdata(mci->pdev, mci);
>> diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c
>> new file mode 100644
>> index 0000000..6ba771d
>> --- /dev/null
>> +++ b/drivers/edac/layerscape_edac.c
>> @@ -0,0 +1,67 @@
>> +/*
>> + * Freescale Memory Controller kernel module
>> + *
>> + * Derived from mpc85xx_edac.c
>
> Up to here is fine...
>
>> + * Author: Dave Jiang <djiang@mvista.com>
>> + *
>> + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
>> + * the terms of the GNU General Public License version 2. This program
>> + * is licensed "as is" without any warranty of any kind, whether express
>> + * or implied.
>> + */
>
> ... but I'm not sure about this. This is a new driver which you are
> adding and not Dave. You probably could say
>
> "Author: York Sun <york.sun@nxp.com>
> (c) NXP ...
>
> Derived from mpc85xx_edac.c, (c) Montavista ..."
>
> so that we have both copyright tags in there.
>
Sorry for the late response. I was out of office last week. Will respin
this patch.
>> +
>> +#include "edac_core.h"
>> +#include "fsl_ddr_edac.h"
>> +
>> +static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
>> + { .compatible = "fsl,qoriq-memory-controller", },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
>> +
>> +static struct platform_driver fsl_ddr_mc_err_driver = {
>> + .probe = fsl_mc_err_probe,
>> + .remove = fsl_mc_err_remove,
>> + .driver = {
>> + .name = "fsl_ddr_mc_err",
>> + .of_match_table = fsl_ddr_mc_err_of_match,
>> + },
>> +};
>> +
>> +static int __init fsl_ddr_mc_init(void)
>> +{
>> + int res = 0;
>
> No need to init it since it is going to be overwritten anyway.
OK.
>
>> +
>> + /* make sure error reporting method is sane */
>> + switch (edac_op_state) {
>> + case EDAC_OPSTATE_POLL:
>> + case EDAC_OPSTATE_INT:
>> + break;
>> + default:
>> + edac_op_state = EDAC_OPSTATE_INT;
>> + break;
>> + }
>> +
>> + res = platform_driver_register(&fsl_ddr_mc_err_driver);
>> + if (res) {
>> + pr_err("Layerscape EDAC: MC fails to register\n");
>
> This is done with pr_fmt(). Grep the tree for examples.
>
> You could define EDAC_MOD_STR like the rest of the drivers do.
>
Will fix.
>
>
>> + return res;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +module_init(fsl_ddr_mc_init);
>> +
>> +static void __exit fsl_ddr_mc_exit(void)
>> +{
>> + platform_driver_unregister(&fsl_ddr_mc_err_driver);
>> +}
>> +
>> +module_exit(fsl_ddr_mc_exit);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Montavista Software, Inc.");
>
> See above.
Will fix.
>
>> +module_param(edac_op_state, int, 0444);
>> +MODULE_PARM_DESC(edac_op_state,
>> + "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
>> --
>
York
^ permalink raw reply [flat|nested] 20+ messages in thread* [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support
@ 2016-08-23 16:46 ` york sun
0 siblings, 0 replies; 20+ messages in thread
From: york sun @ 2016-08-23 16:46 UTC (permalink / raw)
To: linux-arm-kernel
On 08/12/2016 02:13 AM, Borislav Petkov wrote:
> On Tue, Aug 09, 2016 at 02:55:45PM -0700, York Sun wrote:
>> Add DDR EDAC for ARM-based compatible controllers. Both big-endian
>> and little-endian are supported, as specified in device tree.
>>
>> Signed-off-by: York Sun <york.sun@nxp.com>
>>
>> ---
>> Change log
>> v4: Drop adding atomic_scrub() for arm64
>> Drop NO_IRQ
>> v3: no change
>> v2: Create new driver using shared DDR object
>>
>> arch/arm64/Kconfig.platforms | 1 +
>> drivers/edac/Kconfig | 7 +++++
>> drivers/edac/Makefile | 3 ++
>> drivers/edac/fsl_ddr_edac.c | 2 +-
>> drivers/edac/layerscape_edac.c | 67 ++++++++++++++++++++++++++++++++++++++++++
>> 5 files changed, 79 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/edac/layerscape_edac.c
>>
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 7ef1d05..185a215 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -41,6 +41,7 @@ config ARCH_EXYNOS
>>
>> config ARCH_LAYERSCAPE
>> bool "ARMv8 based Freescale Layerscape SoC family"
>> + select EDAC_SUPPORT
>> help
>> This enables support for the Freescale Layerscape SoC family.
>>
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 6ca7474..f1ac4e2 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -258,6 +258,13 @@ config EDAC_MPC85XX
>> Support for error detection and correction on the Freescale
>> MPC8349, MPC8560, MPC8540, MPC8548, T4240
>>
>> +config EDAC_LAYERSCAPE
>> + tristate "Freescale Layerscape DDR"
>> + depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
>> + help
>> + Support for error detection and correction on Freescale memory
>> + controllers on Layerscape SoCs.
>> +
>> config EDAC_MV64X60
>> tristate "Marvell MV64x60"
>> depends on EDAC_MM_EDAC && MV64X60
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> index ee047a4..910dc83 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -54,6 +54,9 @@ obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
>> mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o
>> obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o
>>
>> +layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o
>> +obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o
>> +
>> obj-$(CONFIG_EDAC_MV64X60) += mv64x60_edac.o
>> obj-$(CONFIG_EDAC_CELL) += cell_edac.o
>> obj-$(CONFIG_EDAC_PPC4XX) += ppc4xx_edac.o
>> diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
>> index d8ce1f6..afade14 100644
>> --- a/drivers/edac/fsl_ddr_edac.c
>> +++ b/drivers/edac/fsl_ddr_edac.c
>> @@ -26,6 +26,7 @@
>>
>> #include <linux/of_platform.h>
>> #include <linux/of_device.h>
>> +#include <linux/of_address.h>
>> #include "edac_module.h"
>> #include "edac_core.h"
>> #include "fsl_ddr_edac.h"
>> @@ -478,7 +479,6 @@ int fsl_mc_err_probe(struct platform_device *op)
>>
>> pdata = mci->pvt_info;
>> pdata->name = "fsl_mc_err";
>> - pdata->irq = NO_IRQ;
>> mci->pdev = &op->dev;
>> pdata->edac_idx = edac_mc_idx++;
>> dev_set_drvdata(mci->pdev, mci);
>> diff --git a/drivers/edac/layerscape_edac.c b/drivers/edac/layerscape_edac.c
>> new file mode 100644
>> index 0000000..6ba771d
>> --- /dev/null
>> +++ b/drivers/edac/layerscape_edac.c
>> @@ -0,0 +1,67 @@
>> +/*
>> + * Freescale Memory Controller kernel module
>> + *
>> + * Derived from mpc85xx_edac.c
>
> Up to here is fine...
>
>> + * Author: Dave Jiang <djiang@mvista.com>
>> + *
>> + * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
>> + * the terms of the GNU General Public License version 2. This program
>> + * is licensed "as is" without any warranty of any kind, whether express
>> + * or implied.
>> + */
>
> ... but I'm not sure about this. This is a new driver which you are
> adding and not Dave. You probably could say
>
> "Author: York Sun <york.sun@nxp.com>
> (c) NXP ...
>
> Derived from mpc85xx_edac.c, (c) Montavista ..."
>
> so that we have both copyright tags in there.
>
Sorry for the late response. I was out of office last week. Will respin
this patch.
>> +
>> +#include "edac_core.h"
>> +#include "fsl_ddr_edac.h"
>> +
>> +static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
>> + { .compatible = "fsl,qoriq-memory-controller", },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
>> +
>> +static struct platform_driver fsl_ddr_mc_err_driver = {
>> + .probe = fsl_mc_err_probe,
>> + .remove = fsl_mc_err_remove,
>> + .driver = {
>> + .name = "fsl_ddr_mc_err",
>> + .of_match_table = fsl_ddr_mc_err_of_match,
>> + },
>> +};
>> +
>> +static int __init fsl_ddr_mc_init(void)
>> +{
>> + int res = 0;
>
> No need to init it since it is going to be overwritten anyway.
OK.
>
>> +
>> + /* make sure error reporting method is sane */
>> + switch (edac_op_state) {
>> + case EDAC_OPSTATE_POLL:
>> + case EDAC_OPSTATE_INT:
>> + break;
>> + default:
>> + edac_op_state = EDAC_OPSTATE_INT;
>> + break;
>> + }
>> +
>> + res = platform_driver_register(&fsl_ddr_mc_err_driver);
>> + if (res) {
>> + pr_err("Layerscape EDAC: MC fails to register\n");
>
> This is done with pr_fmt(). Grep the tree for examples.
>
> You could define EDAC_MOD_STR like the rest of the drivers do.
>
Will fix.
>
>
>> + return res;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +module_init(fsl_ddr_mc_init);
>> +
>> +static void __exit fsl_ddr_mc_exit(void)
>> +{
>> + platform_driver_unregister(&fsl_ddr_mc_err_driver);
>> +}
>> +
>> +module_exit(fsl_ddr_mc_exit);
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_AUTHOR("Montavista Software, Inc.");
>
> See above.
Will fix.
>
>> +module_param(edac_op_state, int, 0444);
>> +MODULE_PARM_DESC(edac_op_state,
>> + "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
>> --
>
York
^ permalink raw reply [flat|nested] 20+ messages in thread