[U-Boot] [PATCH 5/5][v5] arch: powerpc: update the eLBC IP input clock

[U-Boot] [PATCH 5/5][v5] arch: powerpc: update the eLBC IP input clock

[Prabhakar Kushwaha]

eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output clock.

So update eLBC IP clock to be defined as per predefined clock
divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
 README                           |  3 +++
 arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++++++++++++++
 arch/powerpc/cpu/mpc85xx/speed.c | 28 ++--------------------------
 arch/powerpc/cpu/mpc86xx/speed.c | 14 +-------------
 4 files changed, 20 insertions(+), 39 deletions(-)

diff --git a/README b/README
index 9fda381..b27e757 100644
--- a/README
+++ b/README
@@ -507,6 +507,9 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_IFC_CLK_DIV
 		Defines divider of platform clock(clock input to IFC controller).
 
+		CONFIG_SYS_FSL_LBC_CLK_DIV
+		Defines divider of platform clock(clock input to eLBC controller).
+
 		CONFIG_SYS_FSL_PBL_PBI
 		It enables addition of RCW (Power on reset configuration) in built image.
 		Please refer doc/README.pblimage for more details
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 765d328..7442495 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1307,6 +1307,20 @@ config SYS_FSL_IFC_CLK_DIV
 		Defines divider of platform clock(clock input to
 		IFC controller).
 
+config SYS_FSL_LBC_CLK_DIV
+	int "Divider of platform clock"
+	depends on FSL_ELBC
+	default 2 if	ARCH_P2041	|| \
+			ARCH_P3041	|| \
+			ARCH_P4080	|| \
+			ARCH_P5020	|| \
+			ARCH_P5040
+	default 1
+
+	help
+		Defines divider of platform clock(clock input to
+		eLBC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index adba092..cb8281e 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -607,32 +607,8 @@ void get_sys_info(sys_info_t *sys_info)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
-	uint lcrr_div;
-#if defined(CONFIG_SYS_LBC_LCRR)
-	/* We will program LCRR to this value later */
-	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
-#endif
-	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-#if defined(CONFIG_FSL_CORENET)
-		/* If this is corenet based SoC, bit-representation
-		 * for four times the clock divider values.
-		 */
-		lcrr_div *= 4;
-#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
-	!defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
-		/*
-		 * Yes, the entire PQ38 family use the same
-		 * bit-representation for twice the clock divider values.
-		 */
-		lcrr_div *= 2;
-#endif
-		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
-	} else {
-		/* In case anyone cares what the unknown value is */
-		sys_info->freq_localbus = lcrr_div;
-	}
+	sys_info->freq_localbus = sys_info->freq_systembus /
+						CONFIG_SYS_FSL_LBC_CLK_DIV;
 #endif
 
 #if defined(CONFIG_FSL_IFC)
diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c
index 05f23db..b9e2100 100644
--- a/arch/powerpc/cpu/mpc86xx/speed.c
+++ b/arch/powerpc/cpu/mpc86xx/speed.c
@@ -78,19 +78,7 @@ void get_sys_info(sys_info_t *sys_info)
 		break;
 	}
 
-#if defined(CONFIG_SYS_LBC_LCRR)
-	/* We will program LCRR to this value later */
-	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
-#else
-	lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
-#endif
-	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
-		sys_info->freq_localbus = sys_info->freq_systembus
-							/ (lcrr_div * 2);
-	} else {
-		/* In case anyone cares what the unknown value is */
-		sys_info->freq_localbus = lcrr_div;
-	}
+	sys_info->freq_localbus = sys_info->freq_systembus;
 }
 
 
-- 
2.7.4

[U-Boot] [PATCH 5/5][v5] arch: powerpc: update the eLBC IP input clock

[york sun]

On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
> eLBC IP clock is always a constant divisor of platform clock
> pre-defined per SoC. Clock ratio register (LCRR) used in
> current implementation governs eLBC IP output clock.
>
> So update eLBC IP clock to be defined as per predefined clock
> divisor of platform clock.
>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> ---
>  README                           |  3 +++
>  arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++++++++++++++
>  arch/powerpc/cpu/mpc85xx/speed.c | 28 ++--------------------------
>  arch/powerpc/cpu/mpc86xx/speed.c | 14 +-------------
>  4 files changed, 20 insertions(+), 39 deletions(-)
>

Prabhakar,

This patch has compiling error for 86xx. Please check.

York

[U-Boot] [PATCH 5/5][v5] arch: powerpc: update the eLBC IP input clock

[york sun]

On 01/30/2017 08:43 AM, york.sun at nxp.com wrote:
> On 01/24/2017 02:35 AM, Prabhakar Kushwaha wrote:
>> eLBC IP clock is always a constant divisor of platform clock
>> pre-defined per SoC. Clock ratio register (LCRR) used in
>> current implementation governs eLBC IP output clock.
>>
>> So update eLBC IP clock to be defined as per predefined clock
>> divisor of platform clock.
>>
>> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
>> ---
>>  README                           |  3 +++
>>  arch/powerpc/cpu/mpc85xx/Kconfig | 14 ++++++++++++++
>>  arch/powerpc/cpu/mpc85xx/speed.c | 28 ++--------------------------
>>  arch/powerpc/cpu/mpc86xx/speed.c | 14 +-------------
>>  4 files changed, 20 insertions(+), 39 deletions(-)
>>
>
> Prabhakar,
>
> This patch has compiling error for 86xx. Please check.
>
>

Correction, it has compiling warning, not error.

York