From: york sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node
Date: Mon, 14 Nov 2016 21:24:02 +0000 [thread overview]
Message-ID: <AM4PR0401MB17328AA3D1DED003CB23E0859ABC0@AM4PR0401MB1732.eurprd04.prod.outlook.com> (raw)
In-Reply-To: 1477970547-28846-1-git-send-email-wenbin.song@nxp.com
On 10/31/2016 08:35 PM, Wenbin song wrote:
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K alignment
> and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT] is used to choose
> which offset will be used. If GIC_ADDR_BIT bit is set, 4K alignment is used,
> or else 64K alignment is used. The rev1.0 silicon only supports the CIG offset
> with 4K alignment.
Wenbin,
According to your patch and your explanation, the rev 1 SoC supports 4K
alignment only. The rev 1.1 and newer SoC supports both 4K and 64K. If
you don't do anything in PBI, the default is 64K. Does this 64k
alignment apply to any other SoCs?
York
next prev parent reply other threads:[~2016-11-14 21:24 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 3:22 [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node Wenbin song
2016-11-01 3:22 ` [U-Boot] [PATCH v6 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node Wenbin song
2016-11-14 21:36 ` york sun
2016-11-16 3:52 ` Wenbin Song
2016-11-14 21:24 ` york sun [this message]
2016-11-16 9:23 ` [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node Wenbin Song
2016-11-16 17:04 ` york sun
2016-11-17 1:14 ` Wenbin Song
2016-12-08 19:06 ` york sun
2016-12-09 9:58 ` Wenbin Song
2016-12-09 15:47 ` york sun
2017-01-04 19:22 ` york sun
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