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From: Wenbin Song <wenbin.song@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node
Date: Thu, 17 Nov 2016 01:14:11 +0000	[thread overview]
Message-ID: <VI1PR0402MB2783A40261D872DEBAB9A804F1B10@VI1PR0402MB2783.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <AM4PR0401MB173238AC9FAB1150E435391C9ABE0@AM4PR0401MB1732.eurprd04.prod.outlook.com>

Hi, york

Best Regards
Wenbin Song


> -----Original Message-----
> From: york sun
> Sent: Thursday, November 17, 2016 1:05 AM
> To: Wenbin Song <wenbin.song@nxp.com>; albert.u.boot at aribaud.net;
> Mingkai Hu <mingkai.hu@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 11/16/2016 01:23 AM, Wenbin Song wrote:
> > Hi: york
> >
> > Best Regards
> > Wenbin Song
> >
> >
> >> -----Original Message-----
> >> From: york sun
> >> Sent: Tuesday, November 15, 2016 5:24 AM
> >> To: Wenbin Song <wenbin.song@nxp.com>; albert.u.boot at aribaud.net;
> >> Mingkai Hu <mingkai.hu@nxp.com>; u-boot at lists.denx.de
> >> Subject: Re: [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A
> >> rev1 GIC node
> >>
> >> On 10/31/2016 08:35 PM, Wenbin song wrote:
> >>> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> >>> alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> >>> is used to choose which offset will be used. If GIC_ADDR_BIT bit is
> >>> set, 4K alignment is used, or else 64K alignment is used. The rev1.0
> >>> silicon only supports the CIG offset with 4K alignment.
> >>
> >> Wenbin,
> >>
> >> According to your patch and your explanation, the rev 1 SoC supports
> >> 4K alignment only. The rev 1.1 and newer SoC supports both 4K and
> >> 64K. If you don't do anything in PBI, the default is 64K.
> >
> > [] yes. You are  correct .
> 
> I would prefer it has 4K alignment if you do nothing in PBI. But I guess it is too
> late to change the hardware.
> 
> >
> > Does this 64k alignment apply to
> >> any other SoCs?
> >>
> > []   This patch only apply  to ls1043a.  and the other SOCs  only support one
> kind of alignment style.  For example, ls1046a align with 64k, ls1012a align with
> 4k.
> 
> In this case, you patch is OK. You can add full SVR check if a future SoC needs
> the same fix.

[]  ok, I will make this change  in the next version of the patch.
 

> 
> York

  reply	other threads:[~2016-11-17  1:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-01  3:22 [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node Wenbin song
2016-11-01  3:22 ` [U-Boot] [PATCH v6 2/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 MSI node Wenbin song
2016-11-14 21:36   ` york sun
2016-11-16  3:52     ` Wenbin Song
2016-11-14 21:24 ` [U-Boot] [PATCH v6 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node york sun
2016-11-16  9:23   ` Wenbin Song
2016-11-16 17:04     ` york sun
2016-11-17  1:14       ` Wenbin Song [this message]
2016-12-08 19:06         ` york sun
2016-12-09  9:58           ` Wenbin Song
2016-12-09 15:47             ` york sun
2017-01-04 19:22             ` york sun

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