* [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support
@ 2017-01-19 5:42 Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 1/3] armv8: fsl-layerscape: Updates DCFG register map Priyanka Jain
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Priyanka Jain @ 2017-01-19 5:42 UTC (permalink / raw)
To: u-boot
Priyanka Jain (3):
armv8: fsl-layerscape: Updates DCFG register map.
armv8: fsl-lsch3: Update VID support
armv8: fsl-layerscape: Add vid support for LS2080AQDS.
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 69 ++++++---
board/freescale/common/vid.c | 174 ++++++++++++++++++--
board/freescale/ls2080aqds/ls2080aqds.c | 9 +
3 files changed, 219 insertions(+), 33 deletions(-)
--
1.7.4.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 1/3] armv8: fsl-layerscape: Updates DCFG register map
2017-01-19 5:42 [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support Priyanka Jain
@ 2017-01-19 5:42 ` Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support Priyanka Jain
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: Priyanka Jain @ 2017-01-19 5:42 UTC (permalink / raw)
To: u-boot
Based on latest hardware documentation,
update ccsr_gur structure (represents DCFG register map)
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 65 ++++++++++++++------
1 files changed, 46 insertions(+), 19 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index e18dcbd..38a6d03 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -184,21 +184,23 @@ struct ccsr_gur {
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
+ u32 gpporcr3;
+ u32 gpporcr4;
+ u8 res_030[0x60-0x30];
#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
u32 dcfg_fusesr; /* Fuse status register */
- u32 gpporcr3;
- u32 gpporcr4;
- u8 res_034[0x70-0x34];
- u32 devdisr; /* Device disable control */
+ u8 res_064[0x70-0x64];
+ u32 devdisr; /* Device disable control 1 */
u32 devdisr2; /* Device disable control 2 */
u32 devdisr3; /* Device disable control 3 */
u32 devdisr4; /* Device disable control 4 */
u32 devdisr5; /* Device disable control 5 */
u32 devdisr6; /* Device disable control 6 */
- u32 devdisr7; /* Device disable control 7 */
+ u8 res_088[0x94-0x88];
+ u32 coredisr; /* Device disable control 7 */
#define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
#define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
#define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
@@ -223,15 +225,11 @@ struct ccsr_gur {
#define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
#define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
#define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
- u8 res_08c[0x90-0x8c];
- u32 coredisru; /* uppper portion for support of 64 cores */
- u32 coredisrl; /* lower portion for support of 64 cores */
u8 res_098[0xa0-0x98];
u32 pvr; /* Processor version */
u32 svr; /* System version */
- u32 mvr; /* Manufacturing version */
- u8 res_0ac[0x100-0xac];
- u32 rcwsr[32]; /* Reset control word status */
+ u8 res_0a8[0x100-0xa8];
+ u32 rcwsr[30]; /* Reset control word status */
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
#define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
@@ -246,24 +244,53 @@ struct ccsr_gur {
#define RCW_SB_EN_REG_INDEX 9
#define RCW_SB_EN_MASK 0x00000400
- u8 res_180[0x200-0x180];
- u32 scratchrw[32]; /* Scratch Read/Write */
- u8 res_280[0x300-0x280];
+ u8 res_178[0x200-0x178];
+ u32 scratchrw[16]; /* Scratch Read/Write */
+ u8 res_240[0x300-0x240];
u32 scratchw1r[4]; /* Scratch Read (Write once) */
u8 res_310[0x400-0x310];
u32 bootlocptrl; /* Boot location pointer low-order addr */
u32 bootlocptrh; /* Boot location pointer high-order addr */
- u8 res_408[0x500-0x408];
- u8 res_500[0x740-0x500]; /* add more registers when needed */
+ u8 res_408[0x520-0x408];
+ u32 usb1_amqr;
+ u32 usb2_amqr;
+ u8 res_528[0x530-0x528]; /* add more registers when needed */
+ u32 sdmm1_amqr;
+ u8 res_534[0x550-0x534]; /* add more registers when needed */
+ u32 sata1_amqr;
+ u32 sata2_amqr;
+ u8 res_558[0x570-0x558]; /* add more registers when needed */
+ u32 misc1_amqr;
+ u8 res_574[0x590-0x574]; /* add more registers when needed */
+ u32 spare1_amqr;
+ u32 spare2_amqr;
+ u8 res_598[0x620-0x598]; /* add more registers when needed */
+ u32 gencr[7]; /* General Control Registers */
+ u8 res_63c[0x640-0x63c]; /* add more registers when needed */
+ u32 cgensr1; /* Core General Status Register */
+ u8 res_644[0x660-0x644]; /* add more registers when needed */
+ u32 cgencr1; /* Core General Control Register */
+ u8 res_664[0x740-0x664]; /* add more registers when needed */
u32 tp_ityp[64]; /* Topology Initiator Type Register */
struct {
u32 upper;
u32 lower;
- } tp_cluster[3]; /* Core Cluster n Topology Register */
- u8 res_858[0x1000-0x858];
+ } tp_cluster[4]; /* Core cluster n Topology Register */
+ u8 res_864[0x920-0x864]; /* add more registers when needed */
+ u32 ioqoscr[8]; /*I/O Quality of Services Register */
+ u32 uccr;
+ u8 res_944[0x960-0x944]; /* add more registers when needed */
+ u32 ftmcr;
+ u8 res_964[0x990-0x964]; /* add more registers when needed */
+ u32 coredisablesr;
+ u8 res_994[0xa00-0x994]; /* add more registers when needed */
+ u32 sdbgcr; /*Secure Debug Confifuration Register */
+ u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
+ u32 ipbrr1;
+ u32 ipbrr2;
+ u8 res_858[0x1000-0xc00];
};
-
struct ccsr_clk_cluster_group {
struct {
u8 res_00[0x10];
--
1.7.4.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support
2017-01-19 5:42 [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 1/3] armv8: fsl-layerscape: Updates DCFG register map Priyanka Jain
@ 2017-01-19 5:42 ` Priyanka Jain
2017-01-27 17:42 ` york sun
2017-01-19 5:42 ` [U-Boot] [PATCH 3/3] armv8: fsl-layerscape: Add vid support for LS2080AQDS Priyanka Jain
2017-03-09 21:29 ` [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support york sun
3 siblings, 1 reply; 10+ messages in thread
From: Priyanka Jain @ 2017-01-19 5:42 UTC (permalink / raw)
To: u-boot
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
LS2088A, LS2080A differs from existing logic.
-VDD voltage array is different
-Registers are different
-VDD calculation logic is different
Add new function adjust_vdd() for LSCH3 compliant SoCs
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
board/freescale/common/vid.c | 174 ++++++++++++++++++--
2 files changed, 164 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 38a6d03..fc4d33b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -187,9 +187,9 @@ struct ccsr_gur {
u32 gpporcr3;
u32 gpporcr4;
u8 res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
u32 dcfg_fusesr; /* Fuse status register */
u8 res_064[0x70-0x64];
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 1a50304..9b65c13 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -284,10 +284,170 @@ static int set_voltage(int i2caddress, int vdd)
return vdd_last;
}
+#ifdef CONFIG_FSL_LSCH3
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
-#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
+ struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid, buf;
+ int vdd_target, vdd_current, vdd_last;
+ int ret, i2caddress;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 10500,
+ 0, /* reserved */
+ 9750,
+ 0, /* reserved */
+ 9500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 10000, /* 1.0000V */
+ 0, /* reserved */
+ 10250,
+ 0, /* reserved */
+ 10500,
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ debug("VID: I2C failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+ ret = find_ir_chip_on_i2c();
+ if (ret < 0) {
+ printf("VID: Could not find voltage regulator on I2C.\n");
+ ret = -1;
+ goto exit;
+ } else {
+ i2caddress = ret;
+ debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
+ }
+
+ /* check IR chip work on Intel mode*/
+ ret = i2c_read(i2caddress,
+ IR36021_INTEL_MODE_OOFSET,
+ 1, (void *)&buf, 1);
+ if (ret) {
+ printf("VID: failed to read IR chip mode.\n");
+ ret = -1;
+ goto exit;
+ }
+ if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+ printf("VID: IR Chip is not used in Intel mode.\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_le32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+ if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+ vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+ }
+ vdd_target = vdd[vid];
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv(CONFIG_VID_FLS_ENV);
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+
+ if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
+ vdd_target = vdd_override * 10; /* convert to 1/10 mV */
+ debug("VDD override is %lu\n", vdd_override);
+ } else if (vdd_override != 0) {
+ printf("Invalid value.\n");
+ }
+
+ /* divide and round up by 10 to get a value in mV */
+ vdd_target = DIV_ROUND_UP(vdd_target, 10);
+ if (vdd_target == 0) {
+ debug("VID: VID not used\n");
+ ret = 0;
+ goto exit;
+ } else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
+ /* Check vdd_target is in valid range */
+ printf("VID: Target VID %d mV is not in range.\n",
+ vdd_target);
+ ret = -1;
+ goto exit;
+ } else {
+ debug("VID: vid = %d mV\n", vdd_target);
+ }
+
+ /*
+ * Read voltage monitor to check real voltage.
+ */
+ vdd_last = read_voltage(i2caddress);
+ if (vdd_last < 0) {
+ printf("VID: Couldn't read sensor abort VID adjustment\n");
+ ret = -1;
+ goto exit;
+ }
+ vdd_current = vdd_last;
+ debug("VID: Core voltage is currently at %d mV\n", vdd_last);
+ /*
+ * Adjust voltage to@or one step above target.
+ * As measurements are less precise than setting the values
+ * we may run through dummy steps that cancel each other
+ * when stepping up and then down.
+ */
+ while (vdd_last > 0 &&
+ vdd_last < vdd_target) {
+ vdd_current += IR_VDD_STEP_UP;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+ while (vdd_last > 0 &&
+ vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
+ vdd_current -= IR_VDD_STEP_DOWN;
+ vdd_last = set_voltage(i2caddress, vdd_current);
+ }
+
+ if (vdd_last > 0)
+ printf("VID: Core voltage after adjustment is at %d mV\n",
+ vdd_last);
+ else
+ ret = -1;
+exit:
+ if (re_enable)
+ enable_interrupts();
+ i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
+ return ret;
+}
+#else /* !CONFIG_FSL_LSCH3 */
+int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+#if defined(CONFIG_FSL_LSCH2)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
@@ -364,11 +524,7 @@ int adjust_vdd(ulong vdd_override)
}
/* get the voltage ID from fuse status register */
-#ifdef CONFIG_FSL_LSCH3
- fusesr = in_le32(&gur->dcfg_fusesr);
-#else
fusesr = in_be32(&gur->dcfg_fusesr);
-#endif
/*
* VID is used according to the table below
* ---------------------------------------
@@ -393,13 +549,6 @@ int adjust_vdd(ulong vdd_override)
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
}
-#elif defined(CONFIG_FSL_LSCH3)
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
- if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
- vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
- FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
- }
#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
@@ -472,6 +621,7 @@ exit:
return ret;
}
+#endif
static int print_vdd(void)
{
--
1.7.4.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 3/3] armv8: fsl-layerscape: Add vid support for LS2080AQDS
2017-01-19 5:42 [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 1/3] armv8: fsl-layerscape: Updates DCFG register map Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support Priyanka Jain
@ 2017-01-19 5:42 ` Priyanka Jain
2017-03-09 21:29 ` [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support york sun
3 siblings, 0 replies; 10+ messages in thread
From: Priyanka Jain @ 2017-01-19 5:42 UTC (permalink / raw)
To: u-boot
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
---
board/freescale/ls2080aqds/ls2080aqds.c | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 73a61fd..dbe4cf7 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -22,6 +22,7 @@
#include "../common/qixis.h"
#include "ls2080aqds_qixis.h"
+#include "../common/vid.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@@ -240,6 +241,14 @@ int board_early_init_f(void)
return 0;
}
+int misc_init_r(void)
+{
+ if (adjust_vdd(0))
+ printf("Warning: Adjusting core voltage failed.\n");
+
+ return 0;
+}
+
void detail_board_ddr_info(void)
{
puts("\nDDR ");
--
1.7.4.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support
2017-01-19 5:42 ` [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support Priyanka Jain
@ 2017-01-27 17:42 ` york sun
2017-01-30 7:21 ` Priyanka Jain
0 siblings, 1 reply; 10+ messages in thread
From: york sun @ 2017-01-27 17:42 UTC (permalink / raw)
To: u-boot
On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
> LS2088A, LS2080A differs from existing logic.
> -VDD voltage array is different
> -Registers are different
> -VDD calculation logic is different
>
> Add new function adjust_vdd() for LSCH3 compliant SoCs
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
> ---
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
> board/freescale/common/vid.c | 174 ++++++++++++++++++--
> 2 files changed, 164 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> index 38a6d03..fc4d33b 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> @@ -187,9 +187,9 @@ struct ccsr_gur {
> u32 gpporcr3;
> u32 gpporcr4;
> u8 res_030[0x60-0x30];
> -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
> +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
> #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
> -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
> +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
> #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
Priyanka,
You changed the fuse register offset and fuse position in this and
previous patch of this set. What's going on? I presume you have verified
it on LS2080ARDB. How did it work before? Do we have two fuse status
registers?
York
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support
2017-01-27 17:42 ` york sun
@ 2017-01-30 7:21 ` Priyanka Jain
2017-02-07 17:08 ` york sun
0 siblings, 1 reply; 10+ messages in thread
From: Priyanka Jain @ 2017-01-30 7:21 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: york sun
> Sent: Friday, January 27, 2017 11:13 PM
> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot at lists.denx.de
> Cc: Arpit Goel <arpit.goel@nxp.com>
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>
> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> > VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
> > LS2088A, LS2080A differs from existing logic.
> > -VDD voltage array is different
> > -Registers are different
> > -VDD calculation logic is different
> >
> > Add new function adjust_vdd() for LSCH3 compliant SoCs
> >
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
> > ---
> > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
> > board/freescale/common/vid.c | 174 ++++++++++++++++++--
> > 2 files changed, 164 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > index 38a6d03..fc4d33b 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> > @@ -187,9 +187,9 @@ struct ccsr_gur {
> > u32 gpporcr3;
> > u32 gpporcr4;
> > u8 res_030[0x60-0x30];
> > -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
> > +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
> > #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
> > -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
> > +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
> > #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
>
>
> Priyanka,
>
> You changed the fuse register offset and fuse position in this and previous patch
> of this set. What's going on? I presume you have verified it on LS2080ARDB.
> How did it work before? Do we have two fuse status registers?
>
> York
York,
These code changes are valid for both LS2080A and LS2088A.
VID was not working before on LS2080A also.
Priyanka
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support
2017-01-30 7:21 ` Priyanka Jain
@ 2017-02-07 17:08 ` york sun
2017-02-08 5:08 ` Priyanka Jain
0 siblings, 1 reply; 10+ messages in thread
From: york sun @ 2017-02-07 17:08 UTC (permalink / raw)
To: u-boot
On 01/29/2017 11:21 PM, Priyanka Jain wrote:
>
>
>> -----Original Message-----
>> From: york sun
>> Sent: Friday, January 27, 2017 11:13 PM
>> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot at lists.denx.de
>> Cc: Arpit Goel <arpit.goel@nxp.com>
>> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>>
>> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
>>> VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
>>> LS2088A, LS2080A differs from existing logic.
>>> -VDD voltage array is different
>>> -Registers are different
>>> -VDD calculation logic is different
>>>
>>> Add new function adjust_vdd() for LSCH3 compliant SoCs
>>>
>>> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
>>> Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
>>> ---
>>> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
>>> board/freescale/common/vid.c | 174 ++++++++++++++++++--
>>> 2 files changed, 164 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> index 38a6d03..fc4d33b 100644
>>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
>>> @@ -187,9 +187,9 @@ struct ccsr_gur {
>>> u32 gpporcr3;
>>> u32 gpporcr4;
>>> u8 res_030[0x60-0x30];
>>> -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
>>> +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
>>> #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
>>> -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
>>> +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
>>> #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
>>
>>
>> Priyanka,
>>
>> You changed the fuse register offset and fuse position in this and previous patch
>> of this set. What's going on? I presume you have verified it on LS2080ARDB.
>> How did it work before? Do we have two fuse status registers?
>>
>> York
>
> York,
>
> These code changes are valid for both LS2080A and LS2088A.
> VID was not working before on LS2080A also.
>
I have to ask, does VID work now with this change set? Have you verified
on both RDB and QDS? How about other SoCs in LSCH3 family?
York
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support
2017-02-07 17:08 ` york sun
@ 2017-02-08 5:08 ` Priyanka Jain
2017-02-08 16:56 ` york sun
0 siblings, 1 reply; 10+ messages in thread
From: Priyanka Jain @ 2017-02-08 5:08 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: york sun
> Sent: Tuesday, February 07, 2017 10:38 PM
> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot at lists.denx.de
> Cc: Arpit Goel <arpit.goel@nxp.com>
> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
>
> On 01/29/2017 11:21 PM, Priyanka Jain wrote:
> >
> >
> >> -----Original Message-----
> >> From: york sun
> >> Sent: Friday, January 27, 2017 11:13 PM
> >> To: Priyanka Jain <priyanka.jain@nxp.com>; u-boot at lists.denx.de
> >> Cc: Arpit Goel <arpit.goel@nxp.com>
> >> Subject: Re: [PATCH 2/3] armv8: fsl-lsch3: Update VID support
> >>
> >> On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> >>> VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like
> >>> LS2088A, LS2080A differs from existing logic.
> >>> -VDD voltage array is different
> >>> -Registers are different
> >>> -VDD calculation logic is different
> >>>
> >>> Add new function adjust_vdd() for LSCH3 compliant SoCs
> >>>
> >>> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> >>> Signed-off-by: Arpit Goel <arpit.goel@nxp.com>
> >>> ---
> >>> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 4 +-
> >>> board/freescale/common/vid.c | 174 ++++++++++++++++++--
> >>> 2 files changed, 164 insertions(+), 14 deletions(-)
> >>>
> >>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> index 38a6d03..fc4d33b 100644
> >>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
> >>> @@ -187,9 +187,9 @@ struct ccsr_gur {
> >>> u32 gpporcr3;
> >>> u32 gpporcr4;
> >>> u8 res_030[0x60-0x30];
> >>> -#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
> >>> +#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
> >>> #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
> >>> -#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
> >>> +#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
> >>> #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
> >>
> >>
> >> Priyanka,
> >>
> >> You changed the fuse register offset and fuse position in this and
> >> previous patch of this set. What's going on? I presume you have verified it on
> LS2080ARDB.
> >> How did it work before? Do we have two fuse status registers?
> >>
> >> York
> >
> > York,
> >
> > These code changes are valid for both LS2080A and LS2088A.
> > VID was not working before on LS2080A also.
> >
>
> I have to ask, does VID work now with this change set? Have you verified on
> both RDB and QDS? How about other SoCs in LSCH3 family?
>
> York
We have verified VID support on LS2080AQDS, LS2080ARDB, LS2088AQDS, LS2080ARDB (all SoCs in upstream for which LSCH3 flag is applicable)
Priyanka
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support
2017-02-08 5:08 ` Priyanka Jain
@ 2017-02-08 16:56 ` york sun
0 siblings, 0 replies; 10+ messages in thread
From: york sun @ 2017-02-08 16:56 UTC (permalink / raw)
To: u-boot
On 02/07/2017 09:08 PM, Priyanka Jain wrote:
>
<snip>
>
> We have verified VID support on LS2080AQDS, LS2080ARDB, LS2088AQDS, LS2080ARDB (all SoCs in upstream for which LSCH3 flag is applicable)
>
>
Great! Thanks.
York
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support
2017-01-19 5:42 [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support Priyanka Jain
` (2 preceding siblings ...)
2017-01-19 5:42 ` [U-Boot] [PATCH 3/3] armv8: fsl-layerscape: Add vid support for LS2080AQDS Priyanka Jain
@ 2017-03-09 21:29 ` york sun
3 siblings, 0 replies; 10+ messages in thread
From: york sun @ 2017-03-09 21:29 UTC (permalink / raw)
To: u-boot
On 01/18/2017 09:43 PM, Priyanka Jain wrote:
> Priyanka Jain (3):
> armv8: fsl-layerscape: Updates DCFG register map.
> armv8: fsl-lsch3: Update VID support
> armv8: fsl-layerscape: Add vid support for LS2080AQDS.
>
> .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 69 ++++++---
> board/freescale/common/vid.c | 174 ++++++++++++++++++--
> board/freescale/ls2080aqds/ls2080aqds.c | 9 +
> 3 files changed, 219 insertions(+), 33 deletions(-)
>
Applied to u-boot-fsl-qoriq master, awaiting upstream.
York
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-03-09 21:29 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-19 5:42 [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 1/3] armv8: fsl-layerscape: Updates DCFG register map Priyanka Jain
2017-01-19 5:42 ` [U-Boot] [PATCH 2/3] armv8: fsl-lsch3: Update VID support Priyanka Jain
2017-01-27 17:42 ` york sun
2017-01-30 7:21 ` Priyanka Jain
2017-02-07 17:08 ` york sun
2017-02-08 5:08 ` Priyanka Jain
2017-02-08 16:56 ` york sun
2017-01-19 5:42 ` [U-Boot] [PATCH 3/3] armv8: fsl-layerscape: Add vid support for LS2080AQDS Priyanka Jain
2017-03-09 21:29 ` [U-Boot] [PATCH 0/3] armv8: fsl-layerscape: Update vid support york sun
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