DPAA: Software Portal selection for network interface

* DPAA: Software Portal selection for network interface
@ 2017-06-22 12:42 Sebastian Huber
  2017-06-22 14:48 ` Madalin-cristian Bucur
  0 siblings, 1 reply; 3+ messages in thread
From: Sebastian Huber @ 2017-06-22 12:42 UTC (permalink / raw)
  To: linuxppc-dev; +Cc: Madalin Bucur

Hello,

as far as I understand the software portal selection for a network=20
interface is done in

static int dpaa_eth_probe(struct platform_device *pdev)
{
     [...]
     channel =3D dpaa_get_channel();
     if (channel < 0) {
         dev_err(dev, "dpaa_get_channel() failed\n");
         err =3D channel;
         goto get_channel_failed;
     }

     priv->channel =3D (u16)channel;

     /* Start a thread that will walk the CPUs with affine portals
      * and add this pool channel to each's dequeue mask.
      */
     dpaa_eth_add_channel(priv->channel);

with

static int dpaa_get_channel(void)
{
     spin_lock(&rx_pool_channel_init);
     if (!rx_pool_channel) {
         u32 pool;
         int ret;

         ret =3D qman_alloc_pool(&pool);

         if (!ret)
             rx_pool_channel =3D pool;
     }
     spin_unlock(&rx_pool_channel_init);
     if (!rx_pool_channel)
         return -ENOMEM;
     return rx_pool_channel;
}

which always returns the same pool channel (e.g. 0x401) if successful.

This means all the QMan portal_isr() are distributed round-robin to all=20
affine portals. Is there some way to configure the software portal for a=20
specific network interface, e.g. use processors 0, 1, 2, 3 for one=20
interface,and 4, 5, 6, 7 for another?

--=20
Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber@embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine gesch=C3=A4ftliche Mitteilung im Sinne des EHUG=
.

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