[PATCH v4 0/2] add qixis driver

[PATCH v4 0/2] add qixis driver

[Pankaj Bansal]

FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis driver which is basically an i2c client driver to control FPGA.

Also added platform driver for MMIO based FPGA, like the one available on LS2088ARDB/LS2088AQDS.

This driver is essential to control MDIO mux multiplexing.

This driver is dependent on below patches:
https://www.mail-archive.com/netdev@vger.kernel.org/msg281274.html

Cc: Varun Sethi <V.Sethi@nxp.com>

---
Notes:
	V3:
	- https://patchwork.kernel.org/cover/10795195/
	V2:
	- https://patchwork.kernel.org/cover/10788341/
	V1:
	- https://patchwork.kernel.org/cover/10627297/

Pankaj Bansal (2):
  dt-bindings: soc: fsl: Document Qixis FPGA usage
  drivers: soc: fsl: add qixis driver

 .../bindings/soc/fsl/qixis_ctrl.txt           |  53 +++++
 drivers/soc/fsl/Kconfig                       |  11 +
 drivers/soc/fsl/Makefile                      |   1 +
 drivers/soc/fsl/qixis_ctrl.c                  | 222 ++++++++++++++++++
 4 files changed, 287 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
 create mode 100644 drivers/soc/fsl/qixis_ctrl.c

-- 
2.17.1

[PATCH v4 0/2] add qixis driver

[Pankaj Bansal]

FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis driver which is basically an i2c client driver to control FPGA.

Also added platform driver for MMIO based FPGA, like the one available on LS2088ARDB/LS2088AQDS.

This driver is essential to control MDIO mux multiplexing.

This driver is dependent on below patches:
https://www.mail-archive.com/netdev@vger.kernel.org/msg281274.html

Cc: Varun Sethi <V.Sethi@nxp.com>

---
Notes:
	V3:
	- https://patchwork.kernel.org/cover/10795195/
	V2:
	- https://patchwork.kernel.org/cover/10788341/
	V1:
	- https://patchwork.kernel.org/cover/10627297/

Pankaj Bansal (2):
  dt-bindings: soc: fsl: Document Qixis FPGA usage
  drivers: soc: fsl: add qixis driver

 .../bindings/soc/fsl/qixis_ctrl.txt           |  53 +++++
 drivers/soc/fsl/Kconfig                       |  11 +
 drivers/soc/fsl/Makefile                      |   1 +
 drivers/soc/fsl/qixis_ctrl.c                  | 222 ++++++++++++++++++
 4 files changed, 287 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
 create mode 100644 drivers/soc/fsl/qixis_ctrl.c

-- 
2.17.1

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[PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage

[Pankaj Bansal]

an FPGA-based system controller, called “Qixis”, which
manages several critical system features, including:
• Reset sequencing
• Power supply configuration
• Board configuration
• hardware configuration

The qixis registers are accessible over one or more system-specific
interfaces, typically I2C, JTAG or an embedded processor.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---

Notes:
    V4:
    - No Change
    V3:
    - Added boardname based compatible field in bindings
    - Added bindings for MMIO based FPGA
    V2:
    - No change

 .../bindings/soc/fsl/qixis_ctrl.txt          | 53 ++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
new file mode 100644
index 000000000000..5d510df14be8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
@@ -0,0 +1,53 @@
+* QIXIS FPGA block
+
+an FPGA-based system controller, called “Qixis”, which
+manages several critical system features, including:
+• Configuration switch monitoring
+• Power on/off sequencing
+• Reset sequencing
+• Power supply configuration
+• Board configuration
+• hardware configuration
+• Background power data collection (DCM)
+• Fault monitoring
+• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
+• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)
+• I2C master for remote board control even with no DUT available
+
+The qixis registers are accessible over one or more system-specific interfaces,
+typically I2C, JTAG or an embedded processor.
+
+FPGA connected to I2C:
+Required properties:
+
+ - compatible: should be a board-specific string followed by a string
+   indicating the type of FPGA.  Example:
+	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
+ - reg : i2c address of the qixis device.
+
+Example (LX2160A-QDS):
+	/* The FPGA node */
+        fpga@66 {
+		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
+		reg = <0x66>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	}
+
+* Freescale on-board FPGA
+
+This is the memory-mapped registers for on board FPGA.
+
+Required properties:
+- compatible: should be a board-specific string followed by a string
+  indicating the type of FPGA.  Example:
+	"fsl,<board>-fpga", "fsl,fpga-qixis"
+- reg: should contain the address and the length of the FPGA register set.
+
+Example (LS2080A-RDB):
+
+        cpld@3,0 {
+                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
+                reg = <0x3 0 0x10000>;
+        };
+
-- 
2.17.1

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[PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage

[Pankaj Bansal]

an FPGA-based system controller, called “Qixis”, which
manages several critical system features, including:
• Reset sequencing
• Power supply configuration
• Board configuration
• hardware configuration

The qixis registers are accessible over one or more system-specific
interfaces, typically I2C, JTAG or an embedded processor.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---

Notes:
    V4:
    - No Change
    V3:
    - Added boardname based compatible field in bindings
    - Added bindings for MMIO based FPGA
    V2:
    - No change

 .../bindings/soc/fsl/qixis_ctrl.txt          | 53 ++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
new file mode 100644
index 000000000000..5d510df14be8
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
@@ -0,0 +1,53 @@
+* QIXIS FPGA block
+
+an FPGA-based system controller, called “Qixis”, which
+manages several critical system features, including:
+• Configuration switch monitoring
+• Power on/off sequencing
+• Reset sequencing
+• Power supply configuration
+• Board configuration
+• hardware configuration
+• Background power data collection (DCM)
+• Fault monitoring
+• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
+• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)
+• I2C master for remote board control even with no DUT available
+
+The qixis registers are accessible over one or more system-specific interfaces,
+typically I2C, JTAG or an embedded processor.
+
+FPGA connected to I2C:
+Required properties:
+
+ - compatible: should be a board-specific string followed by a string
+   indicating the type of FPGA.  Example:
+	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
+ - reg : i2c address of the qixis device.
+
+Example (LX2160A-QDS):
+	/* The FPGA node */
+        fpga@66 {
+		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
+		reg = <0x66>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	}
+
+* Freescale on-board FPGA
+
+This is the memory-mapped registers for on board FPGA.
+
+Required properties:
+- compatible: should be a board-specific string followed by a string
+  indicating the type of FPGA.  Example:
+	"fsl,<board>-fpga", "fsl,fpga-qixis"
+- reg: should contain the address and the length of the FPGA register set.
+
+Example (LS2080A-RDB):
+
+        cpld@3,0 {
+                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
+                reg = <0x3 0 0x10000>;
+        };
+
-- 
2.17.1

RE: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage

[Leo Li]

> -----Original Message-----
> From: Pankaj Bansal
> Sent: Tuesday, February 5, 2019 4:15 AM
> To: Leo Li <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Mark
> Rutland <mark.rutland@arm.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> open list : OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> <devicetree@vger.kernel.org>; Pankaj Bansal <pankaj.bansal@nxp.com>
> Subject: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage
> 
> an FPGA-based system controller, called “Qixis”, which
> manages several critical system features, including:
> • Reset sequencing
> • Power supply configuration
> • Board configuration
> • hardware configuration
> 
> The qixis registers are accessible over one or more system-specific
> interfaces, typically I2C, JTAG or an embedded processor.

In theory the on-board FPGA is not part of the SoC.  The Qixis device has been defined previously in Documentation/devicetree/bindings/board/fsl-board.txt file.  Although normally board bindings are defined in architecture specific binding folders, this is a good place for board related stuff used across multiple architectures.  You can update the existing binding if needed.

> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> 
> Notes:
>     V4:
>     - No Change
>     V3:
>     - Added boardname based compatible field in bindings
>     - Added bindings for MMIO based FPGA
>     V2:
>     - No change
> 
>  .../bindings/soc/fsl/qixis_ctrl.txt          | 53 ++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> new file mode 100644
> index 000000000000..5d510df14be8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> @@ -0,0 +1,53 @@
> +* QIXIS FPGA block
> +
> +an FPGA-based system controller, called “Qixis”, which
> +manages several critical system features, including:
> +• Configuration switch monitoring
> +• Power on/off sequencing
> +• Reset sequencing
> +• Power supply configuration
> +• Board configuration
> +• hardware configuration
> +• Background power data collection (DCM)
> +• Fault monitoring
> +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
> +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so
> on)
> +• I2C master for remote board control even with no DUT available
> +
> +The qixis registers are accessible over one or more system-specific
> interfaces,
> +typically I2C, JTAG or an embedded processor.
> +
> +FPGA connected to I2C:
> +Required properties:
> +
> + - compatible: should be a board-specific string followed by a string
> +   indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
> + - reg : i2c address of the qixis device.
> +
> +Example (LX2160A-QDS):
> +	/* The FPGA node */
> +        fpga@66 {
> +		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
> +		reg = <0x66>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +	}
> +
> +* Freescale on-board FPGA
> +
> +This is the memory-mapped registers for on board FPGA.
> +
> +Required properties:
> +- compatible: should be a board-specific string followed by a string
> +  indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis"
> +- reg: should contain the address and the length of the FPGA register set.
> +
> +Example (LS2080A-RDB):
> +
> +        cpld@3,0 {
> +                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
> +                reg = <0x3 0 0x10000>;
> +        };
> +
> --
> 2.17.1

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RE: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage

[Leo Li]

> -----Original Message-----
> From: Pankaj Bansal
> Sent: Tuesday, February 5, 2019 4:15 AM
> To: Leo Li <leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; Mark
> Rutland <mark.rutland@arm.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> open list : OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> <devicetree@vger.kernel.org>; Pankaj Bansal <pankaj.bansal@nxp.com>
> Subject: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage
> 
> an FPGA-based system controller, called “Qixis”, which
> manages several critical system features, including:
> • Reset sequencing
> • Power supply configuration
> • Board configuration
> • hardware configuration
> 
> The qixis registers are accessible over one or more system-specific
> interfaces, typically I2C, JTAG or an embedded processor.

In theory the on-board FPGA is not part of the SoC.  The Qixis device has been defined previously in Documentation/devicetree/bindings/board/fsl-board.txt file.  Although normally board bindings are defined in architecture specific binding folders, this is a good place for board related stuff used across multiple architectures.  You can update the existing binding if needed.

> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> 
> Notes:
>     V4:
>     - No Change
>     V3:
>     - Added boardname based compatible field in bindings
>     - Added bindings for MMIO based FPGA
>     V2:
>     - No change
> 
>  .../bindings/soc/fsl/qixis_ctrl.txt          | 53 ++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> new file mode 100644
> index 000000000000..5d510df14be8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> @@ -0,0 +1,53 @@
> +* QIXIS FPGA block
> +
> +an FPGA-based system controller, called “Qixis”, which
> +manages several critical system features, including:
> +• Configuration switch monitoring
> +• Power on/off sequencing
> +• Reset sequencing
> +• Power supply configuration
> +• Board configuration
> +• hardware configuration
> +• Background power data collection (DCM)
> +• Fault monitoring
> +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
> +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so
> on)
> +• I2C master for remote board control even with no DUT available
> +
> +The qixis registers are accessible over one or more system-specific
> interfaces,
> +typically I2C, JTAG or an embedded processor.
> +
> +FPGA connected to I2C:
> +Required properties:
> +
> + - compatible: should be a board-specific string followed by a string
> +   indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"
> + - reg : i2c address of the qixis device.
> +
> +Example (LX2160A-QDS):
> +	/* The FPGA node */
> +        fpga@66 {
> +		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
> +		reg = <0x66>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +	}
> +
> +* Freescale on-board FPGA
> +
> +This is the memory-mapped registers for on board FPGA.
> +
> +Required properties:
> +- compatible: should be a board-specific string followed by a string
> +  indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis"
> +- reg: should contain the address and the length of the FPGA register set.
> +
> +Example (LS2080A-RDB):
> +
> +        cpld@3,0 {
> +                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
> +                reg = <0x3 0 0x10000>;
> +        };
> +
> --
> 2.17.1

Re: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage

[Rob Herring]

On Tue, Feb 05, 2019 at 10:14:40AM +0000, Pankaj Bansal wrote:
> an FPGA-based system controller, called “Qixis”, which
> manages several critical system features, including:
> • Reset sequencing
> • Power supply configuration
> • Board configuration
> • hardware configuration
> 
> The qixis registers are accessible over one or more system-specific
> interfaces, typically I2C, JTAG or an embedded processor.
> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> 
> Notes:
>     V4:
>     - No Change
>     V3:
>     - Added boardname based compatible field in bindings
>     - Added bindings for MMIO based FPGA
>     V2:
>     - No change
> 
>  .../bindings/soc/fsl/qixis_ctrl.txt          | 53 ++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> new file mode 100644
> index 000000000000..5d510df14be8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> @@ -0,0 +1,53 @@
> +* QIXIS FPGA block
> +
> +an FPGA-based system controller, called “Qixis”, which
> +manages several critical system features, including:
> +• Configuration switch monitoring
> +• Power on/off sequencing
> +• Reset sequencing
> +• Power supply configuration
> +• Board configuration
> +• hardware configuration
> +• Background power data collection (DCM)
> +• Fault monitoring
> +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
> +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)
> +• I2C master for remote board control even with no DUT available
> +
> +The qixis registers are accessible over one or more system-specific interfaces,
> +typically I2C, JTAG or an embedded processor.
> +
> +FPGA connected to I2C:
> +Required properties:
> +
> + - compatible: should be a board-specific string followed by a string
> +   indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"

You don't really need the '-i2c' part because it will only get bound to 
an i2c based driver when a child of an i2c controller.

> + - reg : i2c address of the qixis device.
> +
> +Example (LX2160A-QDS):
> +	/* The FPGA node */
> +        fpga@66 {
> +		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
> +		reg = <0x66>;

> +		#address-cells = <1>;
> +		#size-cells = <0>;

You don't need this unless you have child nodes with 'reg'.

> +	}
> +
> +* Freescale on-board FPGA
> +
> +This is the memory-mapped registers for on board FPGA.
> +
> +Required properties:
> +- compatible: should be a board-specific string followed by a string
> +  indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis"
> +- reg: should contain the address and the length of the FPGA register set.
> +
> +Example (LS2080A-RDB):
> +
> +        cpld@3,0 {
> +                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
> +                reg = <0x3 0 0x10000>;
> +        };
> +
> -- 
> 2.17.1
> 

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Re: [PATCH v4 1/2] dt-bindings: soc: fsl: Document Qixis FPGA usage

[Rob Herring]

On Tue, Feb 05, 2019 at 10:14:40AM +0000, Pankaj Bansal wrote:
> an FPGA-based system controller, called “Qixis”, which
> manages several critical system features, including:
> • Reset sequencing
> • Power supply configuration
> • Board configuration
> • hardware configuration
> 
> The qixis registers are accessible over one or more system-specific
> interfaces, typically I2C, JTAG or an embedded processor.
> 
> Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
> ---
> 
> Notes:
>     V4:
>     - No Change
>     V3:
>     - Added boardname based compatible field in bindings
>     - Added bindings for MMIO based FPGA
>     V2:
>     - No change
> 
>  .../bindings/soc/fsl/qixis_ctrl.txt          | 53 ++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> new file mode 100644
> index 000000000000..5d510df14be8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/qixis_ctrl.txt
> @@ -0,0 +1,53 @@
> +* QIXIS FPGA block
> +
> +an FPGA-based system controller, called “Qixis”, which
> +manages several critical system features, including:
> +• Configuration switch monitoring
> +• Power on/off sequencing
> +• Reset sequencing
> +• Power supply configuration
> +• Board configuration
> +• hardware configuration
> +• Background power data collection (DCM)
> +• Fault monitoring
> +• RCW bypass SRAM (replace flash RCW with internal RCW) (NOR only)
> +• Dedicated functional validation blocks (POSt/IRS, triggered event, and so on)
> +• I2C master for remote board control even with no DUT available
> +
> +The qixis registers are accessible over one or more system-specific interfaces,
> +typically I2C, JTAG or an embedded processor.
> +
> +FPGA connected to I2C:
> +Required properties:
> +
> + - compatible: should be a board-specific string followed by a string
> +   indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis-i2c"

You don't really need the '-i2c' part because it will only get bound to 
an i2c based driver when a child of an i2c controller.

> + - reg : i2c address of the qixis device.
> +
> +Example (LX2160A-QDS):
> +	/* The FPGA node */
> +        fpga@66 {
> +		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c";
> +		reg = <0x66>;

> +		#address-cells = <1>;
> +		#size-cells = <0>;

You don't need this unless you have child nodes with 'reg'.

> +	}
> +
> +* Freescale on-board FPGA
> +
> +This is the memory-mapped registers for on board FPGA.
> +
> +Required properties:
> +- compatible: should be a board-specific string followed by a string
> +  indicating the type of FPGA.  Example:
> +	"fsl,<board>-fpga", "fsl,fpga-qixis"
> +- reg: should contain the address and the length of the FPGA register set.
> +
> +Example (LS2080A-RDB):
> +
> +        cpld@3,0 {
> +                compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
> +                reg = <0x3 0 0x10000>;
> +        };
> +
> -- 
> 2.17.1
> 

[PATCH v4 2/2] drivers: soc: fsl: add qixis driver

[Pankaj Bansal]

FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis
driver which is basically an i2c client driver to control FPGA.

Also added platform driver for MMIO based FPGA, like the one available
on LS2088ARDB/LS2088AQDS.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---

Notes:
    V4:
    - Fix compilation error when qixis_ctrl is built as standalone module.
    V3:
    - Add MMIO based FPGA driver
    V2:
    - Modify the driver to not create platform devices corresponding to subnodes.
      because the subnodes are not actual devices.
    - Use mdio_mux_regmap_init/mdio_mux_regmap_uninit
    - Remove header file from include folder, as no qixis api is called from outside
    - Add regmap_exit in driver's remove function
    Dendencies:
    - https://www.mail-archive.com/netdev@vger.kernel.org/msg281274.html

 drivers/soc/fsl/Kconfig      |  11 ++
 drivers/soc/fsl/Makefile     |   1 +
 drivers/soc/fsl/qixis_ctrl.c | 222 +++++++++++++++++++++++++++++++++
 3 files changed, 234 insertions(+)

diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
index 8f80e8bbf29e..75993be04e42 100644
--- a/drivers/soc/fsl/Kconfig
+++ b/drivers/soc/fsl/Kconfig
@@ -28,4 +28,15 @@ config FSL_MC_DPIO
 	  other DPAA2 objects. This driver does not expose the DPIO
 	  objects individually, but groups them under a service layer
 	  API.
+
+config FSL_QIXIS
+	tristate "QIXIS system controller driver"
+	depends on OF
+	select REGMAP_I2C
+	select REGMAP_MMIO
+	default n
+	help
+	  Say y here to enable QIXIS system controller api. The qixis driver
+	  provides FPGA functions to control system.
+
 endmenu
diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 803ef1bfb5ff..47e0cfc66ca4 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,5 +5,6 @@
 obj-$(CONFIG_FSL_DPAA)                 += qbman/
 obj-$(CONFIG_QUICC_ENGINE)		+= qe/
 obj-$(CONFIG_CPM)			+= qe/
+obj-$(CONFIG_FSL_QIXIS) 		+= qixis_ctrl.o
 obj-$(CONFIG_FSL_GUTS)			+= guts.o
 obj-$(CONFIG_FSL_MC_DPIO) 		+= dpio/
diff --git a/drivers/soc/fsl/qixis_ctrl.c b/drivers/soc/fsl/qixis_ctrl.c
new file mode 100644
index 000000000000..a8108bfd5195
--- /dev/null
+++ b/drivers/soc/fsl/qixis_ctrl.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/* Freescale QIXIS system controller driver.
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2018-2019 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mdio-mux.h>
+
+/* QIXIS MAP */
+struct fsl_qixis_regs {
+	u8		id;		/* Identification Registers */
+	u8		version;	/* Version Register */
+	u8		qixis_ver;	/* QIXIS Version Register */
+	u8		reserved1[0x1f];
+};
+
+struct mdio_mux_data {
+	void			*data;
+	struct list_head	link;
+};
+
+struct qixis_priv {
+	struct regmap		*regmap;
+	struct list_head	mdio_mux_list;
+};
+
+static struct regmap_config qixis_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static int fsl_qixis_mdio_mux_init(struct device *dev, struct qixis_priv *priv)
+{
+	struct device_node *child;
+	struct mdio_mux_data *mux_data;
+	int ret;
+
+	INIT_LIST_HEAD(&priv->mdio_mux_list);
+	for_each_child_of_node(dev->of_node, child) {
+		if (!of_node_name_prefix(child, "mdio-mux"))
+			continue;
+
+		mux_data = devm_kzalloc(dev, sizeof(struct mdio_mux_data),
+					GFP_KERNEL);
+		if (!mux_data)
+			return -ENOMEM;
+		ret = mdio_mux_regmap_init(dev, child, &mux_data->data);
+		if (ret)
+			return ret;
+		list_add(&mux_data->link, &priv->mdio_mux_list);
+	}
+
+	return 0;
+}
+
+static int fsl_qixis_mdio_mux_uninit(struct qixis_priv *priv)
+{
+	struct list_head *pos;
+	struct mdio_mux_data *mux_data;
+
+	list_for_each(pos, &priv->mdio_mux_list) {
+		mux_data = list_entry(pos, struct mdio_mux_data, link);
+		mdio_mux_regmap_uninit(mux_data->data);
+	}
+
+	return 0;
+}
+
+static int fsl_qixis_probe(struct platform_device *pdev)
+{
+	static struct fsl_qixis_regs __iomem *qixis;
+	struct qixis_priv *priv;
+	int ret;
+	u32 qver;
+
+	qixis = of_iomap(pdev->dev.of_node, 0);
+	if (IS_ERR_OR_NULL(qixis)) {
+		pr_err("%s: Could not map qixis registers\n", __func__);
+		return -ENODEV;
+	}
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(struct qixis_priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = devm_regmap_init_mmio(&pdev->dev, qixis,
+					     &qixis_regmap_config);
+	regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
+		    &qver);
+	pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
+
+	ret = fsl_qixis_mdio_mux_init(&pdev->dev, priv);
+	if (ret)
+		goto error;
+
+	platform_set_drvdata(pdev, priv);
+
+	return 0;
+error:
+	regmap_exit(priv->regmap);
+
+	return ret;
+}
+
+static int fsl_qixis_remove(struct platform_device *pdev)
+{
+	struct qixis_priv *priv;
+
+	priv = platform_get_drvdata(pdev);
+	fsl_qixis_mdio_mux_uninit(priv);
+	regmap_exit(priv->regmap);
+
+	return 0;
+}
+
+static const struct of_device_id fsl_qixis_of_match[] = {
+	{ .compatible = "fsl,fpga-qixis", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, fsl_qixis_of_match);
+
+static struct platform_driver fsl_qixis_driver = {
+	.driver = {
+		.name = "qixis_ctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(fsl_qixis_of_match),
+	},
+	.probe = fsl_qixis_probe,
+	.remove = fsl_qixis_remove,
+};
+
+static int fsl_qixis_i2c_probe(struct i2c_client *client)
+{
+	struct qixis_priv *priv;
+	int ret;
+	u32 qver;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EOPNOTSUPP;
+
+	priv = devm_kzalloc(&client->dev, sizeof(struct qixis_priv),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = regmap_init_i2c(client, &qixis_regmap_config);
+	regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
+		    &qver);
+	pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
+
+	ret = fsl_qixis_mdio_mux_init(&client->dev, priv);
+	if (ret)
+		goto error;
+
+	i2c_set_clientdata(client, priv);
+
+	return 0;
+error:
+	regmap_exit(priv->regmap);
+
+	return ret;
+}
+
+static int fsl_qixis_i2c_remove(struct i2c_client *client)
+{
+	struct qixis_priv *priv;
+
+	priv = i2c_get_clientdata(client);
+	fsl_qixis_mdio_mux_uninit(priv);
+	regmap_exit(priv->regmap);
+
+	return 0;
+}
+
+static const struct of_device_id fsl_qixis_i2c_of_match[] = {
+	{ .compatible = "fsl,fpga-qixis-i2c" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, fsl_qixis_i2c_of_match);
+
+static struct i2c_driver fsl_qixis_i2c_driver = {
+	.driver = {
+		.name	= "qixis_ctrl_i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(fsl_qixis_i2c_of_match),
+	},
+	.probe_new	= fsl_qixis_i2c_probe,
+	.remove		= fsl_qixis_i2c_remove,
+};
+
+static int __init fsl_qixis_init(void)
+{
+	pr_info("FSL: Qixis Control driver\n");
+
+	if (platform_driver_register(&fsl_qixis_driver))
+		pr_warn("could not register Qixis Control platform driver\n");
+	return i2c_add_driver(&fsl_qixis_i2c_driver);
+}
+module_init(fsl_qixis_init);
+
+static void __exit fsl_qixis_exit(void)
+{
+	platform_driver_unregister(&fsl_qixis_driver);
+	i2c_del_driver(&fsl_qixis_i2c_driver);
+}
+module_exit(fsl_qixis_exit);
+
+MODULE_AUTHOR("Wang Dongsheng <dongsheng.wang@freescale.com>");
+MODULE_DESCRIPTION("Freescale QIXIS system controller driver");
+MODULE_LICENSE("GPL");
+
-- 
2.17.1

[PATCH v4 2/2] drivers: soc: fsl: add qixis driver

[Pankaj Bansal]

FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis
driver which is basically an i2c client driver to control FPGA.

Also added platform driver for MMIO based FPGA, like the one available
on LS2088ARDB/LS2088AQDS.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
---

Notes:
    V4:
    - Fix compilation error when qixis_ctrl is built as standalone module.
    V3:
    - Add MMIO based FPGA driver
    V2:
    - Modify the driver to not create platform devices corresponding to subnodes.
      because the subnodes are not actual devices.
    - Use mdio_mux_regmap_init/mdio_mux_regmap_uninit
    - Remove header file from include folder, as no qixis api is called from outside
    - Add regmap_exit in driver's remove function
    Dendencies:
    - https://www.mail-archive.com/netdev@vger.kernel.org/msg281274.html

 drivers/soc/fsl/Kconfig      |  11 ++
 drivers/soc/fsl/Makefile     |   1 +
 drivers/soc/fsl/qixis_ctrl.c | 222 +++++++++++++++++++++++++++++++++
 3 files changed, 234 insertions(+)

diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
index 8f80e8bbf29e..75993be04e42 100644
--- a/drivers/soc/fsl/Kconfig
+++ b/drivers/soc/fsl/Kconfig
@@ -28,4 +28,15 @@ config FSL_MC_DPIO
 	  other DPAA2 objects. This driver does not expose the DPIO
 	  objects individually, but groups them under a service layer
 	  API.
+
+config FSL_QIXIS
+	tristate "QIXIS system controller driver"
+	depends on OF
+	select REGMAP_I2C
+	select REGMAP_MMIO
+	default n
+	help
+	  Say y here to enable QIXIS system controller api. The qixis driver
+	  provides FPGA functions to control system.
+
 endmenu
diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 803ef1bfb5ff..47e0cfc66ca4 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,5 +5,6 @@
 obj-$(CONFIG_FSL_DPAA)                 += qbman/
 obj-$(CONFIG_QUICC_ENGINE)		+= qe/
 obj-$(CONFIG_CPM)			+= qe/
+obj-$(CONFIG_FSL_QIXIS) 		+= qixis_ctrl.o
 obj-$(CONFIG_FSL_GUTS)			+= guts.o
 obj-$(CONFIG_FSL_MC_DPIO) 		+= dpio/
diff --git a/drivers/soc/fsl/qixis_ctrl.c b/drivers/soc/fsl/qixis_ctrl.c
new file mode 100644
index 000000000000..a8108bfd5195
--- /dev/null
+++ b/drivers/soc/fsl/qixis_ctrl.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/* Freescale QIXIS system controller driver.
+ *
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2018-2019 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/mdio-mux.h>
+
+/* QIXIS MAP */
+struct fsl_qixis_regs {
+	u8		id;		/* Identification Registers */
+	u8		version;	/* Version Register */
+	u8		qixis_ver;	/* QIXIS Version Register */
+	u8		reserved1[0x1f];
+};
+
+struct mdio_mux_data {
+	void			*data;
+	struct list_head	link;
+};
+
+struct qixis_priv {
+	struct regmap		*regmap;
+	struct list_head	mdio_mux_list;
+};
+
+static struct regmap_config qixis_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static int fsl_qixis_mdio_mux_init(struct device *dev, struct qixis_priv *priv)
+{
+	struct device_node *child;
+	struct mdio_mux_data *mux_data;
+	int ret;
+
+	INIT_LIST_HEAD(&priv->mdio_mux_list);
+	for_each_child_of_node(dev->of_node, child) {
+		if (!of_node_name_prefix(child, "mdio-mux"))
+			continue;
+
+		mux_data = devm_kzalloc(dev, sizeof(struct mdio_mux_data),
+					GFP_KERNEL);
+		if (!mux_data)
+			return -ENOMEM;
+		ret = mdio_mux_regmap_init(dev, child, &mux_data->data);
+		if (ret)
+			return ret;
+		list_add(&mux_data->link, &priv->mdio_mux_list);
+	}
+
+	return 0;
+}
+
+static int fsl_qixis_mdio_mux_uninit(struct qixis_priv *priv)
+{
+	struct list_head *pos;
+	struct mdio_mux_data *mux_data;
+
+	list_for_each(pos, &priv->mdio_mux_list) {
+		mux_data = list_entry(pos, struct mdio_mux_data, link);
+		mdio_mux_regmap_uninit(mux_data->data);
+	}
+
+	return 0;
+}
+
+static int fsl_qixis_probe(struct platform_device *pdev)
+{
+	static struct fsl_qixis_regs __iomem *qixis;
+	struct qixis_priv *priv;
+	int ret;
+	u32 qver;
+
+	qixis = of_iomap(pdev->dev.of_node, 0);
+	if (IS_ERR_OR_NULL(qixis)) {
+		pr_err("%s: Could not map qixis registers\n", __func__);
+		return -ENODEV;
+	}
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(struct qixis_priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = devm_regmap_init_mmio(&pdev->dev, qixis,
+					     &qixis_regmap_config);
+	regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
+		    &qver);
+	pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
+
+	ret = fsl_qixis_mdio_mux_init(&pdev->dev, priv);
+	if (ret)
+		goto error;
+
+	platform_set_drvdata(pdev, priv);
+
+	return 0;
+error:
+	regmap_exit(priv->regmap);
+
+	return ret;
+}
+
+static int fsl_qixis_remove(struct platform_device *pdev)
+{
+	struct qixis_priv *priv;
+
+	priv = platform_get_drvdata(pdev);
+	fsl_qixis_mdio_mux_uninit(priv);
+	regmap_exit(priv->regmap);
+
+	return 0;
+}
+
+static const struct of_device_id fsl_qixis_of_match[] = {
+	{ .compatible = "fsl,fpga-qixis", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, fsl_qixis_of_match);
+
+static struct platform_driver fsl_qixis_driver = {
+	.driver = {
+		.name = "qixis_ctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = of_match_ptr(fsl_qixis_of_match),
+	},
+	.probe = fsl_qixis_probe,
+	.remove = fsl_qixis_remove,
+};
+
+static int fsl_qixis_i2c_probe(struct i2c_client *client)
+{
+	struct qixis_priv *priv;
+	int ret;
+	u32 qver;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EOPNOTSUPP;
+
+	priv = devm_kzalloc(&client->dev, sizeof(struct qixis_priv),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->regmap = regmap_init_i2c(client, &qixis_regmap_config);
+	regmap_read(priv->regmap, offsetof(struct fsl_qixis_regs, qixis_ver),
+		    &qver);
+	pr_info("Freescale QIXIS Version: 0x%08x\n", qver);
+
+	ret = fsl_qixis_mdio_mux_init(&client->dev, priv);
+	if (ret)
+		goto error;
+
+	i2c_set_clientdata(client, priv);
+
+	return 0;
+error:
+	regmap_exit(priv->regmap);
+
+	return ret;
+}
+
+static int fsl_qixis_i2c_remove(struct i2c_client *client)
+{
+	struct qixis_priv *priv;
+
+	priv = i2c_get_clientdata(client);
+	fsl_qixis_mdio_mux_uninit(priv);
+	regmap_exit(priv->regmap);
+
+	return 0;
+}
+
+static const struct of_device_id fsl_qixis_i2c_of_match[] = {
+	{ .compatible = "fsl,fpga-qixis-i2c" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, fsl_qixis_i2c_of_match);
+
+static struct i2c_driver fsl_qixis_i2c_driver = {
+	.driver = {
+		.name	= "qixis_ctrl_i2c",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(fsl_qixis_i2c_of_match),
+	},
+	.probe_new	= fsl_qixis_i2c_probe,
+	.remove		= fsl_qixis_i2c_remove,
+};
+
+static int __init fsl_qixis_init(void)
+{
+	pr_info("FSL: Qixis Control driver\n");
+
+	if (platform_driver_register(&fsl_qixis_driver))
+		pr_warn("could not register Qixis Control platform driver\n");
+	return i2c_add_driver(&fsl_qixis_i2c_driver);
+}
+module_init(fsl_qixis_init);
+
+static void __exit fsl_qixis_exit(void)
+{
+	platform_driver_unregister(&fsl_qixis_driver);
+	i2c_del_driver(&fsl_qixis_i2c_driver);
+}
+module_exit(fsl_qixis_exit);
+
+MODULE_AUTHOR("Wang Dongsheng <dongsheng.wang@freescale.com>");
+MODULE_DESCRIPTION("Freescale QIXIS system controller driver");
+MODULE_LICENSE("GPL");
+
-- 
2.17.1


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