* [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt
@ 2020-08-19 1:59 Fabio Estevam
2020-08-19 2:34 ` [EXT] " Andy Duan
2020-08-23 2:15 ` Shawn Guo
0 siblings, 2 replies; 3+ messages in thread
From: Fabio Estevam @ 2020-08-19 1:59 UTC (permalink / raw)
To: shawnguo; +Cc: linux-arm-kernel, Fabio Estevam, fugang.duan, linux-imx, kernel
The i.MX8M SoCs have a fourth ENET interrupt dedicated to PPS (Pulse Per
Second). Add support for it.
Suggested-by: Rogerio Nunes <rogerio.nunes@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 ++-
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 76f040e4be5e..b83f400def8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -854,7 +854,8 @@
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET1_ROOT>,
<&clk IMX8MM_CLK_ENET_TIMER>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 9385dd7d1a2f..746faf1cf2fb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -741,7 +741,8 @@
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
<&clk IMX8MN_CLK_ENET1_ROOT>,
<&clk IMX8MN_CLK_ENET_TIMER>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9de2aa1c573c..cad2dd790bec 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -713,7 +713,8 @@
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
<&clk IMX8MP_CLK_SIM_ENET_ROOT>,
<&clk IMX8MP_CLK_ENET_TIMER>,
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index f70435cf9ad5..0d02ccdb0abc 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1031,7 +1031,8 @@
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
<&clk IMX8MQ_CLK_ENET1_ROOT>,
<&clk IMX8MQ_CLK_ENET_TIMER>,
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* RE: [EXT] [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt
2020-08-19 1:59 [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt Fabio Estevam
@ 2020-08-19 2:34 ` Andy Duan
2020-08-23 2:15 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Andy Duan @ 2020-08-19 2:34 UTC (permalink / raw)
To: Fabio Estevam, shawnguo; +Cc: linux-arm-kernel, dl-linux-imx, kernel
From: Fabio Estevam <festevam@gmail.com> Sent: Wednesday, August 19, 2020 10:00 AM
> The i.MX8M SoCs have a fourth ENET interrupt dedicated to PPS (Pulse Per
> Second). Add support for it.
>
> Suggested-by: Rogerio Nunes <rogerio.nunes@nxp.com>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 3 ++-
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 3 ++-
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 3 ++-
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 ++-
> 4 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 76f040e4be5e..b83f400def8b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -854,7 +854,8 @@
> reg = <0x30be0000 0x10000>;
> interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk
> IMX8MM_CLK_ENET1_ROOT>,
> <&clk
> IMX8MM_CLK_ENET1_ROOT>,
> <&clk
> IMX8MM_CLK_ENET_TIMER>, diff --git
> a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9385dd7d1a2f..746faf1cf2fb 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -741,7 +741,8 @@
> reg = <0x30be0000 0x10000>;
> interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk
> IMX8MN_CLK_ENET1_ROOT>,
> <&clk
> IMX8MN_CLK_ENET1_ROOT>,
> <&clk
> IMX8MN_CLK_ENET_TIMER>, diff --git
> a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 9de2aa1c573c..cad2dd790bec 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -713,7 +713,8 @@
> reg = <0x30be0000 0x10000>;
> interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk
> IMX8MP_CLK_ENET1_ROOT>,
> <&clk
> IMX8MP_CLK_SIM_ENET_ROOT>,
> <&clk
> IMX8MP_CLK_ENET_TIMER>, diff --git
> a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index f70435cf9ad5..0d02ccdb0abc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -1031,7 +1031,8 @@
> reg = <0x30be0000 0x10000>;
> interrupts = <GIC_SPI 118
> IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 119
> IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>;
> + <GIC_SPI 120
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121
> + IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk
> IMX8MQ_CLK_ENET1_ROOT>,
> <&clk
> IMX8MQ_CLK_ENET1_ROOT>,
> <&clk
> IMX8MQ_CLK_ENET_TIMER>,
> --
> 2.17.1
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt
2020-08-19 1:59 [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt Fabio Estevam
2020-08-19 2:34 ` [EXT] " Andy Duan
@ 2020-08-23 2:15 ` Shawn Guo
1 sibling, 0 replies; 3+ messages in thread
From: Shawn Guo @ 2020-08-23 2:15 UTC (permalink / raw)
To: Fabio Estevam; +Cc: linux-arm-kernel, fugang.duan, linux-imx, kernel
On Tue, Aug 18, 2020 at 10:59:46PM -0300, Fabio Estevam wrote:
> The i.MX8M SoCs have a fourth ENET interrupt dedicated to PPS (Pulse Per
> Second). Add support for it.
>
> Suggested-by: Rogerio Nunes <rogerio.nunes@nxp.com>
> Signed-off-by: Fabio Estevam <festevam@gmail.com>
Applied, thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-08-19 1:59 [PATCH] arm64: dts: imx8m: Add the ENET PPS interrupt Fabio Estevam
2020-08-19 2:34 ` [EXT] " Andy Duan
2020-08-23 2:15 ` Shawn Guo
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