* [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
@ 2016-08-11 4:43 Shengzhou Liu
2016-08-11 4:43 ` [U-Boot] [PATCH 2/2] armv8:ls1012a: Use common MMDC driver for ls1012a Shengzhou Liu
2016-08-11 19:44 ` [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver york sun
0 siblings, 2 replies; 6+ messages in thread
From: Shengzhou Liu @ 2016-08-11 4:43 UTC (permalink / raw)
To: u-boot
This patch adds basic support for Freescale MMDC(Multi Mode DDR Controller).
Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a
update to this driver to support more flexible configuration if new features
(DDR4, multiple controllers/chip selections, etc) are implimented in future.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
---
Makefile | 1 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 +
drivers/ddr/fsl/Makefile | 1 +
drivers/ddr/fsl/fsl_mmdc.c | 152 ++++++++++++++++++++++
include/fsl_mmdc.h | 83 +++++-------
5 files changed, 192 insertions(+), 47 deletions(-)
create mode 100644 drivers/ddr/fsl/fsl_mmdc.c
diff --git a/Makefile b/Makefile
index 99cc8cf..1bf6c6a 100644
--- a/Makefile
+++ b/Makefile
@@ -647,6 +647,7 @@ libs-y += drivers/power/ \
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b0ad4b4..478b7ab 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -18,6 +18,8 @@
#ifndef CONFIG_LS1012A
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+#else
+#define CONFIG_SYS_FSL_MMDC /* Freescale MMDC driver */
#endif
/*
diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
index 01ea862..00dea42 100644
--- a/drivers/ddr/fsl/Makefile
+++ b/drivers/ddr/fsl/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
+obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
new file mode 100644
index 0000000..eb36cea
--- /dev/null
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
+ */
+
+#include <common.h>
+#include <fsl_mmdc.h>
+#include <asm/io.h>
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+ int timeout = 1000;
+
+ out_be32(ptr, value);
+
+ while (in_be32(ptr) & bits) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0)
+ printf("Error: %p wait for clear timeout.\n", ptr);
+}
+
+void mmdc_init(void)
+{
+ struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+ unsigned int tmp;
+
+ /* 1. set configuration request */
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+ /* 2. configure the desired timing parameters */
+ out_be32(&mmdc->mdotc, CONFIG_MMDC_MDOTC);
+ out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0);
+ out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1);
+ out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2);
+
+ /* 3. configure DDR type and other miscellaneous parameters */
+ out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC);
+ out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
+ out_be32(&mmdc->mdrwd, CONFIG_MMDC_MDRWD);
+ out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL);
+
+ /* 4. configure the required delay while leaving reset */
+ out_be32(&mmdc->mdor, CONFIG_MMDC_MDOR);
+
+ /* 5. configure DDR physical parameters */
+ /* set row/column address width, burst length, data bus width */
+ tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1);
+ out_be32(&mmdc->mdctl, tmp);
+ /* configure address space partition */
+ out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP);
+
+ /* 6. perform a ZQ calibration - not needed here, doing in #8b */
+
+ /* 7. enable MMDC with the desired chip select */
+#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
+ out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
+#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
+ out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
+#endif
+
+ /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
+
+ /* 8b. ZQ calibration */
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
+
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, CONFIG_MMDC_MPZQHWCTRL,
+ MPZQHWCTRL_ZQ_HW_FORCE);
+
+ /* 9a. calibrations now, wr lvl */
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
+ CMD_NORMAL);
+
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
+ MPWLGCR_HW_WL_EN);
+
+ mdelay(1);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+ out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+ mdelay(1);
+
+ /* 9b. read DQS gating calibration */
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+ out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+ /* set absolute read delay offset for bytes */
+ out_be32(&mmdc->mprddlctl, CONFIG_MMDC_MPRDDLCTL);
+
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* 9c. read calibration */
+ out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+ out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+ out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
+ MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
+
+ out_be32(&mmdc->mdscr, (MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3));
+
+ /* 10. configure power-down, self-refresh entry, exit parameters */
+ out_be32(&mmdc->mdpdc, CONFIG_MMDC_MDPDC);
+ out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
+
+ /* 11. ZQ config again? do nothing here */
+
+ /* 12. refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref, CONFIG_MMDC_MDREF,
+ MDREF_START_REFRESH);
+
+ /* 13. disable CON_REQ */
+ out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
+}
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
index a939d89..a10e40c 100644
--- a/include/fsl_mmdc.h
+++ b/include/fsl_mmdc.h
@@ -7,63 +7,39 @@
#ifndef FSL_MMDC_H
#define FSL_MMDC_H
-#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
-#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
-
-#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
-#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
-#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
-#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
-
-#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
-
-#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
-
-#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
-
-#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
-
-/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
-#define WR_LVL_HW_EN 0x00000001
+/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
+#define MPWLGCR_HW_WL_EN (1 << 0)
/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
-#define MPR_COMPARE_EN 0x00000001
+#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
-#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
-#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
-#define AUTO_RD_CALIBRATION_EN 0x00000010
-
-#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
+#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
-#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
+/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
+#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
-#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
-
-#define START_REFRESH 0x00000001
+/* MMDC Core Refresh Control Register (MMDC_MDREF) */
+#define MDREF_START_REFRESH (1 << 0)
/* MMDC Core Special Command Register (MDSCR) */
-#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
-
-#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
-
-#define DISABLE_CFG_REQ 0x0
-#define CONFIGURATION_REQ (0x1 << 15)
-#define WL_EN (0x1 << 9)
-
-#define CMD_NORMAL (0x0 << 4)
-#define CMD_PRECHARGE (0x1 << 4)
-#define CMD_AUTO_REFRESH (0x2 << 4)
-#define CMD_LOAD_MODE_REG (0x3 << 4)
-#define CMD_ZQ_CALIBRATION (0x4 << 4)
-#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
-#define CMD_MRR (0x6 << 4)
-
+#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+#define MDSCR_DISABLE_CFG_REQ (0 << 15)
+#define MDSCR_ENABLE_CON_REQ (1 << 15)
+#define MDSCR_CON_ACK (1 << 14)
+#define MDSCR_WL_EN (1 << 9)
+#define CMD_NORMAL (0 << 4)
+#define CMD_PRECHARGE (1 << 4)
+#define CMD_AUTO_REFRESH (2 << 4)
+#define CMD_LOAD_MODE_REG (3 << 4)
+#define CMD_ZQ_CALIBRATION (4 << 4)
+#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
+#define CMD_MRR (6 << 4)
#define CMD_BANK_ADDR_0 0x0
#define CMD_BANK_ADDR_1 0x1
#define CMD_BANK_ADDR_2 0x2
@@ -73,8 +49,19 @@
#define CMD_BANK_ADDR_6 0x6
#define CMD_BANK_ADDR_7 0x7
+/* MMDC Core Control Register (MDCTL) */
+#define MDCTL_SDE0 (1 << 31)
+#define MDCTL_SDE1 (1 << 30)
+
+/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
+#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
+
+/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
+#define MMDC_MPMUR0_FRC_MSR (1 << 11)
+
+
/* MMDC Registers */
-struct mmdc_p_regs {
+struct mmdc_regs {
u32 mdctl;
u32 mdpdc;
u32 mdotc;
@@ -157,4 +144,6 @@ struct mmdc_p_regs {
u32 mpdccr;
};
+void mmdc_init(void);
+
#endif /* FSL_MMDC_H */
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] armv8:ls1012a: Use common MMDC driver for ls1012a
2016-08-11 4:43 [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver Shengzhou Liu
@ 2016-08-11 4:43 ` Shengzhou Liu
2016-08-11 19:44 ` [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver york sun
1 sibling, 0 replies; 6+ messages in thread
From: Shengzhou Liu @ 2016-08-11 4:43 UTC (permalink / raw)
To: u-boot
Let's use common MMDC driver for DDR initialization on
LS1012ARDB, LS1012AQDS, LS1012AFRDM boards.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
---
board/freescale/ls1012afrdm/ls1012afrdm.c | 116 ------------------------------
board/freescale/ls1012aqds/ls1012aqds.c | 116 ------------------------------
board/freescale/ls1012ardb/ls1012ardb.c | 116 ------------------------------
include/configs/ls1012afrdm.h | 23 ++++--
include/configs/ls1012aqds.h | 24 ++++++-
include/configs/ls1012ardb.h | 22 ++++--
6 files changed, 57 insertions(+), 360 deletions(-)
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index a94a458..0bbb558 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -18,20 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
- int timeout = 1000;
-
- out_be32(ptr, value);
-
- while (in_be32(ptr) & bits) {
- udelay(100);
- timeout--;
- }
- if (timeout <= 0)
- puts("Error: wait for clear timeout.\n");
-}
-
int checkboard(void)
{
puts("Board: LS1012AFRDM ");
@@ -39,108 +25,6 @@ int checkboard(void)
return 0;
}
-void mmdc_init(void)
-{
- struct mmdc_p_regs *mmdc =
- (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- /* configure timing parms */
- out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
- out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
- out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
- out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
- /* other parms */
- out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
- out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
- out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
- out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
- /* out of reset delays */
- out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
- out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
- /* Enable MMDC */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
- /* dram init sequence: update MRs */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
- CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
- set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
- CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
- FORCE_ZQ_AUTO_CALIBRATION);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
- CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
- set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
- mdelay(1);
-
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
- set_wait_for_bits_clear(&mmdc->mpdgctrl0,
- AUTO_RD_DQS_GATING_CALIBRATION_EN,
- AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- set_wait_for_bits_clear(&mmdc->mprddlhwctl,
- AUTO_RD_CALIBRATION_EN,
- AUTO_RD_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* PD, SR */
- out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
- out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
- /* refresh scheme */
- set_wait_for_bits_clear(&mmdc->mdref,
- CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
- START_REFRESH);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
int dram_init(void)
{
mmdc_init();
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 71eea82..392b6c2 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -28,20 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
- int timeout = 1000;
-
- out_be32(ptr, value);
-
- while (in_be32(ptr) & bits) {
- udelay(100);
- timeout--;
- }
- if (timeout <= 0)
- puts("Error: wait for clear timeout.\n");
-}
-
int checkboard(void)
{
char buf[64];
@@ -67,108 +53,6 @@ int checkboard(void)
return 0;
}
-void mmdc_init(void)
-{
- struct mmdc_p_regs *mmdc =
- (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- /* configure timing parms */
- out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
- out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
- out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
- out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
- /* other parms */
- out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
- out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
- out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
- out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
- /* out of reset delays */
- out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
- out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
- /* Enable MMDC */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
- /* dram init sequence: update MRs */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
- CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
- set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
- CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
- FORCE_ZQ_AUTO_CALIBRATION);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
- CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
- set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
- mdelay(1);
-
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
- set_wait_for_bits_clear(&mmdc->mpdgctrl0,
- AUTO_RD_DQS_GATING_CALIBRATION_EN,
- AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- set_wait_for_bits_clear(&mmdc->mprddlhwctl,
- AUTO_RD_CALIBRATION_EN,
- AUTO_RD_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* PD, SR */
- out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
- out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
- /* refresh scheme */
- set_wait_for_bits_clear(&mmdc->mdref,
- CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
- START_REFRESH);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
int dram_init(void)
{
mmdc_init();
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index f69768d..80426f6 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -22,20 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
- int timeout = 1000;
-
- out_be32(ptr, value);
-
- while (in_be32(ptr) & bits) {
- udelay(100);
- timeout--;
- }
- if (timeout <= 0)
- puts("Error: wait for clear timeout.\n");
-}
-
int checkboard(void)
{
u8 in1;
@@ -71,108 +57,6 @@ int checkboard(void)
return 0;
}
-void mmdc_init(void)
-{
- struct mmdc_p_regs *mmdc =
- (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- /* configure timing parms */
- out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING);
- out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
- out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
- out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
- /* other parms */
- out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC);
- out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
- out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
- out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
- /* out of reset delays */
- out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
- /* physical parms */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
- out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
- /* Enable MMDC */
- out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
- /* dram init sequence: update MRs */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
- CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
- /* dram init sequence: ZQCL */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
- set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
- CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
- FORCE_ZQ_AUTO_CALIBRATION);
-
- /* Calibrations now: wr lvl */
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
- CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
- set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
- mdelay(1);
-
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
- out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
- mdelay(1);
-
- /* Calibrations now: Read DQS gating calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
- set_wait_for_bits_clear(&mmdc->mpdgctrl0,
- AUTO_RD_DQS_GATING_CALIBRATION_EN,
- AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* Calibrations now: Read calibration */
- out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
- CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
- out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
- CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
- out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
- set_wait_for_bits_clear(&mmdc->mprddlhwctl,
- AUTO_RD_CALIBRATION_EN,
- AUTO_RD_CALIBRATION_EN);
-
- out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
- CMD_BANK_ADDR_3));
-
- /* PD, SR */
- out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
- out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
- /* refresh scheme */
- set_wait_for_bits_clear(&mmdc->mdref,
- CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
- START_REFRESH);
-
- /* disable CON_REQ */
- out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
int dram_init(void)
{
mmdc_init();
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index ad81142..dd77bc1 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -9,19 +9,34 @@
#include "ls1012a_common.h"
+/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x04180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x84180000
-
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+/* DDR board-specific timing parameters */
+#define CONFIG_MMDC_MDCTL 0x04180000
+#define CONFIG_MMDC_MDPDC 0x00030035
+#define CONFIG_MMDC_MDOTC 0x12554000
+#define CONFIG_MMDC_MDCFG0 0xbabf7954
+#define CONFIG_MMDC_MDCFG1 0xff328f64
+#define CONFIG_MMDC_MDCFG2 0x01ff00db
+#define CONFIG_MMDC_MDMISC 0x00001680
+#define CONFIG_MMDC_MDREF 0x0f3c8000
+#define CONFIG_MMDC_MDRWD 0x00002000
+#define CONFIG_MMDC_MDOR 0x00bf1023
+#define CONFIG_MMDC_MDASP 0x0000007f
+#define CONFIG_MMDC_MPODTCTRL 0x0000022a
+#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
+#define CONFIG_MMDC_MPRDDLCTL 0x40404040
+
+
/*
* USB
*/
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 6e31ca0..08f1117 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -9,14 +9,32 @@
#include "ls1012a_common.h"
-
+/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+
+/* DDR board-specific timing parameters */
+#define CONFIG_MMDC_MDCTL 0x05180000
+#define CONFIG_MMDC_MDPDC 0x00030035
+#define CONFIG_MMDC_MDOTC 0x12554000
+#define CONFIG_MMDC_MDCFG0 0xbabf7954
+#define CONFIG_MMDC_MDCFG1 0xff328f64
+#define CONFIG_MMDC_MDCFG2 0x01ff00db
+#define CONFIG_MMDC_MDMISC 0x00001680
+#define CONFIG_MMDC_MDREF 0x0f3c8000
+#define CONFIG_MMDC_MDRWD 0x00002000
+#define CONFIG_MMDC_MDOR 0x00bf1023
+#define CONFIG_MMDC_MDASP 0x0000007f
+#define CONFIG_MMDC_MPODTCTRL 0x0000022a
+#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
+#define CONFIG_MMDC_MPRDDLCTL 0x40404040
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
/*
* QIXIS Definitions
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 6046ab7..7c7d868 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -9,20 +9,32 @@
#include "ls1012a_common.h"
-
+/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
-
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x9fffffff
+/* DDR board-specific timing parameters */
+#define CONFIG_MMDC_MDCTL 0x05180000
+#define CONFIG_MMDC_MDPDC 0x00030035
+#define CONFIG_MMDC_MDOTC 0x12554000
+#define CONFIG_MMDC_MDCFG0 0xbabf7954
+#define CONFIG_MMDC_MDCFG1 0xff328f64
+#define CONFIG_MMDC_MDCFG2 0x01ff00db
+#define CONFIG_MMDC_MDMISC 0x00001680
+#define CONFIG_MMDC_MDREF 0x0f3c8000
+#define CONFIG_MMDC_MDRWD 0x00002000
+#define CONFIG_MMDC_MDOR 0x00bf1023
+#define CONFIG_MMDC_MDASP 0x0000007f
+#define CONFIG_MMDC_MPODTCTRL 0x0000022a
+#define CONFIG_MMDC_MPZQHWCTRL 0xa1390003
+#define CONFIG_MMDC_MPRDDLCTL 0x40404040
+
/*
* USB
*/
--
2.1.0.27.g96db324
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
2016-08-11 4:43 [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver Shengzhou Liu
2016-08-11 4:43 ` [U-Boot] [PATCH 2/2] armv8:ls1012a: Use common MMDC driver for ls1012a Shengzhou Liu
@ 2016-08-11 19:44 ` york sun
2016-08-12 3:44 ` Shengzhou Liu
1 sibling, 1 reply; 6+ messages in thread
From: york sun @ 2016-08-11 19:44 UTC (permalink / raw)
To: u-boot
On 08/10/2016 09:55 PM, Shengzhou Liu wrote:
> This patch adds basic support for Freescale MMDC(Multi Mode DDR Controller).
> Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a
> update to this driver to support more flexible configuration if new features
> (DDR4, multiple controllers/chip selections, etc) are implimented in future.
>
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
> ---
> Makefile | 1 +
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 +
> drivers/ddr/fsl/Makefile | 1 +
> drivers/ddr/fsl/fsl_mmdc.c | 152 ++++++++++++++++++++++
> include/fsl_mmdc.h | 83 +++++-------
> 5 files changed, 192 insertions(+), 47 deletions(-)
> create mode 100644 drivers/ddr/fsl/fsl_mmdc.c
>
> diff --git a/Makefile b/Makefile
> index 99cc8cf..1bf6c6a 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -647,6 +647,7 @@ libs-y += drivers/power/ \
> libs-y += drivers/spi/
> libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
> libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
> +libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
> libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
> libs-y += drivers/serial/
> libs-y += drivers/usb/dwc3/
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index b0ad4b4..478b7ab 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -18,6 +18,8 @@
> #ifndef CONFIG_LS1012A
> #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
> #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
> +#else
> +#define CONFIG_SYS_FSL_MMDC /* Freescale MMDC driver */
> #endif
Let's revert this logic, shall we?
>
> /*
> diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile
> index 01ea862..00dea42 100644
> --- a/drivers/ddr/fsl/Makefile
> +++ b/drivers/ddr/fsl/Makefile
> @@ -33,3 +33,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
> obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
> obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
> obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
> +obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
> diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
> new file mode 100644
> index 0000000..eb36cea
> --- /dev/null
> +++ b/drivers/ddr/fsl/fsl_mmdc.c
> @@ -0,0 +1,152 @@
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
I think we should use NXP now.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +/*
> + * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
> + */
> +
> +#include <common.h>
> +#include <fsl_mmdc.h>
> +#include <asm/io.h>
> +
> +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
> +{
> + int timeout = 1000;
> +
> + out_be32(ptr, value);
> +
> + while (in_be32(ptr) & bits) {
> + udelay(100);
> + timeout--;
> + }
> + if (timeout <= 0)
> + printf("Error: %p wait for clear timeout.\n", ptr);
> +}
> +
> +void mmdc_init(void)
> +{
> + struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
> + unsigned int tmp;
> +
> + /* 1. set configuration request */
> + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
> +
> + /* 2. configure the desired timing parameters */
> + out_be32(&mmdc->mdotc, CONFIG_MMDC_MDOTC);
> + out_be32(&mmdc->mdcfg0, CONFIG_MMDC_MDCFG0);
> + out_be32(&mmdc->mdcfg1, CONFIG_MMDC_MDCFG1);
> + out_be32(&mmdc->mdcfg2, CONFIG_MMDC_MDCFG2);
> +
> + /* 3. configure DDR type and other miscellaneous parameters */
> + out_be32(&mmdc->mdmisc, CONFIG_MMDC_MDMISC);
> + out_be32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
> + out_be32(&mmdc->mdrwd, CONFIG_MMDC_MDRWD);
> + out_be32(&mmdc->mpodtctrl, CONFIG_MMDC_MPODTCTRL);
> +
> + /* 4. configure the required delay while leaving reset */
> + out_be32(&mmdc->mdor, CONFIG_MMDC_MDOR);
> +
> + /* 5. configure DDR physical parameters */
> + /* set row/column address width, burst length, data bus width */
> + tmp = CONFIG_MMDC_MDCTL & ~(MDCTL_SDE0 | MDCTL_SDE1);
> + out_be32(&mmdc->mdctl, tmp);
> + /* configure address space partition */
> + out_be32(&mmdc->mdasp, CONFIG_MMDC_MDASP);
> +
> + /* 6. perform a ZQ calibration - not needed here, doing in #8b */
> +
> + /* 7. enable MMDC with the desired chip select */
> +#if (CONFIG_CHIP_SELECTS_PER_CTRL == 1)
> + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0);
> +#elif (CONFIG_CHIP_SELECTS_PER_CTRL == 2)
> + out_be32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
> +#endif
> +
> + /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2);
> +
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
> +
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
> +
> + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
> + CMD_ADDR_LSB_MR_ADDR(0x30) |
> + MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
> +
> + /* 8b. ZQ calibration */
> + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) | MDSCR_ENABLE_CON_REQ |
> + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
> +
> + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, CONFIG_MMDC_MPZQHWCTRL,
> + MPZQHWCTRL_ZQ_HW_FORCE);
> +
> + /* 9a. calibrations now, wr lvl */
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) |
> + MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
> +
> + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | MDSCR_WL_EN |
> + CMD_NORMAL);
> +
> + set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
> + MPWLGCR_HW_WL_EN);
> +
> + mdelay(1);
> +
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
> + out_be32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
> +
> + mdelay(1);
> +
> + /* 9b. read DQS gating calibration */
> + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
> + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
> +
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
> +
> + out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
> + /* set absolute read delay offset for bytes */
> + out_be32(&mmdc->mprddlctl, CONFIG_MMDC_MPRDDLCTL);
> +
> + set_wait_for_bits_clear(&mmdc->mpdgctrl0,
> + AUTO_RD_DQS_GATING_CALIBRATION_EN,
> + AUTO_RD_DQS_GATING_CALIBRATION_EN);
> +
> + out_be32(&mmdc->mdscr, (MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
> + CMD_BANK_ADDR_3));
> +
> + /* 9c. read calibration */
> + out_be32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
> + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
> + out_be32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
> + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
> + out_be32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
> + set_wait_for_bits_clear(&mmdc->mprddlhwctl,
> + MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
> + MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
> +
> + out_be32(&mmdc->mdscr, (MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
> + CMD_BANK_ADDR_3));
> +
> + /* 10. configure power-down, self-refresh entry, exit parameters */
> + out_be32(&mmdc->mdpdc, CONFIG_MMDC_MDPDC);
> + out_be32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
> +
> + /* 11. ZQ config again? do nothing here */
> +
> + /* 12. refresh scheme */
> + set_wait_for_bits_clear(&mmdc->mdref, CONFIG_MMDC_MDREF,
> + MDREF_START_REFRESH);
> +
> + /* 13. disable CON_REQ */
> + out_be32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
> +}
> diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
> index a939d89..a10e40c 100644
> --- a/include/fsl_mmdc.h
> +++ b/include/fsl_mmdc.h
> @@ -7,63 +7,39 @@
> #ifndef FSL_MMDC_H
> #define FSL_MMDC_H
>
> -#define CONFIG_SYS_MMDC_CORE_ODT_TIMING 0x12554000
> -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0 0xbabf7954
> -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64
> -#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db
> -
> -#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680
> -#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800
> -#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000
> -#define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a
> -
> -#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY 0x00bf1023
> -
> -#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION 0x0000007f
> -
> -#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL 0xa1390003
> -
> -#define FORCE_ZQ_AUTO_CALIBRATION (0x1 << 16)
> -
> -/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
> -#define WR_LVL_HW_EN 0x00000001
> +/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
> +#define MPWLGCR_HW_WL_EN (1 << 0)
>
> /* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
> -#define MPR_COMPARE_EN 0x00000001
> +#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
>
> -#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG 0x40404040
>
> /* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
> -#define AUTO_RD_DQS_GATING_CALIBRATION_EN 0x10000000
> +#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
>
> /* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
> -#define AUTO_RD_CALIBRATION_EN 0x00000010
> -
> -#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL 0x00030035
> +#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
>
> -#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT 0x00001067
> +/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
> +#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
>
> -#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL 0x0f3c8000
> -
> -#define START_REFRESH 0x00000001
> +/* MMDC Core Refresh Control Register (MMDC_MDREF) */
> +#define MDREF_START_REFRESH (1 << 0)
>
> /* MMDC Core Special Command Register (MDSCR) */
> -#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
> -
> -#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
> -
> -#define DISABLE_CFG_REQ 0x0
> -#define CONFIGURATION_REQ (0x1 << 15)
> -#define WL_EN (0x1 << 9)
> -
> -#define CMD_NORMAL (0x0 << 4)
> -#define CMD_PRECHARGE (0x1 << 4)
> -#define CMD_AUTO_REFRESH (0x2 << 4)
> -#define CMD_LOAD_MODE_REG (0x3 << 4)
> -#define CMD_ZQ_CALIBRATION (0x4 << 4)
> -#define CMD_PRECHARGE_BANK_OPEN (0x5 << 4)
> -#define CMD_MRR (0x6 << 4)
> -
> +#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
> +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
> +#define MDSCR_DISABLE_CFG_REQ (0 << 15)
> +#define MDSCR_ENABLE_CON_REQ (1 << 15)
> +#define MDSCR_CON_ACK (1 << 14)
> +#define MDSCR_WL_EN (1 << 9)
> +#define CMD_NORMAL (0 << 4)
> +#define CMD_PRECHARGE (1 << 4)
> +#define CMD_AUTO_REFRESH (2 << 4)
> +#define CMD_LOAD_MODE_REG (3 << 4)
> +#define CMD_ZQ_CALIBRATION (4 << 4)
> +#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
> +#define CMD_MRR (6 << 4)
> #define CMD_BANK_ADDR_0 0x0
> #define CMD_BANK_ADDR_1 0x1
> #define CMD_BANK_ADDR_2 0x2
Removing those macros causes compiling error for ls1012afrdm_qspi
ls1012aqds_qspi ls1012ardb_qspi. Please rearrange the change.
York
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
2016-08-11 19:44 ` [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver york sun
@ 2016-08-12 3:44 ` Shengzhou Liu
2016-08-12 5:56 ` york sun
0 siblings, 1 reply; 6+ messages in thread
From: Shengzhou Liu @ 2016-08-12 3:44 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: york sun
> Sent: Friday, August 12, 2016 3:45 AM
> To: Shengzhou Liu <shengzhou.liu@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
>
> > +#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
> > +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
> > +#define MDSCR_DISABLE_CFG_REQ (0 << 15)
> > +#define MDSCR_ENABLE_CON_REQ (1 << 15)
> > +#define MDSCR_CON_ACK (1 << 14)
> > +#define MDSCR_WL_EN (1 << 9)
> > +#define CMD_NORMAL (0 << 4)
> > +#define CMD_PRECHARGE (1 << 4)
> > +#define CMD_AUTO_REFRESH (2 << 4)
> > +#define CMD_LOAD_MODE_REG (3 << 4)
> > +#define CMD_ZQ_CALIBRATION (4 << 4)
> > +#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
> > +#define CMD_MRR (6 << 4)
> > #define CMD_BANK_ADDR_0 0x0
> > #define CMD_BANK_ADDR_1 0x1
> > #define CMD_BANK_ADDR_2 0x2
>
> Removing those macros causes compiling error for ls1012afrdm_qspi
> ls1012aqds_qspi ls1012ardb_qspi. Please rearrange the change.
>
> York
Why do you want to remove those macros? They are needed and useful, I compiled it for ls1012a QDS/ RDB/FRDM without any issue, and worked fine on boards.
Shengzhou
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
2016-08-12 3:44 ` Shengzhou Liu
@ 2016-08-12 5:56 ` york sun
2016-08-12 10:08 ` Shengzhou Liu
0 siblings, 1 reply; 6+ messages in thread
From: york sun @ 2016-08-12 5:56 UTC (permalink / raw)
To: u-boot
I am not suggesting remove the macros. Please try to compile after applying first patch. You will see the errors
York
-------- Original Message --------
From: Shengzhou Liu <shengzhou.liu@nxp.com>
Sent: Thursday, August 11, 2016 08:44 PM
To: york sun <york.sun@nxp.com>,u-boot at lists.denx.de
Subject: RE: [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
> -----Original Message-----
> From: york sun
> Sent: Friday, August 12, 2016 3:45 AM
> To: Shengzhou Liu <shengzhou.liu@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
>
> > +#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
> > +#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
> > +#define MDSCR_DISABLE_CFG_REQ (0 << 15)
> > +#define MDSCR_ENABLE_CON_REQ (1 << 15)
> > +#define MDSCR_CON_ACK (1 << 14)
> > +#define MDSCR_WL_EN (1 << 9)
> > +#define CMD_NORMAL (0 << 4)
> > +#define CMD_PRECHARGE (1 << 4)
> > +#define CMD_AUTO_REFRESH (2 << 4)
> > +#define CMD_LOAD_MODE_REG (3 << 4)
> > +#define CMD_ZQ_CALIBRATION (4 << 4)
> > +#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
> > +#define CMD_MRR (6 << 4)
> > #define CMD_BANK_ADDR_0 0x0
> > #define CMD_BANK_ADDR_1 0x1
> > #define CMD_BANK_ADDR_2 0x2
>
> Removing those macros causes compiling error for ls1012afrdm_qspi
> ls1012aqds_qspi ls1012ardb_qspi. Please rearrange the change.
>
> York
Why do you want to remove those macros? They are needed and useful, I compiled it for ls1012a QDS/ RDB/FRDM without any issue, and worked fine on boards.
Shengzhou
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
2016-08-12 5:56 ` york sun
@ 2016-08-12 10:08 ` Shengzhou Liu
0 siblings, 0 replies; 6+ messages in thread
From: Shengzhou Liu @ 2016-08-12 10:08 UTC (permalink / raw)
To: u-boot
It needs to apply both patches before compiling. The second patch will remove the old board level code and apply common mmdc driver.
I understand that in theory we should keep every single patch is compileable, but to make it clean to customer I separated them to two patches.
Do I really need to combine the two to one patch?
Shengzhou
From: york sun
Sent: Friday, August 12, 2016 1:56 PM
To: Shengzhou Liu <shengzhou.liu@nxp.com>; u-boot at lists.denx.de
Subject: RE: [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver
I am not suggesting remove the macros. Please try to compile after applying first patch. You will see the errors
York
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-08-12 10:08 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-11 4:43 [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver Shengzhou Liu
2016-08-11 4:43 ` [U-Boot] [PATCH 2/2] armv8:ls1012a: Use common MMDC driver for ls1012a Shengzhou Liu
2016-08-11 19:44 ` [U-Boot] [PATCH 1/2] driver/ddr/fsl: Add general MMDC driver york sun
2016-08-12 3:44 ` Shengzhou Liu
2016-08-12 5:56 ` york sun
2016-08-12 10:08 ` Shengzhou Liu
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