* [PATCH v3 00/13] AT91 pm cleanup for 3.20
@ 2015-01-27 5:50 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:50 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
Hi Nicolas,
This version is rebased on the branch: at91-3.20-cleanup of the repository
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
It is purpose to clean up the PM code, includes the patches from Peter Rosin and Sylvain Rochet.
Since verifying the USB clock and USB PLL disabling before suspending to memory,
it aslo depends on the following patch serials from Sylvain:
[PATCHv6 0/5] USB: gadget: atmel_usba_udc: Driver improvements
[PATCHv7 0/6] USB: host: Atmel OHCI and EHCI drivers improvements
Removes CONFIG_AT91_SLOW_CLOCK config item to simply the PM config,
The suspend to standby mode uses the same sram function as the suspend to memory mode.
Remove some unused code.
Alexandr & Sylvain, Thank you very much for so many feedbacks.
Changes in v2:
- Rebase on the at91-3.20-cleanup branch
- Recover the verify clock condition, only for suspend to memory.
- Collect ACK from Alexandre
- Add the macro for PM mode
Changes in v3
- Sylvain splits the patch in two
- Add handling if no sram allocated for PM
- Retain the STANDBY and SUSPEND_MEM select in at91_pm_enter.
Peter Rosin (1):
pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
Sylvain Rochet (2):
pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts
pm: at91: pm_slowclock: remove clocks which are already stopped when
entering slow clock mode
Wenyou Yang (10):
pm: at91: pm_slowclock: remove the unused code related with
SLOWDOWN_MASTER_CLOCK
pm: at91: move the copying the sram function to the sram
initializationi phase
ARM: at91: move select SRAM to ARCH_AT91
pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
pm: at91: the standby mode uses the same sram function as the suspend
to memory mode
pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S
pm: at91: rename function name:
at91_slow_clock()-->at91_pm_suspend_sram_fn
pm: at91: remove the at91_xxx_standby() function definitions in the
pm.h
pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby
members
pm: at91: amend the pm_suspend entry for at91_cpuidle_device
arch/arm/mach-at91/Kconfig | 17 +-
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/pm.c | 150 ++++++++---------
arch/arm/mach-at91/pm.h | 100 +----------
arch/arm/mach-at91/pm_slowclock.S | 323 ------------------------------------
arch/arm/mach-at91/pm_suspend.S | 277 +++++++++++++++++++++++++++++++
arch/arm/mach-at91/setup.c | 19 +--
include/soc/at91/at91sam9_ddrsdr.h | 2 +-
8 files changed, 367 insertions(+), 523 deletions(-)
delete mode 100644 arch/arm/mach-at91/pm_slowclock.S
create mode 100644 arch/arm/mach-at91/pm_suspend.S
--
1.7.9.5
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 00/13] AT91 pm cleanup for 3.20
@ 2015-01-27 5:50 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi Nicolas,
This version is rebased on the branch: at91-3.20-cleanup of the repository
git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91.git
It is purpose to clean up the PM code, includes the patches from Peter Rosin and Sylvain Rochet.
Since verifying the USB clock and USB PLL disabling before suspending to memory,
it aslo depends on the following patch serials from Sylvain:
[PATCHv6 0/5] USB: gadget: atmel_usba_udc: Driver improvements
[PATCHv7 0/6] USB: host: Atmel OHCI and EHCI drivers improvements
Removes CONFIG_AT91_SLOW_CLOCK config item to simply the PM config,
The suspend to standby mode uses the same sram function as the suspend to memory mode.
Remove some unused code.
Alexandr & Sylvain, Thank you very much for so many feedbacks.
Changes in v2:
- Rebase on the at91-3.20-cleanup branch
- Recover the verify clock condition, only for suspend to memory.
- Collect ACK from Alexandre
- Add the macro for PM mode
Changes in v3
- Sylvain splits the patch in two
- Add handling if no sram allocated for PM
- Retain the STANDBY and SUSPEND_MEM select in at91_pm_enter.
Peter Rosin (1):
pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
Sylvain Rochet (2):
pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts
pm: at91: pm_slowclock: remove clocks which are already stopped when
entering slow clock mode
Wenyou Yang (10):
pm: at91: pm_slowclock: remove the unused code related with
SLOWDOWN_MASTER_CLOCK
pm: at91: move the copying the sram function to the sram
initializationi phase
ARM: at91: move select SRAM to ARCH_AT91
pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
pm: at91: the standby mode uses the same sram function as the suspend
to memory mode
pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S
pm: at91: rename function name:
at91_slow_clock()-->at91_pm_suspend_sram_fn
pm: at91: remove the at91_xxx_standby() function definitions in the
pm.h
pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby
members
pm: at91: amend the pm_suspend entry for at91_cpuidle_device
arch/arm/mach-at91/Kconfig | 17 +-
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/pm.c | 150 ++++++++---------
arch/arm/mach-at91/pm.h | 100 +----------
arch/arm/mach-at91/pm_slowclock.S | 323 ------------------------------------
arch/arm/mach-at91/pm_suspend.S | 277 +++++++++++++++++++++++++++++++
arch/arm/mach-at91/setup.c | 19 +--
include/soc/at91/at91sam9_ddrsdr.h | 2 +-
8 files changed, 367 insertions(+), 523 deletions(-)
delete mode 100644 arch/arm/mach-at91/pm_slowclock.S
create mode 100644 arch/arm/mach-at91/pm_suspend.S
--
1.7.9.5
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 01/13] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:51 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:51 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
From: Sylvain Rochet <sylvain.rochet@finsecur.com>
Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
something went wrong instead of continuing in unknown condition. There
is not much we can do if a PLL lock never ends, we are running in SRAM
and we will not be able to connect back the sdram or ddram in order to
be able to fire up a message or just panic.
As a bonus, not decounting the timeout register in slow clock mode
reduce cumulated suspend time and resume time from ~17ms to ~15ms.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
---
arch/arm/mach-at91/pm_slowclock.S | 33 ++++-----------------------------
1 file changed, 4 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 556151e..50744e7 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -25,11 +25,6 @@
*/
#undef SLOWDOWN_MASTER_CLOCK
-#define MCKRDY_TIMEOUT 1000
-#define MOSCRDY_TIMEOUT 1000
-#define PLLALOCK_TIMEOUT 1000
-#define PLLBLOCK_TIMEOUT 1000
-
pmc .req r0
sdramc .req r1
ramc1 .req r2
@@ -41,56 +36,36 @@ tmp2 .req r5
* Wait until master clock is ready (after switching master clock source)
*/
.macro wait_mckrdy
- mov tmp2, #MCKRDY_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MCKRDY
beq 1b
-2:
.endm
/*
* Wait until master oscillator has stabilized.
*/
.macro wait_moscrdy
- mov tmp2, #MOSCRDY_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCS
beq 1b
-2:
.endm
/*
* Wait until PLLA has locked.
*/
.macro wait_pllalock
- mov tmp2, #PLLALOCK_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKA
beq 1b
-2:
.endm
/*
* Wait until PLLB has locked.
*/
.macro wait_pllblock
- mov tmp2, #PLLBLOCK_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKB
beq 1b
-2:
.endm
.text
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 01/13] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts
@ 2015-01-27 5:51 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:51 UTC (permalink / raw)
To: linux-arm-kernel
From: Sylvain Rochet <sylvain.rochet@finsecur.com>
Removed timeout on XTAL, PLL lock and Master Clock Ready, hang if
something went wrong instead of continuing in unknown condition. There
is not much we can do if a PLL lock never ends, we are running in SRAM
and we will not be able to connect back the sdram or ddram in order to
be able to fire up a message or just panic.
As a bonus, not decounting the timeout register in slow clock mode
reduce cumulated suspend time and resume time from ~17ms to ~15ms.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
---
arch/arm/mach-at91/pm_slowclock.S | 33 ++++-----------------------------
1 file changed, 4 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 556151e..50744e7 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -25,11 +25,6 @@
*/
#undef SLOWDOWN_MASTER_CLOCK
-#define MCKRDY_TIMEOUT 1000
-#define MOSCRDY_TIMEOUT 1000
-#define PLLALOCK_TIMEOUT 1000
-#define PLLBLOCK_TIMEOUT 1000
-
pmc .req r0
sdramc .req r1
ramc1 .req r2
@@ -41,56 +36,36 @@ tmp2 .req r5
* Wait until master clock is ready (after switching master clock source)
*/
.macro wait_mckrdy
- mov tmp2, #MCKRDY_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MCKRDY
beq 1b
-2:
.endm
/*
* Wait until master oscillator has stabilized.
*/
.macro wait_moscrdy
- mov tmp2, #MOSCRDY_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_MOSCS
beq 1b
-2:
.endm
/*
* Wait until PLLA has locked.
*/
.macro wait_pllalock
- mov tmp2, #PLLALOCK_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKA
beq 1b
-2:
.endm
/*
* Wait until PLLB has locked.
*/
.macro wait_pllblock
- mov tmp2, #PLLBLOCK_TIMEOUT
-1: sub tmp2, tmp2, #1
- cmp tmp2, #0
- beq 2f
- ldr tmp1, [pmc, #AT91_PMC_SR]
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
tst tmp1, #AT91_PMC_LOCKB
beq 1b
-2:
.endm
.text
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 02/13] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:52 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:52 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
From: Sylvain Rochet <sylvain.rochet@finsecur.com>
Assume USB PLL and PLL B are already stopped before entering sleep mode,
print a warning if this isn't the case.
Removed PLL B from slow clock code, all drivers are supposed to properly
unprepare clocks.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
---
arch/arm/mach-at91/pm.c | 12 ++++++++++++
arch/arm/mach-at91/pm_slowclock.S | 31 -------------------------------
2 files changed, 12 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 87c1fd8..5dd4e41 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -98,6 +98,18 @@ static int at91_pm_verify_clocks(void)
}
}
+ /* Drivers should have previously suspended USB PLL */
+ if (at91_pmc_read(AT91_CKGR_UCKR) & AT91_PMC_UPLLEN) {
+ pr_err("AT91: PM - Suspend-to-RAM with USB PLL running\n");
+ return 0;
+ }
+
+ /* Drivers should have previously suspended PLL B */
+ if (at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) {
+ pr_err("AT91: PM - Suspend-to-RAM with PLL B running\n");
+ return 0;
+ }
+
return 1;
}
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 50744e7..e2bfaf5 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -59,15 +59,6 @@ tmp2 .req r5
beq 1b
.endm
-/*
- * Wait until PLLB has locked.
- */
- .macro wait_pllblock
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_LOCKB
- beq 1b
- .endm
-
.text
/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
@@ -173,13 +164,6 @@ sdr_sr_done:
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
str tmp1, [pmc, #AT91_CKGR_PLLAR]
- /* Save PLLB setting and disable it */
- ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
- str tmp1, .saved_pllbr
-
- mov tmp1, #AT91_PMC_PLLCOUNT
- str tmp1, [pmc, #AT91_CKGR_PLLBR]
-
/* Turn off the main oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCEN
@@ -195,18 +179,6 @@ sdr_sr_done:
wait_moscrdy
- /* Restore PLLB setting */
- ldr tmp1, .saved_pllbr
- str tmp1, [pmc, #AT91_CKGR_PLLBR]
-
- tst tmp1, #(AT91_PMC_MUL & 0xff0000)
- bne 1f
- tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
- beq 2f
-1:
- wait_pllblock
-2:
-
/* Restore PLLA setting */
ldr tmp1, .saved_pllar
str tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -285,9 +257,6 @@ ram_restored:
.saved_pllar:
.word 0
-.saved_pllbr:
- .word 0
-
.saved_sam9_lpr:
.word 0
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 02/13] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode
@ 2015-01-27 5:52 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Sylvain Rochet <sylvain.rochet@finsecur.com>
Assume USB PLL and PLL B are already stopped before entering sleep mode,
print a warning if this isn't the case.
Removed PLL B from slow clock code, all drivers are supposed to properly
unprepare clocks.
Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com>
---
arch/arm/mach-at91/pm.c | 12 ++++++++++++
arch/arm/mach-at91/pm_slowclock.S | 31 -------------------------------
2 files changed, 12 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 87c1fd8..5dd4e41 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -98,6 +98,18 @@ static int at91_pm_verify_clocks(void)
}
}
+ /* Drivers should have previously suspended USB PLL */
+ if (at91_pmc_read(AT91_CKGR_UCKR) & AT91_PMC_UPLLEN) {
+ pr_err("AT91: PM - Suspend-to-RAM with USB PLL running\n");
+ return 0;
+ }
+
+ /* Drivers should have previously suspended PLL B */
+ if (at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) {
+ pr_err("AT91: PM - Suspend-to-RAM with PLL B running\n");
+ return 0;
+ }
+
return 1;
}
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 50744e7..e2bfaf5 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -59,15 +59,6 @@ tmp2 .req r5
beq 1b
.endm
-/*
- * Wait until PLLB has locked.
- */
- .macro wait_pllblock
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_LOCKB
- beq 1b
- .endm
-
.text
/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
@@ -173,13 +164,6 @@ sdr_sr_done:
orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
str tmp1, [pmc, #AT91_CKGR_PLLAR]
- /* Save PLLB setting and disable it */
- ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
- str tmp1, .saved_pllbr
-
- mov tmp1, #AT91_PMC_PLLCOUNT
- str tmp1, [pmc, #AT91_CKGR_PLLBR]
-
/* Turn off the main oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
bic tmp1, tmp1, #AT91_PMC_MOSCEN
@@ -195,18 +179,6 @@ sdr_sr_done:
wait_moscrdy
- /* Restore PLLB setting */
- ldr tmp1, .saved_pllbr
- str tmp1, [pmc, #AT91_CKGR_PLLBR]
-
- tst tmp1, #(AT91_PMC_MUL & 0xff0000)
- bne 1f
- tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
- beq 2f
-1:
- wait_pllblock
-2:
-
/* Restore PLLA setting */
ldr tmp1, .saved_pllar
str tmp1, [pmc, #AT91_CKGR_PLLAR]
@@ -285,9 +257,6 @@ ram_restored:
.saved_pllar:
.word 0
-.saved_pllbr:
- .word 0
-
.saved_sam9_lpr:
.word 0
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:53 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:53 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
From: Peter Rosin <peda@axentia.se>
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.
Assume that the second controller has the same fault, but that is
untested.
Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/pm_slowclock.S | 43 +++++++++++++++++++++++++++++++-----
include/soc/at91/at91sam9_ddrsdr.h | 2 +-
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index e2bfaf5..1155217 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -100,6 +100,16 @@ ddr_sr_enable:
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_sr_enable
+ /* LPDDR1 --> force DDR2 mode during self-refresh */
+ ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ str tmp1, .saved_sam9_mdr
+ bic tmp1, tmp1, #~AT91_DDRSDRC_MD
+ cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ biceq tmp1, tmp1, #AT91_DDRSDRC_MD
+ orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
+ streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+
/* prepare for DDRAM self-refresh mode */
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
str tmp1, .saved_sam9_lpr
@@ -108,14 +118,26 @@ ddr_sr_enable:
/* figure out if we use the second ram controller */
cmp ramc1, #0
- ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
- strne tmp2, .saved_sam9_lpr1
- bicne tmp2, #AT91_DDRSDRC_LPCB
- orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+ beq ddr_no_2nd_ctrl
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ str tmp2, .saved_sam9_mdr1
+ bic tmp2, tmp2, #~AT91_DDRSDRC_MD
+ cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ biceq tmp2, tmp2, #AT91_DDRSDRC_MD
+ orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
+ streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ str tmp2, .saved_sam9_lpr1
+ bic tmp2, #AT91_DDRSDRC_LPCB
+ orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
/* Enable DDRAM self-refresh mode */
+ str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ddr_no_2nd_ctrl:
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
- strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
b sdr_sr_done
@@ -227,12 +249,17 @@ sdr_sr_done:
*/
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_en_restore
+ /* Restore MDR in case of LPDDR1 */
+ ldr tmp1, .saved_sam9_mdr
+ str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
/* Restore LPR on AT91 with DDRAM */
ldr tmp1, .saved_sam9_lpr
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
/* if we use the second ram controller */
cmp ramc1, #0
+ ldrne tmp2, .saved_sam9_mdr1
+ strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
ldrne tmp2, .saved_sam9_lpr1
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
@@ -263,5 +290,11 @@ ram_restored:
.saved_sam9_lpr1:
.word 0
+.saved_sam9_mdr:
+ .word 0
+
+.saved_sam9_mdr1:
+ .word 0
+
ENTRY(at91_slow_clock_sz)
.word .-at91_slow_clock
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
index 0210797..dc10c52 100644
--- a/include/soc/at91/at91sam9_ddrsdr.h
+++ b/include/soc/at91/at91sam9_ddrsdr.h
@@ -92,7 +92,7 @@
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
-#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
+#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
@ 2015-01-27 5:53 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Peter Rosin <peda@axentia.se>
The DDRSDR controller fails miserably to put LPDDR1 memories in
self-refresh. Force the controller to think it has DDR2 memories
during the self-refresh period, as the DDR2 self-refresh spec is
equivalent to LPDDR1, and is correctly implemented in the
controller.
Assume that the second controller has the same fault, but that is
untested.
Signed-off-by: Peter Rosin <peda@axentia.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
---
arch/arm/mach-at91/pm_slowclock.S | 43 +++++++++++++++++++++++++++++++-----
include/soc/at91/at91sam9_ddrsdr.h | 2 +-
2 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index e2bfaf5..1155217 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -100,6 +100,16 @@ ddr_sr_enable:
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_sr_enable
+ /* LPDDR1 --> force DDR2 mode during self-refresh */
+ ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ str tmp1, .saved_sam9_mdr
+ bic tmp1, tmp1, #~AT91_DDRSDRC_MD
+ cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ biceq tmp1, tmp1, #AT91_DDRSDRC_MD
+ orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
+ streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+
/* prepare for DDRAM self-refresh mode */
ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
str tmp1, .saved_sam9_lpr
@@ -108,14 +118,26 @@ ddr_sr_enable:
/* figure out if we use the second ram controller */
cmp ramc1, #0
- ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
- strne tmp2, .saved_sam9_lpr1
- bicne tmp2, #AT91_DDRSDRC_LPCB
- orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+ beq ddr_no_2nd_ctrl
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ str tmp2, .saved_sam9_mdr1
+ bic tmp2, tmp2, #~AT91_DDRSDRC_MD
+ cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ biceq tmp2, tmp2, #AT91_DDRSDRC_MD
+ orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
+ streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ str tmp2, .saved_sam9_lpr1
+ bic tmp2, #AT91_DDRSDRC_LPCB
+ orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
/* Enable DDRAM self-refresh mode */
+ str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ddr_no_2nd_ctrl:
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
- strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
b sdr_sr_done
@@ -227,12 +249,17 @@ sdr_sr_done:
*/
cmp memctrl, #AT91_MEMCTRL_DDRSDR
bne sdr_en_restore
+ /* Restore MDR in case of LPDDR1 */
+ ldr tmp1, .saved_sam9_mdr
+ str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
/* Restore LPR on AT91 with DDRAM */
ldr tmp1, .saved_sam9_lpr
str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
/* if we use the second ram controller */
cmp ramc1, #0
+ ldrne tmp2, .saved_sam9_mdr1
+ strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
ldrne tmp2, .saved_sam9_lpr1
strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
@@ -263,5 +290,11 @@ ram_restored:
.saved_sam9_lpr1:
.word 0
+.saved_sam9_mdr:
+ .word 0
+
+.saved_sam9_mdr1:
+ .word 0
+
ENTRY(at91_slow_clock_sz)
.word .-at91_slow_clock
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h
index 0210797..dc10c52 100644
--- a/include/soc/at91/at91sam9_ddrsdr.h
+++ b/include/soc/at91/at91sam9_ddrsdr.h
@@ -92,7 +92,7 @@
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
-#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
+#define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 04/13] pm: at91: pm_slowclock: remove the unused code related with SLOWDOWN_MASTER_CLOCK
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:54 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:54 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
The SLOWDOWN_MASTER_CLOCK definition is not used, remove the redundant code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm_slowclock.S | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 1155217..4e55665 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -11,20 +11,11 @@
* published by the Free Software Foundation.
*
*/
-
#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
-/*
- * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
- * clock during suspend by adjusting its prescalar and divisor.
- * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
- * are errata regarding adjusting the prescalar and divisor.
- */
-#undef SLOWDOWN_MASTER_CLOCK
-
pmc .req r0
sdramc .req r1
ramc1 .req r2
@@ -166,18 +157,6 @@ sdr_sr_done:
wait_mckrdy
-#ifdef SLOWDOWN_MASTER_CLOCK
- /*
- * Set the Master Clock PRES and MDIV fields.
- *
- * See AT91RM9200 errata #27 and #28 for details.
- */
- mov tmp1, #0
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-#endif
-
/* Save PLLA setting and disable it */
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
str tmp1, .saved_pllar
@@ -213,22 +192,6 @@ sdr_sr_done:
wait_pllalock
4:
-#ifdef SLOWDOWN_MASTER_CLOCK
- /*
- * First set PRES if it was not 0,
- * than set CSS and MDIV fields.
- *
- * See AT91RM9200 errata #27 and #28 for details.
- */
- ldr tmp1, .saved_mckr
- tst tmp1, #AT91_PMC_PRES
- beq 2f
- and tmp1, tmp1, #AT91_PMC_PRES
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-#endif
-
/*
* Restore master clock setting
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 04/13] pm: at91: pm_slowclock: remove the unused code related with SLOWDOWN_MASTER_CLOCK
@ 2015-01-27 5:54 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:54 UTC (permalink / raw)
To: linux-arm-kernel
The SLOWDOWN_MASTER_CLOCK definition is not used, remove the redundant code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm_slowclock.S | 37 -------------------------------------
1 file changed, 37 deletions(-)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 1155217..4e55665 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -11,20 +11,11 @@
* published by the Free Software Foundation.
*
*/
-
#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
-/*
- * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
- * clock during suspend by adjusting its prescalar and divisor.
- * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
- * are errata regarding adjusting the prescalar and divisor.
- */
-#undef SLOWDOWN_MASTER_CLOCK
-
pmc .req r0
sdramc .req r1
ramc1 .req r2
@@ -166,18 +157,6 @@ sdr_sr_done:
wait_mckrdy
-#ifdef SLOWDOWN_MASTER_CLOCK
- /*
- * Set the Master Clock PRES and MDIV fields.
- *
- * See AT91RM9200 errata #27 and #28 for details.
- */
- mov tmp1, #0
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-#endif
-
/* Save PLLA setting and disable it */
ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
str tmp1, .saved_pllar
@@ -213,22 +192,6 @@ sdr_sr_done:
wait_pllalock
4:
-#ifdef SLOWDOWN_MASTER_CLOCK
- /*
- * First set PRES if it was not 0,
- * than set CSS and MDIV fields.
- *
- * See AT91RM9200 errata #27 and #28 for details.
- */
- ldr tmp1, .saved_mckr
- tst tmp1, #AT91_PMC_PRES
- beq 2f
- and tmp1, tmp1, #AT91_PMC_PRES
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-#endif
-
/*
* Restore master clock setting
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 05/13] pm: at91: move the copying the sram function to the sram initializationi phase
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:55 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:55 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
To decrease the suspend time, move the copying the sram function
to the sram initialization phase, instead of every time go to suspend.
In the meanwhile, if there is no sram allocated for PM, the PM is not supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5dd4e41..6b08098 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -161,10 +161,6 @@ static int at91_pm_enter(suspend_state_t state)
* turning off the main oscillator; reverse on wakeup.
*/
if (slow_clock) {
-#ifdef CONFIG_AT91_SLOW_CLOCK
- /* copy slow_clock handler to SRAM, and call it */
- memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
-#endif
slow_clock(at91_pmc_base, at91_ramc_base[0],
at91_ramc_base[1],
at91_pm_data.memctrl);
@@ -272,6 +268,9 @@ static void __init at91_pm_sram_init(void)
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
+ /* Copy the slow_clock handler to SRAM */
+ memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+
put_node:
of_node_put(node);
}
@@ -289,7 +288,10 @@ static void __init at91_pm_init(void)
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
- suspend_set_ops(&at91_pm_ops);
+ if (slow_clock)
+ suspend_set_ops(&at91_pm_ops);
+ else
+ pr_info("AT91: PM : Not supported, due to no sram allocated\n");
}
void __init at91_rm9200_pm_init(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 05/13] pm: at91: move the copying the sram function to the sram initializationi phase
@ 2015-01-27 5:55 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:55 UTC (permalink / raw)
To: linux-arm-kernel
To decrease the suspend time, move the copying the sram function
to the sram initialization phase, instead of every time go to suspend.
In the meanwhile, if there is no sram allocated for PM, the PM is not supported.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 5dd4e41..6b08098 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -161,10 +161,6 @@ static int at91_pm_enter(suspend_state_t state)
* turning off the main oscillator; reverse on wakeup.
*/
if (slow_clock) {
-#ifdef CONFIG_AT91_SLOW_CLOCK
- /* copy slow_clock handler to SRAM, and call it */
- memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
-#endif
slow_clock(at91_pmc_base, at91_ramc_base[0],
at91_ramc_base[1],
at91_pm_data.memctrl);
@@ -272,6 +268,9 @@ static void __init at91_pm_sram_init(void)
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
+ /* Copy the slow_clock handler to SRAM */
+ memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+
put_node:
of_node_put(node);
}
@@ -289,7 +288,10 @@ static void __init at91_pm_init(void)
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
- suspend_set_ops(&at91_pm_ops);
+ if (slow_clock)
+ suspend_set_ops(&at91_pm_ops);
+ else
+ pr_info("AT91: PM : Not supported, due to no sram allocated\n");
}
void __init at91_rm9200_pm_init(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 06/13] ARM: at91: move select SRAM to ARCH_AT91
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:56 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:56 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
Because the CONFIG_AT91_SLOW_CLOCK will be removed
to simply the PM config, so move select SRAM.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c6956b8..cbaf0c8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -24,6 +24,7 @@ config SOC_AT91SAM9
select GENERIC_CLOCKEVENTS
select MEMORY
select ATMEL_SDRAMC
+ select SRAM if PM
config SOC_SAMA5
bool
@@ -34,6 +35,7 @@ config SOC_SAMA5
select MEMORY
select ATMEL_SDRAMC
select PHYLIB if NETDEVICES
+ select SRAM if PM
menu "Atmel AT91 System-on-Chip"
@@ -91,6 +93,7 @@ config SOC_AT91RM9200
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_USB_CLK
+ select SRAM if PM
config SOC_AT91SAM9260
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
@@ -159,7 +162,6 @@ comment "AT91 Feature Selections"
config AT91_SLOW_CLOCK
bool "Suspend-to-RAM disables main oscillator"
- select SRAM
depends on SUSPEND
help
Select this if you want Suspend-to-RAM to save the most power
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 06/13] ARM: at91: move select SRAM to ARCH_AT91
@ 2015-01-27 5:56 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:56 UTC (permalink / raw)
To: linux-arm-kernel
Because the CONFIG_AT91_SLOW_CLOCK will be removed
to simply the PM config, so move select SRAM.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c6956b8..cbaf0c8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -24,6 +24,7 @@ config SOC_AT91SAM9
select GENERIC_CLOCKEVENTS
select MEMORY
select ATMEL_SDRAMC
+ select SRAM if PM
config SOC_SAMA5
bool
@@ -34,6 +35,7 @@ config SOC_SAMA5
select MEMORY
select ATMEL_SDRAMC
select PHYLIB if NETDEVICES
+ select SRAM if PM
menu "Atmel AT91 System-on-Chip"
@@ -91,6 +93,7 @@ config SOC_AT91RM9200
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_USB_CLK
+ select SRAM if PM
config SOC_AT91SAM9260
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
@@ -159,7 +162,6 @@ comment "AT91 Feature Selections"
config AT91_SLOW_CLOCK
bool "Suspend-to-RAM disables main oscillator"
- select SRAM
depends on SUSPEND
help
Select this if you want Suspend-to-RAM to save the most power
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:57 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:57 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
The slow clock always exists, for the suspend to memory mode,
the master clock always switch to the slow clock.
To simplify the PM config, remove this config item, remove
the definition code as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 13 -------------
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/pm.c | 7 -------
3 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index cbaf0c8..0af6744 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -160,19 +160,6 @@ endif # SOC_SAM_V4_V5
comment "AT91 Feature Selections"
-config AT91_SLOW_CLOCK
- bool "Suspend-to-RAM disables main oscillator"
- depends on SUSPEND
- help
- Select this if you want Suspend-to-RAM to save the most power
- possible (without powering off the CPU) by disabling the PLLs
- and main oscillator so that only the 32 KiHz clock is available.
-
- When only that slow-clock is available, some peripherals lose
- functionality. Many can't issue wakeup events unless faster
- clocks are available. Some lose their operating state and
- need to be completely re-initialized.
-
config AT91_TIMER_HZ
int "Kernel HZ (jiffies per second)"
range 32 1024
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8ef7d9a..13dd3e6 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
# Power Management
obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
+obj-$(CONFIG_PM) += pm_slowclock.o
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 6b08098..0377c0d 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -133,11 +133,9 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
-#ifdef CONFIG_AT91_SLOW_CLOCK
extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
extern u32 at91_slow_clock_sz;
-#endif
static int at91_pm_enter(suspend_state_t state)
{
@@ -232,7 +230,6 @@ void at91_pm_set_standby(void (*at91_standby)(void))
}
}
-#ifdef CONFIG_AT91_SLOW_CLOCK
static void __init at91_pm_sram_init(void)
{
struct gen_pool *sram_pool;
@@ -274,14 +271,10 @@ static void __init at91_pm_sram_init(void)
put_node:
of_node_put(node);
}
-#endif
-
static void __init at91_pm_init(void)
{
-#ifdef CONFIG_AT91_SLOW_CLOCK
at91_pm_sram_init();
-#endif
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
@ 2015-01-27 5:57 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:57 UTC (permalink / raw)
To: linux-arm-kernel
The slow clock always exists, for the suspend to memory mode,
the master clock always switch to the slow clock.
To simplify the PM config, remove this config item, remove
the definition code as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 13 -------------
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/pm.c | 7 -------
3 files changed, 1 insertion(+), 21 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index cbaf0c8..0af6744 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -160,19 +160,6 @@ endif # SOC_SAM_V4_V5
comment "AT91 Feature Selections"
-config AT91_SLOW_CLOCK
- bool "Suspend-to-RAM disables main oscillator"
- depends on SUSPEND
- help
- Select this if you want Suspend-to-RAM to save the most power
- possible (without powering off the CPU) by disabling the PLLs
- and main oscillator so that only the 32 KiHz clock is available.
-
- When only that slow-clock is available, some peripherals lose
- functionality. Many can't issue wakeup events unless faster
- clocks are available. Some lose their operating state and
- need to be completely re-initialized.
-
config AT91_TIMER_HZ
int "Kernel HZ (jiffies per second)"
range 32 1024
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8ef7d9a..13dd3e6 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
# Power Management
obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
+obj-$(CONFIG_PM) += pm_slowclock.o
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 6b08098..0377c0d 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -133,11 +133,9 @@ EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
-#ifdef CONFIG_AT91_SLOW_CLOCK
extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
extern u32 at91_slow_clock_sz;
-#endif
static int at91_pm_enter(suspend_state_t state)
{
@@ -232,7 +230,6 @@ void at91_pm_set_standby(void (*at91_standby)(void))
}
}
-#ifdef CONFIG_AT91_SLOW_CLOCK
static void __init at91_pm_sram_init(void)
{
struct gen_pool *sram_pool;
@@ -274,14 +271,10 @@ static void __init at91_pm_sram_init(void)
put_node:
of_node_put(node);
}
-#endif
-
static void __init at91_pm_init(void)
{
-#ifdef CONFIG_AT91_SLOW_CLOCK
at91_pm_sram_init();
-#endif
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:58 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:58 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
To simply the PM code, the suspend to standby mode uses the same sram function
as the suspend to memory mode, running in the internal SRAM,
instead of the respective code for each mode.
But for the suspend to standby mode, the master clock doesn't
switch to the slow clock, and the main oscillator doesn't
turn off as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/pm.c | 87 +++++++++++++++++--------------------
arch/arm/mach-at91/pm.h | 7 +++
arch/arm/mach-at91/pm_slowclock.S | 18 ++++++++
3 files changed, 65 insertions(+), 47 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 0377c0d..d967c31 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -71,7 +71,7 @@ static int at91_pm_begin(suspend_state_t state)
* Verify that all the clocks are correct before entering
* slow-clock mode.
*/
-static int at91_pm_verify_clocks(void)
+static int at91_pm_verify_clocks(suspend_state_t state)
{
unsigned long scsr;
int i;
@@ -137,62 +137,55 @@ extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
extern u32 at91_slow_clock_sz;
+static void at91_pm_suspend(suspend_state_t state)
+{
+ unsigned int pm_data = at91_pm_data.memctrl;
+
+ pm_data |= (state == PM_SUSPEND_MEM) ?
+ AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+
+ slow_clock(at91_pmc_base, at91_ramc_base[0],
+ at91_ramc_base[1], pm_data);
+}
+
static int at91_pm_enter(suspend_state_t state)
{
at91_pinctrl_gpio_suspend();
switch (state) {
+ /*
+ * Suspend-to-RAM is like STANDBY plus slow clock mode, so
+ * drivers must suspend more deeply, the master clock switches
+ * to the clk32k and turns off the main oscillator
+ */
+ case PM_SUSPEND_MEM:
/*
- * Suspend-to-RAM is like STANDBY plus slow clock mode, so
- * drivers must suspend more deeply: only the master clock
- * controller may be using the main oscillator.
+ * Ensure that clocks are in a valid state.
*/
- case PM_SUSPEND_MEM:
- /*
- * Ensure that clocks are in a valid state.
- */
- if (!at91_pm_verify_clocks())
- goto error;
-
- /*
- * Enter slow clock mode by switching over to clk32k and
- * turning off the main oscillator; reverse on wakeup.
- */
- if (slow_clock) {
- slow_clock(at91_pmc_base, at91_ramc_base[0],
- at91_ramc_base[1],
- at91_pm_data.memctrl);
- break;
- } else {
- pr_info("AT91: PM - no slow clock mode enabled ...\n");
- /* FALLTHROUGH leaving master clock alone */
- }
+ if (!at91_pm_verify_clocks(state))
+ goto error;
- /*
- * STANDBY mode has *all* drivers suspended; ignores irqs not
- * marked as 'wakeup' event sources; and reduces DRAM power.
- * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
- * nothing fancy done with main or cpu clocks.
- */
- case PM_SUSPEND_STANDBY:
- /*
- * NOTE: the Wait-for-Interrupt instruction needs to be
- * in icache so no SDRAM accesses are needed until the
- * wakeup IRQ occurs and self-refresh is terminated.
- * For ARM 926 based chips, this requirement is weaker
- * as at91sam9 can access a RAM in self-refresh mode.
- */
- if (at91_pm_standby)
- at91_pm_standby();
- break;
+ at91_pm_suspend(state);
- case PM_SUSPEND_ON:
- cpu_do_idle();
- break;
+ break;
- default:
- pr_debug("AT91: PM - bogus suspend state %d\n", state);
- goto error;
+ /*
+ * STANDBY mode has *all* drivers suspended; ignores irqs not
+ * marked as 'wakeup' event sources; and reduces DRAM power.
+ * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
+ * nothing fancy done with main or cpu clocks.
+ */
+ case PM_SUSPEND_STANDBY:
+ at91_pm_suspend(state);
+ break;
+
+ case PM_SUSPEND_ON:
+ cpu_do_idle();
+ break;
+
+ default:
+ pr_debug("AT91: PM - bogus suspend state %d\n", state);
+ goto error;
}
error:
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index d2c8996..5bc9c33 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -15,6 +15,13 @@
#include <mach/at91_ramc.h>
+#define AT91_PM_MEMCTRL_MASK 0x0f
+#define AT91_PM_MODE_OFFSET 4
+#define AT91_PM_MODE_MASK 0x0f
+#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
+
+#define AT91_PM_SLOW_CLOCK 0x01
+
#ifdef CONFIG_PM
extern void at91_pm_set_standby(void (*at91_standby)(void));
#else
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 4e55665..f56d114 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,12 +16,15 @@
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
+#include "pm.h"
+
pmc .req r0
sdramc .req r1
ramc1 .req r2
memctrl .req r3
tmp1 .req r4
tmp2 .req r5
+mode .req r6
/*
* Wait until master clock is ready (after switching master clock source)
@@ -73,6 +76,13 @@ ENTRY(at91_slow_clock)
mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4
+ mov tmp1, memctrl
+ mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET
+ and mode, tmp2, #AT91_PM_MODE_MASK
+
+ mov tmp1, memctrl
+ and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK
+
cmp memctrl, #AT91_MEMCTRL_MC
bne ddr_sr_enable
@@ -145,6 +155,9 @@ sdr_sr_enable:
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
sdr_sr_done:
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_disable_main_clock
+
/* Save Master clock setting */
ldr tmp1, [pmc, #AT91_PMC_MCKR]
str tmp1, .saved_mckr
@@ -170,9 +183,13 @@ sdr_sr_done:
bic tmp1, tmp1, #AT91_PMC_MOSCEN
str tmp1, [pmc, #AT91_CKGR_MOR]
+skip_disable_main_clock:
/* Wait for interrupt */
mcr p15, 0, tmp1, c7, c0, 4
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_enable_main_clock
+
/* Turn on the main oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCEN
@@ -200,6 +217,7 @@ sdr_sr_done:
wait_mckrdy
+skip_enable_main_clock:
/*
* at91rm9200 Memory controller
* Do nothing - self-refresh is automatically disabled.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode
@ 2015-01-27 5:58 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:58 UTC (permalink / raw)
To: linux-arm-kernel
To simply the PM code, the suspend to standby mode uses the same sram function
as the suspend to memory mode, running in the internal SRAM,
instead of the respective code for each mode.
But for the suspend to standby mode, the master clock doesn't
switch to the slow clock, and the main oscillator doesn't
turn off as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/pm.c | 87 +++++++++++++++++--------------------
arch/arm/mach-at91/pm.h | 7 +++
arch/arm/mach-at91/pm_slowclock.S | 18 ++++++++
3 files changed, 65 insertions(+), 47 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 0377c0d..d967c31 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -71,7 +71,7 @@ static int at91_pm_begin(suspend_state_t state)
* Verify that all the clocks are correct before entering
* slow-clock mode.
*/
-static int at91_pm_verify_clocks(void)
+static int at91_pm_verify_clocks(suspend_state_t state)
{
unsigned long scsr;
int i;
@@ -137,62 +137,55 @@ extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
extern u32 at91_slow_clock_sz;
+static void at91_pm_suspend(suspend_state_t state)
+{
+ unsigned int pm_data = at91_pm_data.memctrl;
+
+ pm_data |= (state == PM_SUSPEND_MEM) ?
+ AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
+
+ slow_clock(at91_pmc_base, at91_ramc_base[0],
+ at91_ramc_base[1], pm_data);
+}
+
static int at91_pm_enter(suspend_state_t state)
{
at91_pinctrl_gpio_suspend();
switch (state) {
+ /*
+ * Suspend-to-RAM is like STANDBY plus slow clock mode, so
+ * drivers must suspend more deeply, the master clock switches
+ * to the clk32k and turns off the main oscillator
+ */
+ case PM_SUSPEND_MEM:
/*
- * Suspend-to-RAM is like STANDBY plus slow clock mode, so
- * drivers must suspend more deeply: only the master clock
- * controller may be using the main oscillator.
+ * Ensure that clocks are in a valid state.
*/
- case PM_SUSPEND_MEM:
- /*
- * Ensure that clocks are in a valid state.
- */
- if (!at91_pm_verify_clocks())
- goto error;
-
- /*
- * Enter slow clock mode by switching over to clk32k and
- * turning off the main oscillator; reverse on wakeup.
- */
- if (slow_clock) {
- slow_clock(at91_pmc_base, at91_ramc_base[0],
- at91_ramc_base[1],
- at91_pm_data.memctrl);
- break;
- } else {
- pr_info("AT91: PM - no slow clock mode enabled ...\n");
- /* FALLTHROUGH leaving master clock alone */
- }
+ if (!at91_pm_verify_clocks(state))
+ goto error;
- /*
- * STANDBY mode has *all* drivers suspended; ignores irqs not
- * marked as 'wakeup' event sources; and reduces DRAM power.
- * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
- * nothing fancy done with main or cpu clocks.
- */
- case PM_SUSPEND_STANDBY:
- /*
- * NOTE: the Wait-for-Interrupt instruction needs to be
- * in icache so no SDRAM accesses are needed until the
- * wakeup IRQ occurs and self-refresh is terminated.
- * For ARM 926 based chips, this requirement is weaker
- * as at91sam9 can access a RAM in self-refresh mode.
- */
- if (at91_pm_standby)
- at91_pm_standby();
- break;
+ at91_pm_suspend(state);
- case PM_SUSPEND_ON:
- cpu_do_idle();
- break;
+ break;
- default:
- pr_debug("AT91: PM - bogus suspend state %d\n", state);
- goto error;
+ /*
+ * STANDBY mode has *all* drivers suspended; ignores irqs not
+ * marked as 'wakeup' event sources; and reduces DRAM power.
+ * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
+ * nothing fancy done with main or cpu clocks.
+ */
+ case PM_SUSPEND_STANDBY:
+ at91_pm_suspend(state);
+ break;
+
+ case PM_SUSPEND_ON:
+ cpu_do_idle();
+ break;
+
+ default:
+ pr_debug("AT91: PM - bogus suspend state %d\n", state);
+ goto error;
}
error:
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index d2c8996..5bc9c33 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -15,6 +15,13 @@
#include <mach/at91_ramc.h>
+#define AT91_PM_MEMCTRL_MASK 0x0f
+#define AT91_PM_MODE_OFFSET 4
+#define AT91_PM_MODE_MASK 0x0f
+#define AT91_PM_MODE(x) (((x) & AT91_PM_MODE_MASK) << AT91_PM_MODE_OFFSET)
+
+#define AT91_PM_SLOW_CLOCK 0x01
+
#ifdef CONFIG_PM
extern void at91_pm_set_standby(void (*at91_standby)(void));
#else
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index 4e55665..f56d114 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -16,12 +16,15 @@
#include <mach/hardware.h>
#include <mach/at91_ramc.h>
+#include "pm.h"
+
pmc .req r0
sdramc .req r1
ramc1 .req r2
memctrl .req r3
tmp1 .req r4
tmp2 .req r5
+mode .req r6
/*
* Wait until master clock is ready (after switching master clock source)
@@ -73,6 +76,13 @@ ENTRY(at91_slow_clock)
mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4
+ mov tmp1, memctrl
+ mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET
+ and mode, tmp2, #AT91_PM_MODE_MASK
+
+ mov tmp1, memctrl
+ and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK
+
cmp memctrl, #AT91_MEMCTRL_MC
bne ddr_sr_enable
@@ -145,6 +155,9 @@ sdr_sr_enable:
str tmp1, [sdramc, #AT91_SDRAMC_LPR]
sdr_sr_done:
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_disable_main_clock
+
/* Save Master clock setting */
ldr tmp1, [pmc, #AT91_PMC_MCKR]
str tmp1, .saved_mckr
@@ -170,9 +183,13 @@ sdr_sr_done:
bic tmp1, tmp1, #AT91_PMC_MOSCEN
str tmp1, [pmc, #AT91_CKGR_MOR]
+skip_disable_main_clock:
/* Wait for interrupt */
mcr p15, 0, tmp1, c7, c0, 4
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_enable_main_clock
+
/* Turn on the main oscillator */
ldr tmp1, [pmc, #AT91_CKGR_MOR]
orr tmp1, tmp1, #AT91_PMC_MOSCEN
@@ -200,6 +217,7 @@ sdr_sr_done:
wait_mckrdy
+skip_enable_main_clock:
/*
* at91rm9200 Memory controller
* Do nothing - self-refresh is automatically disabled.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 09/13] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:59 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:59 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
Because the sram function is used for the suspend to standby mode as well,
more than suspend to memory, so renaming is more elegant.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 281 -------------------------------------
arch/arm/mach-at91/pm_suspend.S | 281 +++++++++++++++++++++++++++++++++++++
3 files changed, 282 insertions(+), 282 deletions(-)
delete mode 100644 arch/arm/mach-at91/pm_slowclock.S
create mode 100644 arch/arm/mach-at91/pm_suspend.S
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 13dd3e6..aba208f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
# Power Management
obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += pm_slowclock.o
+obj-$(CONFIG_PM) += pm_suspend.o
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
deleted file mode 100644
index f56d114..0000000
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * arch/arm/mach-at91/pm_slow_clock.S
- *
- * Copyright (C) 2006 Savin Zlobec
- *
- * AT91SAM9 support:
- * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/linkage.h>
-#include <linux/clk/at91_pmc.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-
-#include "pm.h"
-
-pmc .req r0
-sdramc .req r1
-ramc1 .req r2
-memctrl .req r3
-tmp1 .req r4
-tmp2 .req r5
-mode .req r6
-
-/*
- * Wait until master clock is ready (after switching master clock source)
- */
- .macro wait_mckrdy
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_MCKRDY
- beq 1b
- .endm
-
-/*
- * Wait until master oscillator has stabilized.
- */
- .macro wait_moscrdy
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_MOSCS
- beq 1b
- .endm
-
-/*
- * Wait until PLLA has locked.
- */
- .macro wait_pllalock
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_LOCKA
- beq 1b
- .endm
-
- .text
-
-/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
- * void __iomem *ramc1, int memctrl)
- */
-ENTRY(at91_slow_clock)
- /* Save registers on stack */
- stmfd sp!, {r4 - r12, lr}
-
- /*
- * Register usage:
- * R0 = Base address of AT91_PMC
- * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
- * R2 = Base address of second RAM Controller or 0 if not present
- * R3 = Memory controller
- * R4 = temporary register
- * R5 = temporary register
- */
-
- /* Drain write buffer */
- mov tmp1, #0
- mcr p15, 0, tmp1, c7, c10, 4
-
- mov tmp1, memctrl
- mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET
- and mode, tmp2, #AT91_PM_MODE_MASK
-
- mov tmp1, memctrl
- and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK
-
- cmp memctrl, #AT91_MEMCTRL_MC
- bne ddr_sr_enable
-
- /*
- * at91rm9200 Memory controller
- */
- /* Put SDRAM in self-refresh mode */
- mov tmp1, #1
- str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
- b sdr_sr_done
-
- /*
- * DDRSDR Memory controller
- */
-ddr_sr_enable:
- cmp memctrl, #AT91_MEMCTRL_DDRSDR
- bne sdr_sr_enable
-
- /* LPDDR1 --> force DDR2 mode during self-refresh */
- ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
- str tmp1, .saved_sam9_mdr
- bic tmp1, tmp1, #~AT91_DDRSDRC_MD
- cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
- ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
- biceq tmp1, tmp1, #AT91_DDRSDRC_MD
- orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
- streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
-
- /* prepare for DDRAM self-refresh mode */
- ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
- str tmp1, .saved_sam9_lpr
- bic tmp1, #AT91_DDRSDRC_LPCB
- orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-
- /* figure out if we use the second ram controller */
- cmp ramc1, #0
- beq ddr_no_2nd_ctrl
-
- ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
- str tmp2, .saved_sam9_mdr1
- bic tmp2, tmp2, #~AT91_DDRSDRC_MD
- cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
- ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
- biceq tmp2, tmp2, #AT91_DDRSDRC_MD
- orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
- streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
-
- ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
- str tmp2, .saved_sam9_lpr1
- bic tmp2, #AT91_DDRSDRC_LPCB
- orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-
- /* Enable DDRAM self-refresh mode */
- str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-ddr_no_2nd_ctrl:
- str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-
- b sdr_sr_done
-
- /*
- * SDRAMC Memory controller
- */
-sdr_sr_enable:
- /* Enable SDRAM self-refresh mode */
- ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
- str tmp1, .saved_sam9_lpr
-
- bic tmp1, #AT91_SDRAMC_LPCB
- orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
- str tmp1, [sdramc, #AT91_SDRAMC_LPR]
-
-sdr_sr_done:
- tst mode, #AT91_PM_SLOW_CLOCK
- beq skip_disable_main_clock
-
- /* Save Master clock setting */
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
- str tmp1, .saved_mckr
-
- /*
- * Set the Master clock source to slow clock
- */
- bic tmp1, tmp1, #AT91_PMC_CSS
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-
- /* Save PLLA setting and disable it */
- ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
- str tmp1, .saved_pllar
-
- mov tmp1, #AT91_PMC_PLLCOUNT
- orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
- str tmp1, [pmc, #AT91_CKGR_PLLAR]
-
- /* Turn off the main oscillator */
- ldr tmp1, [pmc, #AT91_CKGR_MOR]
- bic tmp1, tmp1, #AT91_PMC_MOSCEN
- str tmp1, [pmc, #AT91_CKGR_MOR]
-
-skip_disable_main_clock:
- /* Wait for interrupt */
- mcr p15, 0, tmp1, c7, c0, 4
-
- tst mode, #AT91_PM_SLOW_CLOCK
- beq skip_enable_main_clock
-
- /* Turn on the main oscillator */
- ldr tmp1, [pmc, #AT91_CKGR_MOR]
- orr tmp1, tmp1, #AT91_PMC_MOSCEN
- str tmp1, [pmc, #AT91_CKGR_MOR]
-
- wait_moscrdy
-
- /* Restore PLLA setting */
- ldr tmp1, .saved_pllar
- str tmp1, [pmc, #AT91_CKGR_PLLAR]
-
- tst tmp1, #(AT91_PMC_MUL & 0xff0000)
- bne 3f
- tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
- beq 4f
-3:
- wait_pllalock
-4:
-
- /*
- * Restore master clock setting
- */
-2: ldr tmp1, .saved_mckr
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-
-skip_enable_main_clock:
- /*
- * at91rm9200 Memory controller
- * Do nothing - self-refresh is automatically disabled.
- */
- cmp memctrl, #AT91_MEMCTRL_MC
- beq ram_restored
-
- /*
- * DDRSDR Memory controller
- */
- cmp memctrl, #AT91_MEMCTRL_DDRSDR
- bne sdr_en_restore
- /* Restore MDR in case of LPDDR1 */
- ldr tmp1, .saved_sam9_mdr
- str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
- /* Restore LPR on AT91 with DDRAM */
- ldr tmp1, .saved_sam9_lpr
- str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-
- /* if we use the second ram controller */
- cmp ramc1, #0
- ldrne tmp2, .saved_sam9_mdr1
- strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
- ldrne tmp2, .saved_sam9_lpr1
- strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-
- b ram_restored
-
- /*
- * SDRAMC Memory controller
- */
-sdr_en_restore:
- /* Restore LPR on AT91 with SDRAM */
- ldr tmp1, .saved_sam9_lpr
- str tmp1, [sdramc, #AT91_SDRAMC_LPR]
-
-ram_restored:
- /* Restore registers, and return */
- ldmfd sp!, {r4 - r12, pc}
-
-
-.saved_mckr:
- .word 0
-
-.saved_pllar:
- .word 0
-
-.saved_sam9_lpr:
- .word 0
-
-.saved_sam9_lpr1:
- .word 0
-
-.saved_sam9_mdr:
- .word 0
-
-.saved_sam9_mdr1:
- .word 0
-
-ENTRY(at91_slow_clock_sz)
- .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
new file mode 100644
index 0000000..8edbad0
--- /dev/null
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -0,0 +1,281 @@
+/*
+ * arch/arm/mach-at91/pm_suspend.S
+ *
+ * Copyright (C) 2006 Savin Zlobec
+ *
+ * AT91SAM9 support:
+ * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/clk/at91_pmc.h>
+#include <mach/hardware.h>
+#include <mach/at91_ramc.h>
+
+#include "pm.h"
+
+pmc .req r0
+sdramc .req r1
+ramc1 .req r2
+memctrl .req r3
+tmp1 .req r4
+tmp2 .req r5
+mode .req r6
+
+/*
+ * Wait until master clock is ready (after switching master clock source)
+ */
+ .macro wait_mckrdy
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_MCKRDY
+ beq 1b
+ .endm
+
+/*
+ * Wait until master oscillator has stabilized.
+ */
+ .macro wait_moscrdy
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_MOSCS
+ beq 1b
+ .endm
+
+/*
+ * Wait until PLLA has locked.
+ */
+ .macro wait_pllalock
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_LOCKA
+ beq 1b
+ .endm
+
+ .text
+
+/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+ * void __iomem *ramc1, int memctrl)
+ */
+ENTRY(at91_slow_clock)
+ /* Save registers on stack */
+ stmfd sp!, {r4 - r12, lr}
+
+ /*
+ * Register usage:
+ * R0 = Base address of AT91_PMC
+ * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+ * R2 = Base address of second RAM Controller or 0 if not present
+ * R3 = Memory controller
+ * R4 = temporary register
+ * R5 = temporary register
+ */
+
+ /* Drain write buffer */
+ mov tmp1, #0
+ mcr p15, 0, tmp1, c7, c10, 4
+
+ mov tmp1, memctrl
+ mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET
+ and mode, tmp2, #AT91_PM_MODE_MASK
+
+ mov tmp1, memctrl
+ and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK
+
+ cmp memctrl, #AT91_MEMCTRL_MC
+ bne ddr_sr_enable
+
+ /*
+ * at91rm9200 Memory controller
+ */
+ /* Put SDRAM in self-refresh mode */
+ mov tmp1, #1
+ str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
+ b sdr_sr_done
+
+ /*
+ * DDRSDR Memory controller
+ */
+ddr_sr_enable:
+ cmp memctrl, #AT91_MEMCTRL_DDRSDR
+ bne sdr_sr_enable
+
+ /* LPDDR1 --> force DDR2 mode during self-refresh */
+ ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ str tmp1, .saved_sam9_mdr
+ bic tmp1, tmp1, #~AT91_DDRSDRC_MD
+ cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ biceq tmp1, tmp1, #AT91_DDRSDRC_MD
+ orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
+ streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+
+ /* prepare for DDRAM self-refresh mode */
+ ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+ str tmp1, .saved_sam9_lpr
+ bic tmp1, #AT91_DDRSDRC_LPCB
+ orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+ /* figure out if we use the second ram controller */
+ cmp ramc1, #0
+ beq ddr_no_2nd_ctrl
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ str tmp2, .saved_sam9_mdr1
+ bic tmp2, tmp2, #~AT91_DDRSDRC_MD
+ cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ biceq tmp2, tmp2, #AT91_DDRSDRC_MD
+ orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
+ streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ str tmp2, .saved_sam9_lpr1
+ bic tmp2, #AT91_DDRSDRC_LPCB
+ orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+ /* Enable DDRAM self-refresh mode */
+ str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ddr_no_2nd_ctrl:
+ str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+
+ b sdr_sr_done
+
+ /*
+ * SDRAMC Memory controller
+ */
+sdr_sr_enable:
+ /* Enable SDRAM self-refresh mode */
+ ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
+ str tmp1, .saved_sam9_lpr
+
+ bic tmp1, #AT91_SDRAMC_LPCB
+ orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
+ str tmp1, [sdramc, #AT91_SDRAMC_LPR]
+
+sdr_sr_done:
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_disable_main_clock
+
+ /* Save Master clock setting */
+ ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ str tmp1, .saved_mckr
+
+ /*
+ * Set the Master clock source to slow clock
+ */
+ bic tmp1, tmp1, #AT91_PMC_CSS
+ str tmp1, [pmc, #AT91_PMC_MCKR]
+
+ wait_mckrdy
+
+ /* Save PLLA setting and disable it */
+ ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
+ str tmp1, .saved_pllar
+
+ mov tmp1, #AT91_PMC_PLLCOUNT
+ orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
+ str tmp1, [pmc, #AT91_CKGR_PLLAR]
+
+ /* Turn off the main oscillator */
+ ldr tmp1, [pmc, #AT91_CKGR_MOR]
+ bic tmp1, tmp1, #AT91_PMC_MOSCEN
+ str tmp1, [pmc, #AT91_CKGR_MOR]
+
+skip_disable_main_clock:
+ /* Wait for interrupt */
+ mcr p15, 0, tmp1, c7, c0, 4
+
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_enable_main_clock
+
+ /* Turn on the main oscillator */
+ ldr tmp1, [pmc, #AT91_CKGR_MOR]
+ orr tmp1, tmp1, #AT91_PMC_MOSCEN
+ str tmp1, [pmc, #AT91_CKGR_MOR]
+
+ wait_moscrdy
+
+ /* Restore PLLA setting */
+ ldr tmp1, .saved_pllar
+ str tmp1, [pmc, #AT91_CKGR_PLLAR]
+
+ tst tmp1, #(AT91_PMC_MUL & 0xff0000)
+ bne 3f
+ tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
+ beq 4f
+3:
+ wait_pllalock
+4:
+
+ /*
+ * Restore master clock setting
+ */
+2: ldr tmp1, .saved_mckr
+ str tmp1, [pmc, #AT91_PMC_MCKR]
+
+ wait_mckrdy
+
+skip_enable_main_clock:
+ /*
+ * at91rm9200 Memory controller
+ * Do nothing - self-refresh is automatically disabled.
+ */
+ cmp memctrl, #AT91_MEMCTRL_MC
+ beq ram_restored
+
+ /*
+ * DDRSDR Memory controller
+ */
+ cmp memctrl, #AT91_MEMCTRL_DDRSDR
+ bne sdr_en_restore
+ /* Restore MDR in case of LPDDR1 */
+ ldr tmp1, .saved_sam9_mdr
+ str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ /* Restore LPR on AT91 with DDRAM */
+ ldr tmp1, .saved_sam9_lpr
+ str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+
+ /* if we use the second ram controller */
+ cmp ramc1, #0
+ ldrne tmp2, .saved_sam9_mdr1
+ strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ ldrne tmp2, .saved_sam9_lpr1
+ strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+
+ b ram_restored
+
+ /*
+ * SDRAMC Memory controller
+ */
+sdr_en_restore:
+ /* Restore LPR on AT91 with SDRAM */
+ ldr tmp1, .saved_sam9_lpr
+ str tmp1, [sdramc, #AT91_SDRAMC_LPR]
+
+ram_restored:
+ /* Restore registers, and return */
+ ldmfd sp!, {r4 - r12, pc}
+
+
+.saved_mckr:
+ .word 0
+
+.saved_pllar:
+ .word 0
+
+.saved_sam9_lpr:
+ .word 0
+
+.saved_sam9_lpr1:
+ .word 0
+
+.saved_sam9_mdr:
+ .word 0
+
+.saved_sam9_mdr1:
+ .word 0
+
+ENTRY(at91_slow_clock_sz)
+ .word .-at91_slow_clock
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 09/13] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S
@ 2015-01-27 5:59 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:59 UTC (permalink / raw)
To: linux-arm-kernel
Because the sram function is used for the suspend to standby mode as well,
more than suspend to memory, so renaming is more elegant.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/Makefile | 2 +-
arch/arm/mach-at91/pm_slowclock.S | 281 -------------------------------------
arch/arm/mach-at91/pm_suspend.S | 281 +++++++++++++++++++++++++++++++++++++
3 files changed, 282 insertions(+), 282 deletions(-)
delete mode 100644 arch/arm/mach-at91/pm_slowclock.S
create mode 100644 arch/arm/mach-at91/pm_suspend.S
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 13dd3e6..aba208f 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
# Power Management
obj-$(CONFIG_PM) += pm.o
-obj-$(CONFIG_PM) += pm_slowclock.o
+obj-$(CONFIG_PM) += pm_suspend.o
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
deleted file mode 100644
index f56d114..0000000
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * arch/arm/mach-at91/pm_slow_clock.S
- *
- * Copyright (C) 2006 Savin Zlobec
- *
- * AT91SAM9 support:
- * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-#include <linux/linkage.h>
-#include <linux/clk/at91_pmc.h>
-#include <mach/hardware.h>
-#include <mach/at91_ramc.h>
-
-#include "pm.h"
-
-pmc .req r0
-sdramc .req r1
-ramc1 .req r2
-memctrl .req r3
-tmp1 .req r4
-tmp2 .req r5
-mode .req r6
-
-/*
- * Wait until master clock is ready (after switching master clock source)
- */
- .macro wait_mckrdy
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_MCKRDY
- beq 1b
- .endm
-
-/*
- * Wait until master oscillator has stabilized.
- */
- .macro wait_moscrdy
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_MOSCS
- beq 1b
- .endm
-
-/*
- * Wait until PLLA has locked.
- */
- .macro wait_pllalock
-1: ldr tmp1, [pmc, #AT91_PMC_SR]
- tst tmp1, #AT91_PMC_LOCKA
- beq 1b
- .endm
-
- .text
-
-/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
- * void __iomem *ramc1, int memctrl)
- */
-ENTRY(at91_slow_clock)
- /* Save registers on stack */
- stmfd sp!, {r4 - r12, lr}
-
- /*
- * Register usage:
- * R0 = Base address of AT91_PMC
- * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
- * R2 = Base address of second RAM Controller or 0 if not present
- * R3 = Memory controller
- * R4 = temporary register
- * R5 = temporary register
- */
-
- /* Drain write buffer */
- mov tmp1, #0
- mcr p15, 0, tmp1, c7, c10, 4
-
- mov tmp1, memctrl
- mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET
- and mode, tmp2, #AT91_PM_MODE_MASK
-
- mov tmp1, memctrl
- and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK
-
- cmp memctrl, #AT91_MEMCTRL_MC
- bne ddr_sr_enable
-
- /*
- * at91rm9200 Memory controller
- */
- /* Put SDRAM in self-refresh mode */
- mov tmp1, #1
- str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
- b sdr_sr_done
-
- /*
- * DDRSDR Memory controller
- */
-ddr_sr_enable:
- cmp memctrl, #AT91_MEMCTRL_DDRSDR
- bne sdr_sr_enable
-
- /* LPDDR1 --> force DDR2 mode during self-refresh */
- ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
- str tmp1, .saved_sam9_mdr
- bic tmp1, tmp1, #~AT91_DDRSDRC_MD
- cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
- ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
- biceq tmp1, tmp1, #AT91_DDRSDRC_MD
- orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
- streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
-
- /* prepare for DDRAM self-refresh mode */
- ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
- str tmp1, .saved_sam9_lpr
- bic tmp1, #AT91_DDRSDRC_LPCB
- orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-
- /* figure out if we use the second ram controller */
- cmp ramc1, #0
- beq ddr_no_2nd_ctrl
-
- ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
- str tmp2, .saved_sam9_mdr1
- bic tmp2, tmp2, #~AT91_DDRSDRC_MD
- cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
- ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
- biceq tmp2, tmp2, #AT91_DDRSDRC_MD
- orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
- streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
-
- ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
- str tmp2, .saved_sam9_lpr1
- bic tmp2, #AT91_DDRSDRC_LPCB
- orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
-
- /* Enable DDRAM self-refresh mode */
- str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-ddr_no_2nd_ctrl:
- str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-
- b sdr_sr_done
-
- /*
- * SDRAMC Memory controller
- */
-sdr_sr_enable:
- /* Enable SDRAM self-refresh mode */
- ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
- str tmp1, .saved_sam9_lpr
-
- bic tmp1, #AT91_SDRAMC_LPCB
- orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
- str tmp1, [sdramc, #AT91_SDRAMC_LPR]
-
-sdr_sr_done:
- tst mode, #AT91_PM_SLOW_CLOCK
- beq skip_disable_main_clock
-
- /* Save Master clock setting */
- ldr tmp1, [pmc, #AT91_PMC_MCKR]
- str tmp1, .saved_mckr
-
- /*
- * Set the Master clock source to slow clock
- */
- bic tmp1, tmp1, #AT91_PMC_CSS
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-
- /* Save PLLA setting and disable it */
- ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
- str tmp1, .saved_pllar
-
- mov tmp1, #AT91_PMC_PLLCOUNT
- orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
- str tmp1, [pmc, #AT91_CKGR_PLLAR]
-
- /* Turn off the main oscillator */
- ldr tmp1, [pmc, #AT91_CKGR_MOR]
- bic tmp1, tmp1, #AT91_PMC_MOSCEN
- str tmp1, [pmc, #AT91_CKGR_MOR]
-
-skip_disable_main_clock:
- /* Wait for interrupt */
- mcr p15, 0, tmp1, c7, c0, 4
-
- tst mode, #AT91_PM_SLOW_CLOCK
- beq skip_enable_main_clock
-
- /* Turn on the main oscillator */
- ldr tmp1, [pmc, #AT91_CKGR_MOR]
- orr tmp1, tmp1, #AT91_PMC_MOSCEN
- str tmp1, [pmc, #AT91_CKGR_MOR]
-
- wait_moscrdy
-
- /* Restore PLLA setting */
- ldr tmp1, .saved_pllar
- str tmp1, [pmc, #AT91_CKGR_PLLAR]
-
- tst tmp1, #(AT91_PMC_MUL & 0xff0000)
- bne 3f
- tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
- beq 4f
-3:
- wait_pllalock
-4:
-
- /*
- * Restore master clock setting
- */
-2: ldr tmp1, .saved_mckr
- str tmp1, [pmc, #AT91_PMC_MCKR]
-
- wait_mckrdy
-
-skip_enable_main_clock:
- /*
- * at91rm9200 Memory controller
- * Do nothing - self-refresh is automatically disabled.
- */
- cmp memctrl, #AT91_MEMCTRL_MC
- beq ram_restored
-
- /*
- * DDRSDR Memory controller
- */
- cmp memctrl, #AT91_MEMCTRL_DDRSDR
- bne sdr_en_restore
- /* Restore MDR in case of LPDDR1 */
- ldr tmp1, .saved_sam9_mdr
- str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
- /* Restore LPR on AT91 with DDRAM */
- ldr tmp1, .saved_sam9_lpr
- str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-
- /* if we use the second ram controller */
- cmp ramc1, #0
- ldrne tmp2, .saved_sam9_mdr1
- strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
- ldrne tmp2, .saved_sam9_lpr1
- strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-
- b ram_restored
-
- /*
- * SDRAMC Memory controller
- */
-sdr_en_restore:
- /* Restore LPR on AT91 with SDRAM */
- ldr tmp1, .saved_sam9_lpr
- str tmp1, [sdramc, #AT91_SDRAMC_LPR]
-
-ram_restored:
- /* Restore registers, and return */
- ldmfd sp!, {r4 - r12, pc}
-
-
-.saved_mckr:
- .word 0
-
-.saved_pllar:
- .word 0
-
-.saved_sam9_lpr:
- .word 0
-
-.saved_sam9_lpr1:
- .word 0
-
-.saved_sam9_mdr:
- .word 0
-
-.saved_sam9_mdr1:
- .word 0
-
-ENTRY(at91_slow_clock_sz)
- .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
new file mode 100644
index 0000000..8edbad0
--- /dev/null
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -0,0 +1,281 @@
+/*
+ * arch/arm/mach-at91/pm_suspend.S
+ *
+ * Copyright (C) 2006 Savin Zlobec
+ *
+ * AT91SAM9 support:
+ * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/linkage.h>
+#include <linux/clk/at91_pmc.h>
+#include <mach/hardware.h>
+#include <mach/at91_ramc.h>
+
+#include "pm.h"
+
+pmc .req r0
+sdramc .req r1
+ramc1 .req r2
+memctrl .req r3
+tmp1 .req r4
+tmp2 .req r5
+mode .req r6
+
+/*
+ * Wait until master clock is ready (after switching master clock source)
+ */
+ .macro wait_mckrdy
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_MCKRDY
+ beq 1b
+ .endm
+
+/*
+ * Wait until master oscillator has stabilized.
+ */
+ .macro wait_moscrdy
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_MOSCS
+ beq 1b
+ .endm
+
+/*
+ * Wait until PLLA has locked.
+ */
+ .macro wait_pllalock
+1: ldr tmp1, [pmc, #AT91_PMC_SR]
+ tst tmp1, #AT91_PMC_LOCKA
+ beq 1b
+ .endm
+
+ .text
+
+/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+ * void __iomem *ramc1, int memctrl)
+ */
+ENTRY(at91_slow_clock)
+ /* Save registers on stack */
+ stmfd sp!, {r4 - r12, lr}
+
+ /*
+ * Register usage:
+ * R0 = Base address of AT91_PMC
+ * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+ * R2 = Base address of second RAM Controller or 0 if not present
+ * R3 = Memory controller
+ * R4 = temporary register
+ * R5 = temporary register
+ */
+
+ /* Drain write buffer */
+ mov tmp1, #0
+ mcr p15, 0, tmp1, c7, c10, 4
+
+ mov tmp1, memctrl
+ mov tmp2, tmp1, lsr#AT91_PM_MODE_OFFSET
+ and mode, tmp2, #AT91_PM_MODE_MASK
+
+ mov tmp1, memctrl
+ and memctrl, tmp1, #AT91_PM_MEMCTRL_MASK
+
+ cmp memctrl, #AT91_MEMCTRL_MC
+ bne ddr_sr_enable
+
+ /*
+ * at91rm9200 Memory controller
+ */
+ /* Put SDRAM in self-refresh mode */
+ mov tmp1, #1
+ str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
+ b sdr_sr_done
+
+ /*
+ * DDRSDR Memory controller
+ */
+ddr_sr_enable:
+ cmp memctrl, #AT91_MEMCTRL_DDRSDR
+ bne sdr_sr_enable
+
+ /* LPDDR1 --> force DDR2 mode during self-refresh */
+ ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ str tmp1, .saved_sam9_mdr
+ bic tmp1, tmp1, #~AT91_DDRSDRC_MD
+ cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ biceq tmp1, tmp1, #AT91_DDRSDRC_MD
+ orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
+ streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+
+ /* prepare for DDRAM self-refresh mode */
+ ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+ str tmp1, .saved_sam9_lpr
+ bic tmp1, #AT91_DDRSDRC_LPCB
+ orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+ /* figure out if we use the second ram controller */
+ cmp ramc1, #0
+ beq ddr_no_2nd_ctrl
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ str tmp2, .saved_sam9_mdr1
+ bic tmp2, tmp2, #~AT91_DDRSDRC_MD
+ cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
+ ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ biceq tmp2, tmp2, #AT91_DDRSDRC_MD
+ orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
+ streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+
+ ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ str tmp2, .saved_sam9_lpr1
+ bic tmp2, #AT91_DDRSDRC_LPCB
+ orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+
+ /* Enable DDRAM self-refresh mode */
+ str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+ddr_no_2nd_ctrl:
+ str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+
+ b sdr_sr_done
+
+ /*
+ * SDRAMC Memory controller
+ */
+sdr_sr_enable:
+ /* Enable SDRAM self-refresh mode */
+ ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
+ str tmp1, .saved_sam9_lpr
+
+ bic tmp1, #AT91_SDRAMC_LPCB
+ orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
+ str tmp1, [sdramc, #AT91_SDRAMC_LPR]
+
+sdr_sr_done:
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_disable_main_clock
+
+ /* Save Master clock setting */
+ ldr tmp1, [pmc, #AT91_PMC_MCKR]
+ str tmp1, .saved_mckr
+
+ /*
+ * Set the Master clock source to slow clock
+ */
+ bic tmp1, tmp1, #AT91_PMC_CSS
+ str tmp1, [pmc, #AT91_PMC_MCKR]
+
+ wait_mckrdy
+
+ /* Save PLLA setting and disable it */
+ ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
+ str tmp1, .saved_pllar
+
+ mov tmp1, #AT91_PMC_PLLCOUNT
+ orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
+ str tmp1, [pmc, #AT91_CKGR_PLLAR]
+
+ /* Turn off the main oscillator */
+ ldr tmp1, [pmc, #AT91_CKGR_MOR]
+ bic tmp1, tmp1, #AT91_PMC_MOSCEN
+ str tmp1, [pmc, #AT91_CKGR_MOR]
+
+skip_disable_main_clock:
+ /* Wait for interrupt */
+ mcr p15, 0, tmp1, c7, c0, 4
+
+ tst mode, #AT91_PM_SLOW_CLOCK
+ beq skip_enable_main_clock
+
+ /* Turn on the main oscillator */
+ ldr tmp1, [pmc, #AT91_CKGR_MOR]
+ orr tmp1, tmp1, #AT91_PMC_MOSCEN
+ str tmp1, [pmc, #AT91_CKGR_MOR]
+
+ wait_moscrdy
+
+ /* Restore PLLA setting */
+ ldr tmp1, .saved_pllar
+ str tmp1, [pmc, #AT91_CKGR_PLLAR]
+
+ tst tmp1, #(AT91_PMC_MUL & 0xff0000)
+ bne 3f
+ tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
+ beq 4f
+3:
+ wait_pllalock
+4:
+
+ /*
+ * Restore master clock setting
+ */
+2: ldr tmp1, .saved_mckr
+ str tmp1, [pmc, #AT91_PMC_MCKR]
+
+ wait_mckrdy
+
+skip_enable_main_clock:
+ /*
+ * at91rm9200 Memory controller
+ * Do nothing - self-refresh is automatically disabled.
+ */
+ cmp memctrl, #AT91_MEMCTRL_MC
+ beq ram_restored
+
+ /*
+ * DDRSDR Memory controller
+ */
+ cmp memctrl, #AT91_MEMCTRL_DDRSDR
+ bne sdr_en_restore
+ /* Restore MDR in case of LPDDR1 */
+ ldr tmp1, .saved_sam9_mdr
+ str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
+ /* Restore LPR on AT91 with DDRAM */
+ ldr tmp1, .saved_sam9_lpr
+ str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
+
+ /* if we use the second ram controller */
+ cmp ramc1, #0
+ ldrne tmp2, .saved_sam9_mdr1
+ strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
+ ldrne tmp2, .saved_sam9_lpr1
+ strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+
+ b ram_restored
+
+ /*
+ * SDRAMC Memory controller
+ */
+sdr_en_restore:
+ /* Restore LPR on AT91 with SDRAM */
+ ldr tmp1, .saved_sam9_lpr
+ str tmp1, [sdramc, #AT91_SDRAMC_LPR]
+
+ram_restored:
+ /* Restore registers, and return */
+ ldmfd sp!, {r4 - r12, pc}
+
+
+.saved_mckr:
+ .word 0
+
+.saved_pllar:
+ .word 0
+
+.saved_sam9_lpr:
+ .word 0
+
+.saved_sam9_lpr1:
+ .word 0
+
+.saved_sam9_mdr:
+ .word 0
+
+.saved_sam9_mdr1:
+ .word 0
+
+ENTRY(at91_slow_clock_sz)
+ .word .-at91_slow_clock
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 10/13] pm: at91: rename function name: at91_slow_clock()-->at91_pm_suspend_sram_fn
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 5:59 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:59 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
As the file name's renaming, rename the file name at91_slow_clock()-->
at91_pm_suspend_sram_fn, rename the function handler's name at the same time.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 27 +++++++++++++--------------
arch/arm/mach-at91/pm_suspend.S | 24 ++++++++++--------------
2 files changed, 23 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index d967c31..ab1a4d6 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -129,13 +129,12 @@ int at91_suspend_entering_slow_clock(void)
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
-
-static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
+static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
-extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
+extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
-extern u32 at91_slow_clock_sz;
+extern u32 at91_pm_suspend_in_sram_sz;
static void at91_pm_suspend(suspend_state_t state)
{
@@ -144,8 +143,8 @@ static void at91_pm_suspend(suspend_state_t state)
pm_data |= (state == PM_SUSPEND_MEM) ?
AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
- slow_clock(at91_pmc_base, at91_ramc_base[0],
- at91_ramc_base[1], pm_data);
+ at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
+ at91_ramc_base[1], pm_data);
}
static int at91_pm_enter(suspend_state_t state)
@@ -249,17 +248,19 @@ static void __init at91_pm_sram_init(void)
goto put_node;
}
- sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
+ sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
if (!sram_base) {
- pr_warn("%s: unable to alloc ocram!\n", __func__);
+ pr_warn("%s: unable to alloc sram!\n", __func__);
goto put_node;
}
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
- slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
+ at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
+ at91_pm_suspend_in_sram_sz, false);
- /* Copy the slow_clock handler to SRAM */
- memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+ /* Copy the pm suspend handler to SRAM */
+ memcpy(at91_suspend_sram_fn,
+ at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
put_node:
of_node_put(node);
@@ -269,12 +270,10 @@ static void __init at91_pm_init(void)
{
at91_pm_sram_init();
- pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
-
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
- if (slow_clock)
+ if (at91_suspend_sram_fn)
suspend_set_ops(&at91_pm_ops);
else
pr_info("AT91: PM : Not supported, due to no sram allocated\n");
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 8edbad0..122a3f1 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -55,23 +55,19 @@ mode .req r6
.text
-/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+/*
+ * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
* void __iomem *ramc1, int memctrl)
+ * @input param:
+ * @r0: the base address of AT91_PMC
+ * @r1: the base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+ * @r2: the base address of second SDRAM Controller or 0 if not present
+ * @r3: the pm information
*/
-ENTRY(at91_slow_clock)
+ENTRY(at91_pm_suspend_in_sram)
/* Save registers on stack */
stmfd sp!, {r4 - r12, lr}
- /*
- * Register usage:
- * R0 = Base address of AT91_PMC
- * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
- * R2 = Base address of second RAM Controller or 0 if not present
- * R3 = Memory controller
- * R4 = temporary register
- * R5 = temporary register
- */
-
/* Drain write buffer */
mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4
@@ -277,5 +273,5 @@ ram_restored:
.saved_sam9_mdr1:
.word 0
-ENTRY(at91_slow_clock_sz)
- .word .-at91_slow_clock
+ENTRY(at91_pm_suspend_in_sram_sz)
+ .word .-at91_pm_suspend_in_sram
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 10/13] pm: at91: rename function name: at91_slow_clock()-->at91_pm_suspend_sram_fn
@ 2015-01-27 5:59 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 5:59 UTC (permalink / raw)
To: linux-arm-kernel
As the file name's renaming, rename the file name at91_slow_clock()-->
at91_pm_suspend_sram_fn, rename the function handler's name at the same time.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 27 +++++++++++++--------------
arch/arm/mach-at91/pm_suspend.S | 24 ++++++++++--------------
2 files changed, 23 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index d967c31..ab1a4d6 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -129,13 +129,12 @@ int at91_suspend_entering_slow_clock(void)
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
-
-static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
+static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
-extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
+extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
void __iomem *ramc1, int memctrl);
-extern u32 at91_slow_clock_sz;
+extern u32 at91_pm_suspend_in_sram_sz;
static void at91_pm_suspend(suspend_state_t state)
{
@@ -144,8 +143,8 @@ static void at91_pm_suspend(suspend_state_t state)
pm_data |= (state == PM_SUSPEND_MEM) ?
AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
- slow_clock(at91_pmc_base, at91_ramc_base[0],
- at91_ramc_base[1], pm_data);
+ at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
+ at91_ramc_base[1], pm_data);
}
static int at91_pm_enter(suspend_state_t state)
@@ -249,17 +248,19 @@ static void __init at91_pm_sram_init(void)
goto put_node;
}
- sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
+ sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
if (!sram_base) {
- pr_warn("%s: unable to alloc ocram!\n", __func__);
+ pr_warn("%s: unable to alloc sram!\n", __func__);
goto put_node;
}
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
- slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
+ at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
+ at91_pm_suspend_in_sram_sz, false);
- /* Copy the slow_clock handler to SRAM */
- memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
+ /* Copy the pm suspend handler to SRAM */
+ memcpy(at91_suspend_sram_fn,
+ at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
put_node:
of_node_put(node);
@@ -269,12 +270,10 @@ static void __init at91_pm_init(void)
{
at91_pm_sram_init();
- pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
-
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
- if (slow_clock)
+ if (at91_suspend_sram_fn)
suspend_set_ops(&at91_pm_ops);
else
pr_info("AT91: PM : Not supported, due to no sram allocated\n");
diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
index 8edbad0..122a3f1 100644
--- a/arch/arm/mach-at91/pm_suspend.S
+++ b/arch/arm/mach-at91/pm_suspend.S
@@ -55,23 +55,19 @@ mode .req r6
.text
-/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+/*
+ * void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *sdramc,
* void __iomem *ramc1, int memctrl)
+ * @input param:
+ * @r0: the base address of AT91_PMC
+ * @r1: the base address of SDRAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+ * @r2: the base address of second SDRAM Controller or 0 if not present
+ * @r3: the pm information
*/
-ENTRY(at91_slow_clock)
+ENTRY(at91_pm_suspend_in_sram)
/* Save registers on stack */
stmfd sp!, {r4 - r12, lr}
- /*
- * Register usage:
- * R0 = Base address of AT91_PMC
- * R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
- * R2 = Base address of second RAM Controller or 0 if not present
- * R3 = Memory controller
- * R4 = temporary register
- * R5 = temporary register
- */
-
/* Drain write buffer */
mov tmp1, #0
mcr p15, 0, tmp1, c7, c10, 4
@@ -277,5 +273,5 @@ ram_restored:
.saved_sam9_mdr1:
.word 0
-ENTRY(at91_slow_clock_sz)
- .word .-at91_slow_clock
+ENTRY(at91_pm_suspend_in_sram_sz)
+ .word .-at91_pm_suspend_in_sram
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 11/13] pm: at91: remove the at91_xxx_standby() function definitions in the pm.h
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 6:00 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 6:00 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
Because the the suspend to standby mode uses the sram function,
these functions will not used, remove the redundant code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.h | 97 -----------------------------------------------
1 file changed, 97 deletions(-)
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 5bc9c33..158575e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -12,7 +12,6 @@
#define __ARCH_ARM_MACH_AT91_PM
#include <asm/proc-fns.h>
-
#include <mach/at91_ramc.h>
#define AT91_PM_MEMCTRL_MASK 0x0f
@@ -22,100 +21,4 @@
#define AT91_PM_SLOW_CLOCK 0x01
-#ifdef CONFIG_PM
-extern void at91_pm_set_standby(void (*at91_standby)(void));
-#else
-static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
-#endif
-
-/*
- * The AT91RM9200 goes into self-refresh mode with this command, and will
- * terminate self-refresh automatically on the next SDRAM access.
- *
- * Self-refresh mode is exited as soon as a memory access is made, but we don't
- * know for sure when that happens. However, we need to restore the low-power
- * mode if it was enabled before going idle. Restoring low-power mode while
- * still in self-refresh is "not recommended", but seems to work.
- */
-
-static inline void at91rm9200_standby(void)
-{
- u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
-
- asm volatile(
- "b 1f\n\t"
- ".align 5\n\t"
- "1: mcr p15, 0, %0, c7, c10, 4\n\t"
- " str %0, [%1, %2]\n\t"
- " str %3, [%1, %4]\n\t"
- " mcr p15, 0, %0, c7, c0, 4\n\t"
- " str %5, [%1, %2]"
- :
- : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
- "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
- "r" (lpr));
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91_ddr_standby(void)
-{
- /* Those two values allow us to delay self-refresh activation
- * to the maximum. */
- u32 lpr0, lpr1 = 0;
- u32 saved_lpr0, saved_lpr1 = 0;
-
- if (at91_ramc_base[1]) {
- saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
- lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
- lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
- }
-
- saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
- lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
- lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-
- /* self-refresh mode now */
- at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
-
- cpu_do_idle();
-
- at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91sam9_sdram_standby(void)
-{
- u32 lpr0, lpr1 = 0;
- u32 saved_lpr0, saved_lpr1 = 0;
-
- if (at91_ramc_base[1]) {
- saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
- lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
- lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
- }
-
- saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
- lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
- lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
-
- /* self-refresh mode now */
- at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
-
- cpu_do_idle();
-
- at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
-}
-
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 11/13] pm: at91: remove the at91_xxx_standby() function definitions in the pm.h
@ 2015-01-27 6:00 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 6:00 UTC (permalink / raw)
To: linux-arm-kernel
Because the the suspend to standby mode uses the sram function,
these functions will not used, remove the redundant code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.h | 97 -----------------------------------------------
1 file changed, 97 deletions(-)
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 5bc9c33..158575e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -12,7 +12,6 @@
#define __ARCH_ARM_MACH_AT91_PM
#include <asm/proc-fns.h>
-
#include <mach/at91_ramc.h>
#define AT91_PM_MEMCTRL_MASK 0x0f
@@ -22,100 +21,4 @@
#define AT91_PM_SLOW_CLOCK 0x01
-#ifdef CONFIG_PM
-extern void at91_pm_set_standby(void (*at91_standby)(void));
-#else
-static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
-#endif
-
-/*
- * The AT91RM9200 goes into self-refresh mode with this command, and will
- * terminate self-refresh automatically on the next SDRAM access.
- *
- * Self-refresh mode is exited as soon as a memory access is made, but we don't
- * know for sure when that happens. However, we need to restore the low-power
- * mode if it was enabled before going idle. Restoring low-power mode while
- * still in self-refresh is "not recommended", but seems to work.
- */
-
-static inline void at91rm9200_standby(void)
-{
- u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
-
- asm volatile(
- "b 1f\n\t"
- ".align 5\n\t"
- "1: mcr p15, 0, %0, c7, c10, 4\n\t"
- " str %0, [%1, %2]\n\t"
- " str %3, [%1, %4]\n\t"
- " mcr p15, 0, %0, c7, c0, 4\n\t"
- " str %5, [%1, %2]"
- :
- : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
- "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
- "r" (lpr));
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91_ddr_standby(void)
-{
- /* Those two values allow us to delay self-refresh activation
- * to the maximum. */
- u32 lpr0, lpr1 = 0;
- u32 saved_lpr0, saved_lpr1 = 0;
-
- if (at91_ramc_base[1]) {
- saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
- lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
- lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
- }
-
- saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
- lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
- lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
-
- /* self-refresh mode now */
- at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
-
- cpu_do_idle();
-
- at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
-}
-
-/* We manage both DDRAM/SDRAM controllers, we need more than one value to
- * remember.
- */
-static inline void at91sam9_sdram_standby(void)
-{
- u32 lpr0, lpr1 = 0;
- u32 saved_lpr0, saved_lpr1 = 0;
-
- if (at91_ramc_base[1]) {
- saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
- lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
- lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
- }
-
- saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
- lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
- lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
-
- /* self-refresh mode now */
- at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
-
- cpu_do_idle();
-
- at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
- if (at91_ramc_base[1])
- at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
-}
-
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 12/13] pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby members
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 6:01 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 6:01 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
Because the at91_xxx_standby function is removed,
remove the struct ramc_ids .data members code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/setup.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4c18428..b8dba9f 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -362,10 +362,10 @@ void __init at91_ioremap_matrix(u32 base_addr)
}
static struct of_device_id ramc_ids[] = {
- { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
- { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
- { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
- { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
+ { .compatible = "atmel,at91rm9200-sdramc" },
+ { .compatible = "atmel,at91sam9260-sdramc" },
+ { .compatible = "atmel,at91sam9g45-ddramc" },
+ { .compatible = "atmel,sama5d3-ddramc" },
{ /*sentinel*/ }
};
@@ -374,28 +374,17 @@ static void at91_dt_ramc(void)
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
- const void *standby = NULL;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
at91_ramc_base[idx] = of_iomap(np, 0);
if (!at91_ramc_base[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
- if (!standby)
- standby = of_id->data;
-
idx++;
}
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
-
- if (!standby) {
- pr_warn("ramc no standby function available\n");
- return;
- }
-
- at91_pm_set_standby(standby);
}
void __init at91_dt_initialize(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 12/13] pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby members
@ 2015-01-27 6:01 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Because the at91_xxx_standby function is removed,
remove the struct ramc_ids .data members code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/setup.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4c18428..b8dba9f 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -362,10 +362,10 @@ void __init at91_ioremap_matrix(u32 base_addr)
}
static struct of_device_id ramc_ids[] = {
- { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
- { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
- { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
- { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
+ { .compatible = "atmel,at91rm9200-sdramc" },
+ { .compatible = "atmel,at91sam9260-sdramc" },
+ { .compatible = "atmel,at91sam9g45-ddramc" },
+ { .compatible = "atmel,sama5d3-ddramc" },
{ /*sentinel*/ }
};
@@ -374,28 +374,17 @@ static void at91_dt_ramc(void)
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
- const void *standby = NULL;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
at91_ramc_base[idx] = of_iomap(np, 0);
if (!at91_ramc_base[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
- if (!standby)
- standby = of_id->data;
-
idx++;
}
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
-
- if (!standby) {
- pr_warn("ramc no standby function available\n");
- return;
- }
-
- at91_pm_set_standby(standby);
}
void __init at91_dt_initialize(void)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 13/13] pm: at91: amend the pm_suspend entry for at91_cpuidle_device
2015-01-27 5:50 ` Wenyou Yang
@ 2015-01-27 6:01 ` Wenyou Yang
-1 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 6:01 UTC (permalink / raw)
To: nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, sergei.shtylyov, linux, wenyou.yang
Because the at91_xxx_standby() function is substitued by the at91_pm_suspend(),
the pm_suspend entry for at91_cpuidle_device changes as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index ab1a4d6..faa5d30 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -40,8 +40,6 @@ static struct {
int memctrl;
} at91_pm_data;
-static void (*at91_pm_standby)(void);
-
static int at91_pm_valid_state(suspend_state_t state)
{
switch (state) {
@@ -214,12 +212,15 @@ static struct platform_device at91_cpuidle_device = {
.name = "cpuidle-at91",
};
-void at91_pm_set_standby(void (*at91_standby)(void))
+static void at91_cpuidle_suspend(void)
{
- if (at91_standby) {
- at91_cpuidle_device.dev.platform_data = at91_standby;
- at91_pm_standby = at91_standby;
- }
+ at91_pm_suspend(PM_SUSPEND_STANDBY);
+}
+
+static void at91_cpuidle_set_suspend(void (*at91_suspend)(void))
+{
+ if (at91_suspend)
+ at91_cpuidle_device.dev.platform_data = at91_suspend;
}
static void __init at91_pm_sram_init(void)
@@ -270,6 +271,8 @@ static void __init at91_pm_init(void)
{
at91_pm_sram_init();
+ at91_cpuidle_set_suspend(at91_cpuidle_suspend);
+
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v3 13/13] pm: at91: amend the pm_suspend entry for at91_cpuidle_device
@ 2015-01-27 6:01 ` Wenyou Yang
0 siblings, 0 replies; 46+ messages in thread
From: Wenyou Yang @ 2015-01-27 6:01 UTC (permalink / raw)
To: linux-arm-kernel
Because the at91_xxx_standby() function is substitued by the at91_pm_suspend(),
the pm_suspend entry for at91_cpuidle_device changes as well.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
---
arch/arm/mach-at91/pm.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index ab1a4d6..faa5d30 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -40,8 +40,6 @@ static struct {
int memctrl;
} at91_pm_data;
-static void (*at91_pm_standby)(void);
-
static int at91_pm_valid_state(suspend_state_t state)
{
switch (state) {
@@ -214,12 +212,15 @@ static struct platform_device at91_cpuidle_device = {
.name = "cpuidle-at91",
};
-void at91_pm_set_standby(void (*at91_standby)(void))
+static void at91_cpuidle_suspend(void)
{
- if (at91_standby) {
- at91_cpuidle_device.dev.platform_data = at91_standby;
- at91_pm_standby = at91_standby;
- }
+ at91_pm_suspend(PM_SUSPEND_STANDBY);
+}
+
+static void at91_cpuidle_set_suspend(void (*at91_suspend)(void))
+{
+ if (at91_suspend)
+ at91_cpuidle_device.dev.platform_data = at91_suspend;
}
static void __init at91_pm_sram_init(void)
@@ -270,6 +271,8 @@ static void __init at91_pm_init(void)
{
at91_pm_sram_init();
+ at91_cpuidle_set_suspend(at91_cpuidle_suspend);
+
if (at91_cpuidle_device.dev.platform_data)
platform_device_register(&at91_cpuidle_device);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 46+ messages in thread
* Re: [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
2015-01-27 5:57 ` Wenyou Yang
@ 2015-01-27 9:55 ` Sylvain Rochet
-1 siblings, 0 replies; 46+ messages in thread
From: Sylvain Rochet @ 2015-01-27 9:55 UTC (permalink / raw)
To: Wenyou Yang
Cc: nicolas.ferre, linux, linux-arm-kernel, linux-kernel,
alexandre.belloni, peda, sergei.shtylyov, linux
Hello Wenyou,
On Tue, Jan 27, 2015 at 01:57:27PM +0800, Wenyou Yang wrote:
>
> static void __init at91_pm_init(void)
> {
> -#ifdef CONFIG_AT91_SLOW_CLOCK
> at91_pm_sram_init();
> -#endif
>
> pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
Details, but the ternary operation can be removed here, slow_clock now
defines whether we have PM support at all, not whether we have
slow_clock mode available.
Maybe we should not even display this message on the console if we
failed to allocate sram for slow_clock, we already fired a message
saying that PM is not available at all in at91_pm_sram_init().
Sylvain
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
@ 2015-01-27 9:55 ` Sylvain Rochet
0 siblings, 0 replies; 46+ messages in thread
From: Sylvain Rochet @ 2015-01-27 9:55 UTC (permalink / raw)
To: linux-arm-kernel
Hello Wenyou,
On Tue, Jan 27, 2015 at 01:57:27PM +0800, Wenyou Yang wrote:
>
> static void __init at91_pm_init(void)
> {
> -#ifdef CONFIG_AT91_SLOW_CLOCK
> at91_pm_sram_init();
> -#endif
>
> pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
Details, but the ternary operation can be removed here, slow_clock now
defines whether we have PM support at all, not whether we have
slow_clock mode available.
Maybe we should not even display this message on the console if we
failed to allocate sram for slow_clock, we already fired a message
saying that PM is not available at all in at91_pm_sram_init().
Sylvain
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
2015-01-27 9:55 ` Sylvain Rochet
@ 2015-01-27 10:07 ` Alexandre Belloni
-1 siblings, 0 replies; 46+ messages in thread
From: Alexandre Belloni @ 2015-01-27 10:07 UTC (permalink / raw)
To: Sylvain Rochet
Cc: Wenyou Yang, nicolas.ferre, linux, linux-arm-kernel,
linux-kernel, peda, sergei.shtylyov, linux
Hi,
On 27/01/2015 at 10:55:15 +0100, Sylvain Rochet wrote :
> Hello Wenyou,
>
> On Tue, Jan 27, 2015 at 01:57:27PM +0800, Wenyou Yang wrote:
> >
> > static void __init at91_pm_init(void)
> > {
> > -#ifdef CONFIG_AT91_SLOW_CLOCK
> > at91_pm_sram_init();
> > -#endif
> >
> > pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
>
> Details, but the ternary operation can be removed here, slow_clock now
> defines whether we have PM support at all, not whether we have
> slow_clock mode available.
>
> Maybe we should not even display this message on the console if we
> failed to allocate sram for slow_clock, we already fired a message
> saying that PM is not available at all in at91_pm_sram_init().
>
That is done in patch 10/13.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
@ 2015-01-27 10:07 ` Alexandre Belloni
0 siblings, 0 replies; 46+ messages in thread
From: Alexandre Belloni @ 2015-01-27 10:07 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 27/01/2015 at 10:55:15 +0100, Sylvain Rochet wrote :
> Hello Wenyou,
>
> On Tue, Jan 27, 2015 at 01:57:27PM +0800, Wenyou Yang wrote:
> >
> > static void __init at91_pm_init(void)
> > {
> > -#ifdef CONFIG_AT91_SLOW_CLOCK
> > at91_pm_sram_init();
> > -#endif
> >
> > pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
>
> Details, but the ternary operation can be removed here, slow_clock now
> defines whether we have PM support at all, not whether we have
> slow_clock mode available.
>
> Maybe we should not even display this message on the console if we
> failed to allocate sram for slow_clock, we already fired a message
> saying that PM is not available at all in at91_pm_sram_init().
>
That is done in patch 10/13.
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode
2015-01-27 5:58 ` Wenyou Yang
@ 2015-01-27 10:08 ` Sylvain Rochet
-1 siblings, 0 replies; 46+ messages in thread
From: Sylvain Rochet @ 2015-01-27 10:08 UTC (permalink / raw)
To: Wenyou Yang
Cc: nicolas.ferre, linux, linux-arm-kernel, linux-kernel,
alexandre.belloni, peda, sergei.shtylyov, linux
Hello Wenyou,
On Tue, Jan 27, 2015 at 01:58:20PM +0800, Wenyou Yang wrote:
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 0377c0d..d967c31 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -71,7 +71,7 @@ static int at91_pm_begin(suspend_state_t state)
> * Verify that all the clocks are correct before entering
> * slow-clock mode.
> */
> -static int at91_pm_verify_clocks(void)
> +static int at91_pm_verify_clocks(suspend_state_t state)
> {
> unsigned long scsr;
> int i;
> @@ (...)
Unused state argument, it was added in v2, this is just a trace of a
reverted v2 change not fully cleaned.
> + if (!at91_pm_verify_clocks(state))
> + goto error;
Ditto.
Sylvain
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode
@ 2015-01-27 10:08 ` Sylvain Rochet
0 siblings, 0 replies; 46+ messages in thread
From: Sylvain Rochet @ 2015-01-27 10:08 UTC (permalink / raw)
To: linux-arm-kernel
Hello Wenyou,
On Tue, Jan 27, 2015 at 01:58:20PM +0800, Wenyou Yang wrote:
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 0377c0d..d967c31 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -71,7 +71,7 @@ static int at91_pm_begin(suspend_state_t state)
> * Verify that all the clocks are correct before entering
> * slow-clock mode.
> */
> -static int at91_pm_verify_clocks(void)
> +static int at91_pm_verify_clocks(suspend_state_t state)
> {
> unsigned long scsr;
> int i;
> @@ (...)
Unused state argument, it was added in v2, this is just a trace of a
reverted v2 change not fully cleaned.
> + if (!at91_pm_verify_clocks(state))
> + goto error;
Ditto.
Sylvain
^ permalink raw reply [flat|nested] 46+ messages in thread
* RE: [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode
2015-01-27 10:08 ` Sylvain Rochet
@ 2015-01-27 10:11 ` Yang, Wenyou
-1 siblings, 0 replies; 46+ messages in thread
From: Yang, Wenyou @ 2015-01-27 10:11 UTC (permalink / raw)
To: Sylvain Rochet
Cc: Ferre, Nicolas, linux, linux-arm-kernel, linux-kernel,
alexandre.belloni, peda, sergei.shtylyov, linux
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1528 bytes --]
Hi Sylvain,
Thanks a lot.
> -----Original Message-----
> From: Sylvain Rochet [mailto:sylvain.rochet@finsecur.com]
> Sent: Tuesday, January 27, 2015 6:08 PM
> To: Yang, Wenyou
> Cc: Ferre, Nicolas; linux@arm.linux.org.uk; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; alexandre.belloni@free-electrons.com;
> peda@axentia.se; sergei.shtylyov@cogentembedded.com; linux@maxim.org.za
> Subject: Re: [PATCH v3 08/13] pm: at91: the standby mode uses the same sram
> function as the suspend to memory mode
>
> Hello Wenyou,
>
> On Tue, Jan 27, 2015 at 01:58:20PM +0800, Wenyou Yang wrote:
> >
> > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index
> > 0377c0d..d967c31 100644
> > --- a/arch/arm/mach-at91/pm.c
> > +++ b/arch/arm/mach-at91/pm.c
> > @@ -71,7 +71,7 @@ static int at91_pm_begin(suspend_state_t state)
> > * Verify that all the clocks are correct before entering
> > * slow-clock mode.
> > */
> > -static int at91_pm_verify_clocks(void)
> > +static int at91_pm_verify_clocks(suspend_state_t state)
> > {
> > unsigned long scsr;
> > int i;
> > @@ (...)
>
> Unused state argument, it was added in v2, this is just a trace of a reverted v2
> change not fully cleaned.
Yes, not clear.
>
>
> > + if (!at91_pm_verify_clocks(state))
> > + goto error;
>
> Ditto.
>
>
> Sylvain
Best Regards,
Wenyou Yang
ÿôèº{.nÇ+‰·Ÿ®‰†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a¢f£¢·hšïêÿ‘êçz_è®\x03(階ŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨èÚ&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode
@ 2015-01-27 10:11 ` Yang, Wenyou
0 siblings, 0 replies; 46+ messages in thread
From: Yang, Wenyou @ 2015-01-27 10:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sylvain,
Thanks a lot.
> -----Original Message-----
> From: Sylvain Rochet [mailto:sylvain.rochet at finsecur.com]
> Sent: Tuesday, January 27, 2015 6:08 PM
> To: Yang, Wenyou
> Cc: Ferre, Nicolas; linux at arm.linux.org.uk; linux-arm-kernel at lists.infradead.org;
> linux-kernel at vger.kernel.org; alexandre.belloni at free-electrons.com;
> peda at axentia.se; sergei.shtylyov at cogentembedded.com; linux at maxim.org.za
> Subject: Re: [PATCH v3 08/13] pm: at91: the standby mode uses the same sram
> function as the suspend to memory mode
>
> Hello Wenyou,
>
> On Tue, Jan 27, 2015 at 01:58:20PM +0800, Wenyou Yang wrote:
> >
> > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index
> > 0377c0d..d967c31 100644
> > --- a/arch/arm/mach-at91/pm.c
> > +++ b/arch/arm/mach-at91/pm.c
> > @@ -71,7 +71,7 @@ static int at91_pm_begin(suspend_state_t state)
> > * Verify that all the clocks are correct before entering
> > * slow-clock mode.
> > */
> > -static int at91_pm_verify_clocks(void)
> > +static int at91_pm_verify_clocks(suspend_state_t state)
> > {
> > unsigned long scsr;
> > int i;
> > @@ (...)
>
> Unused state argument, it was added in v2, this is just a trace of a reverted v2
> change not fully cleaned.
Yes, not clear.
>
>
> > + if (!at91_pm_verify_clocks(state))
> > + goto error;
>
> Ditto.
>
>
> Sylvain
Best Regards,
Wenyou Yang
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
2015-01-27 10:07 ` Alexandre Belloni
@ 2015-01-27 10:13 ` Sylvain Rochet
-1 siblings, 0 replies; 46+ messages in thread
From: Sylvain Rochet @ 2015-01-27 10:13 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Wenyou Yang, nicolas.ferre, linux, linux-arm-kernel,
linux-kernel, peda, sergei.shtylyov, linux
Hi,
On Tue, Jan 27, 2015 at 11:07:42AM +0100, Alexandre Belloni wrote:
> Hi,
>
> On 27/01/2015 at 10:55:15 +0100, Sylvain Rochet wrote :
> > Hello Wenyou,
> >
> > On Tue, Jan 27, 2015 at 01:57:27PM +0800, Wenyou Yang wrote:
> > >
> > > static void __init at91_pm_init(void)
> > > {
> > > -#ifdef CONFIG_AT91_SLOW_CLOCK
> > > at91_pm_sram_init();
> > > -#endif
> > >
> > > pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
> >
> > Details, but the ternary operation can be removed here, slow_clock now
> > defines whether we have PM support at all, not whether we have
> > slow_clock mode available.
> >
> > Maybe we should not even display this message on the console if we
> > failed to allocate sram for slow_clock, we already fired a message
> > saying that PM is not available at all in at91_pm_sram_init().
>
> That is done in patch 10/13.
Indeed… I missed that because 10/13 is a rename patch, this should be
done here IMHO :)
Sylvain
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK
@ 2015-01-27 10:13 ` Sylvain Rochet
0 siblings, 0 replies; 46+ messages in thread
From: Sylvain Rochet @ 2015-01-27 10:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On Tue, Jan 27, 2015 at 11:07:42AM +0100, Alexandre Belloni wrote:
> Hi,
>
> On 27/01/2015 at 10:55:15 +0100, Sylvain Rochet wrote :
> > Hello Wenyou,
> >
> > On Tue, Jan 27, 2015 at 01:57:27PM +0800, Wenyou Yang wrote:
> > >
> > > static void __init at91_pm_init(void)
> > > {
> > > -#ifdef CONFIG_AT91_SLOW_CLOCK
> > > at91_pm_sram_init();
> > > -#endif
> > >
> > > pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
> >
> > Details, but the ternary operation can be removed here, slow_clock now
> > defines whether we have PM support at all, not whether we have
> > slow_clock mode available.
> >
> > Maybe we should not even display this message on the console if we
> > failed to allocate sram for slow_clock, we already fired a message
> > saying that PM is not available at all in at91_pm_sram_init().
>
> That is done in patch 10/13.
Indeed? I missed that because 10/13 is a rename patch, this should be
done here IMHO :)
Sylvain
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
2015-01-27 5:53 ` Wenyou Yang
@ 2015-01-27 10:24 ` Sergei Shtylyov
-1 siblings, 0 replies; 46+ messages in thread
From: Sergei Shtylyov @ 2015-01-27 10:24 UTC (permalink / raw)
To: Wenyou Yang, nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni,
sylvain.rochet, peda, linux
Hello.
On 1/27/2015 8:53 AM, Wenyou Yang wrote:
> From: Peter Rosin <peda@axentia.se>
> The DDRSDR controller fails miserably to put LPDDR1 memories in
> self-refresh. Force the controller to think it has DDR2 memories
> during the self-refresh period, as the DDR2 self-refresh spec is
> equivalent to LPDDR1, and is correctly implemented in the
> controller.
> Assume that the second controller has the same fault, but that is
> untested.
> Signed-off-by: Peter Rosin <peda@axentia.se>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/pm_slowclock.S | 43 +++++++++++++++++++++++++++++++-----
> include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> 2 files changed, 39 insertions(+), 6 deletions(-)
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index e2bfaf5..1155217 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
[...]
> @@ -108,14 +118,26 @@ ddr_sr_enable:
>
> /* figure out if we use the second ram controller */
> cmp ramc1, #0
> - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> - strne tmp2, .saved_sam9_lpr1
> - bicne tmp2, #AT91_DDRSDRC_LPCB
> - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> + beq ddr_no_2nd_ctrl
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + str tmp2, .saved_sam9_mdr1
> + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
Didn't you forget ~? Either that, or ~ above is not needed, I think.
> + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> + str tmp2, .saved_sam9_lpr1
> + bic tmp2, #AT91_DDRSDRC_LPCB
Didn't you forget ~? And isn't it 3-operand instruction (as seen in the
above code)?
> + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
Only 2 operands?
[...]
WBR, Sergei
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
@ 2015-01-27 10:24 ` Sergei Shtylyov
0 siblings, 0 replies; 46+ messages in thread
From: Sergei Shtylyov @ 2015-01-27 10:24 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
On 1/27/2015 8:53 AM, Wenyou Yang wrote:
> From: Peter Rosin <peda@axentia.se>
> The DDRSDR controller fails miserably to put LPDDR1 memories in
> self-refresh. Force the controller to think it has DDR2 memories
> during the self-refresh period, as the DDR2 self-refresh spec is
> equivalent to LPDDR1, and is correctly implemented in the
> controller.
> Assume that the second controller has the same fault, but that is
> untested.
> Signed-off-by: Peter Rosin <peda@axentia.se>
> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> ---
> arch/arm/mach-at91/pm_slowclock.S | 43 +++++++++++++++++++++++++++++++-----
> include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> 2 files changed, 39 insertions(+), 6 deletions(-)
> diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
> index e2bfaf5..1155217 100644
> --- a/arch/arm/mach-at91/pm_slowclock.S
> +++ b/arch/arm/mach-at91/pm_slowclock.S
[...]
> @@ -108,14 +118,26 @@ ddr_sr_enable:
>
> /* figure out if we use the second ram controller */
> cmp ramc1, #0
> - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> - strne tmp2, .saved_sam9_lpr1
> - bicne tmp2, #AT91_DDRSDRC_LPCB
> - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> + beq ddr_no_2nd_ctrl
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + str tmp2, .saved_sam9_mdr1
> + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
Didn't you forget ~? Either that, or ~ above is not needed, I think.
> + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> +
> + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> + str tmp2, .saved_sam9_lpr1
> + bic tmp2, #AT91_DDRSDRC_LPCB
Didn't you forget ~? And isn't it 3-operand instruction (as seen in the
above code)?
> + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
Only 2 operands?
[...]
WBR, Sergei
^ permalink raw reply [flat|nested] 46+ messages in thread
* RE: [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
2015-01-27 10:24 ` Sergei Shtylyov
@ 2015-01-27 12:14 ` Peter Rosin
-1 siblings, 0 replies; 46+ messages in thread
From: Peter Rosin @ 2015-01-27 12:14 UTC (permalink / raw)
To: Sergei Shtylyov, Wenyou Yang, nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni, sylvain.rochet, linux
Sergei Shtylyov wrote:
> Hello.
Hi!
> On 1/27/2015 8:53 AM, Wenyou Yang wrote:
>
> > From: Peter Rosin <peda@axentia.se>
>
> > The DDRSDR controller fails miserably to put LPDDR1 memories in
> > self-refresh. Force the controller to think it has DDR2 memories
> > during the self-refresh period, as the DDR2 self-refresh spec is
> > equivalent to LPDDR1, and is correctly implemented in the controller.
>
> > Assume that the second controller has the same fault, but that is
> > untested.
>
> > Signed-off-by: Peter Rosin <peda@axentia.se>
> > Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> > ---
> > arch/arm/mach-at91/pm_slowclock.S | 43
> +++++++++++++++++++++++++++++++-----
> > include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> > 2 files changed, 39 insertions(+), 6 deletions(-)
>
> > diff --git a/arch/arm/mach-at91/pm_slowclock.S
> > b/arch/arm/mach-at91/pm_slowclock.S
> > index e2bfaf5..1155217 100644
> > --- a/arch/arm/mach-at91/pm_slowclock.S
> > +++ b/arch/arm/mach-at91/pm_slowclock.S
> [...]
> > @@ -108,14 +118,26 @@ ddr_sr_enable:
> >
> > /* figure out if we use the second ram controller */
> > cmp ramc1, #0
> > - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > - strne tmp2, .saved_sam9_lpr1
> > - bicne tmp2, #AT91_DDRSDRC_LPCB
> > - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> > + beq ddr_no_2nd_ctrl
> > +
> > + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > + str tmp2, .saved_sam9_mdr1
> > + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> > + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> > + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
>
> Didn't you forget ~? Either that, or ~ above is not needed, I think.
The code is correct, the first bic with ~ clears bits not in the relevant
field in order to compare if LPDDR mode is active. The second bic(eq)
w/o ~ clears the field, to make way for the bits in the below orreq
when actually changing the register content into DDR2 mode.
> > + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> > + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > +
> > + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > + str tmp2, .saved_sam9_lpr1
> > + bic tmp2, #AT91_DDRSDRC_LPCB
>
> Didn't you forget ~? And isn't it 3-operand instruction (as seen in the above
> code)?
The logic for the LPR register is from the old code, the "only" thing
I did to it was changing the instruction sequence to not have the
???ne form, i.e. ldrne, strne, bicne, orrne became ldr, str, bic, orr
with a jump around it instead. So, the original code also had a two
argument bic(ne), which indeed is strange, and I don't know why
there is no warning from the assembler. Since there is no warning,
my guess is that the assembler somehow mends it? Or does the
patch actually break the second controller? It would be a surprise
it the assembler handles 2-operand bicne differently from a
2-operand bic, no?
> > + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
>
> Only 2 operands?
Same argument as above. I didn't touch it (sort of...)
Should I update the patch and fix this collateral 2-operand problem as
well? To me, it feels like a separate patch, no?
> [...]
>
> WBR, Sergei
Cheers,
Peter
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
@ 2015-01-27 12:14 ` Peter Rosin
0 siblings, 0 replies; 46+ messages in thread
From: Peter Rosin @ 2015-01-27 12:14 UTC (permalink / raw)
To: linux-arm-kernel
Sergei Shtylyov wrote:
> Hello.
Hi!
> On 1/27/2015 8:53 AM, Wenyou Yang wrote:
>
> > From: Peter Rosin <peda@axentia.se>
>
> > The DDRSDR controller fails miserably to put LPDDR1 memories in
> > self-refresh. Force the controller to think it has DDR2 memories
> > during the self-refresh period, as the DDR2 self-refresh spec is
> > equivalent to LPDDR1, and is correctly implemented in the controller.
>
> > Assume that the second controller has the same fault, but that is
> > untested.
>
> > Signed-off-by: Peter Rosin <peda@axentia.se>
> > Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> > ---
> > arch/arm/mach-at91/pm_slowclock.S | 43
> +++++++++++++++++++++++++++++++-----
> > include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> > 2 files changed, 39 insertions(+), 6 deletions(-)
>
> > diff --git a/arch/arm/mach-at91/pm_slowclock.S
> > b/arch/arm/mach-at91/pm_slowclock.S
> > index e2bfaf5..1155217 100644
> > --- a/arch/arm/mach-at91/pm_slowclock.S
> > +++ b/arch/arm/mach-at91/pm_slowclock.S
> [...]
> > @@ -108,14 +118,26 @@ ddr_sr_enable:
> >
> > /* figure out if we use the second ram controller */
> > cmp ramc1, #0
> > - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > - strne tmp2, .saved_sam9_lpr1
> > - bicne tmp2, #AT91_DDRSDRC_LPCB
> > - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> > + beq ddr_no_2nd_ctrl
> > +
> > + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > + str tmp2, .saved_sam9_mdr1
> > + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> > + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> > + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
>
> Didn't you forget ~? Either that, or ~ above is not needed, I think.
The code is correct, the first bic with ~ clears bits not in the relevant
field in order to compare if LPDDR mode is active. The second bic(eq)
w/o ~ clears the field, to make way for the bits in the below orreq
when actually changing the register content into DDR2 mode.
> > + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> > + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > +
> > + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > + str tmp2, .saved_sam9_lpr1
> > + bic tmp2, #AT91_DDRSDRC_LPCB
>
> Didn't you forget ~? And isn't it 3-operand instruction (as seen in the above
> code)?
The logic for the LPR register is from the old code, the "only" thing
I did to it was changing the instruction sequence to not have the
???ne form, i.e. ldrne, strne, bicne, orrne became ldr, str, bic, orr
with a jump around it instead. So, the original code also had a two
argument bic(ne), which indeed is strange, and I don't know why
there is no warning from the assembler. Since there is no warning,
my guess is that the assembler somehow mends it? Or does the
patch actually break the second controller? It would be a surprise
it the assembler handles 2-operand bicne differently from a
2-operand bic, no?
> > + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
>
> Only 2 operands?
Same argument as above. I didn't touch it (sort of...)
Should I update the patch and fix this collateral 2-operand problem as
well? To me, it feels like a separate patch, no?
> [...]
>
> WBR, Sergei
Cheers,
Peter
^ permalink raw reply [flat|nested] 46+ messages in thread
* RE: [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
2015-01-27 10:24 ` Sergei Shtylyov
@ 2015-01-27 21:55 ` Peter Rosin
-1 siblings, 0 replies; 46+ messages in thread
From: Peter Rosin @ 2015-01-27 21:55 UTC (permalink / raw)
To: Sergei Shtylyov, Wenyou Yang, nicolas.ferre, linux
Cc: linux-arm-kernel, linux-kernel, alexandre.belloni, sylvain.rochet, linux
I wrote:
> Sergei Shtylyov wrote:
> > On 1/27/2015 8:53 AM, Wenyou Yang wrote:
> >
> > > From: Peter Rosin <peda@axentia.se>
> >
> > > The DDRSDR controller fails miserably to put LPDDR1 memories in
> > > self-refresh. Force the controller to think it has DDR2 memories
> > > during the self-refresh period, as the DDR2 self-refresh spec is
> > > equivalent to LPDDR1, and is correctly implemented in the controller.
> >
> > > Assume that the second controller has the same fault, but that is
> > > untested.
> >
> > > Signed-off-by: Peter Rosin <peda@axentia.se>
> > > Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> > > ---
> > > arch/arm/mach-at91/pm_slowclock.S | 43
> > +++++++++++++++++++++++++++++++-----
> > > include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> > > 2 files changed, 39 insertions(+), 6 deletions(-)
> >
> > > diff --git a/arch/arm/mach-at91/pm_slowclock.S
> > > b/arch/arm/mach-at91/pm_slowclock.S
> > > index e2bfaf5..1155217 100644
> > > --- a/arch/arm/mach-at91/pm_slowclock.S
> > > +++ b/arch/arm/mach-at91/pm_slowclock.S
> > [...]
> > > @@ -108,14 +118,26 @@ ddr_sr_enable:
> > >
> > > /* figure out if we use the second ram controller */
> > > cmp ramc1, #0
> > > - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > > - strne tmp2, .saved_sam9_lpr1
> > > - bicne tmp2, #AT91_DDRSDRC_LPCB
> > > - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> > > + beq ddr_no_2nd_ctrl
> > > +
> > > + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > > + str tmp2, .saved_sam9_mdr1
> > > + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> > > + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> > > + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > > + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
> >
> > Didn't you forget ~? Either that, or ~ above is not needed, I think.
>
> The code is correct, the first bic with ~ clears bits not in the relevant
> field in order to compare if LPDDR mode is active. The second bic(eq)
> w/o ~ clears the field, to make way for the bits in the below orreq
> when actually changing the register content into DDR2 mode.
>
> > > + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> > > + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > > +
> > > + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > > + str tmp2, .saved_sam9_lpr1
> > > + bic tmp2, #AT91_DDRSDRC_LPCB
> >
> > Didn't you forget ~? And isn't it 3-operand instruction (as seen in the above
> > code)?
>
> The logic for the LPR register is from the old code, the "only" thing
> I did to it was changing the instruction sequence to not have the
> ???ne form, i.e. ldrne, strne, bicne, orrne became ldr, str, bic, orr
> with a jump around it instead. So, the original code also had a two
> argument bic(ne), which indeed is strange, and I don't know why
> there is no warning from the assembler. Since there is no warning,
> my guess is that the assembler somehow mends it? Or does the
> patch actually break the second controller? It would be a surprise
> it the assembler handles 2-operand bicne differently from a
s/it the/if the/
> 2-operand bic, no?
>
> > > + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> >
> > Only 2 operands?
>
> Same argument as above. I didn't touch it (sort of...)
>
> Should I update the patch and fix this collateral 2-operand problem as
> well? To me, it feels like a separate patch, no?
I have now checked the assembler output, and apparently it mends the
input, just as I thought. That might be a fluke, of course, or it might be a
deliberate shorthand when the destination register is the same as the
following operand? But I also note that there are more instances of this
2 vs. 3 argument syntax, and I suggest that they are all fixed in one go,
if it is determined that they need fixing. I am obviously not an authority
when it comes to arm assembler syntax, so someone else will have to
advise...
Cheers,
Peter
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
@ 2015-01-27 21:55 ` Peter Rosin
0 siblings, 0 replies; 46+ messages in thread
From: Peter Rosin @ 2015-01-27 21:55 UTC (permalink / raw)
To: linux-arm-kernel
I wrote:
> Sergei Shtylyov wrote:
> > On 1/27/2015 8:53 AM, Wenyou Yang wrote:
> >
> > > From: Peter Rosin <peda@axentia.se>
> >
> > > The DDRSDR controller fails miserably to put LPDDR1 memories in
> > > self-refresh. Force the controller to think it has DDR2 memories
> > > during the self-refresh period, as the DDR2 self-refresh spec is
> > > equivalent to LPDDR1, and is correctly implemented in the controller.
> >
> > > Assume that the second controller has the same fault, but that is
> > > untested.
> >
> > > Signed-off-by: Peter Rosin <peda@axentia.se>
> > > Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
> > > ---
> > > arch/arm/mach-at91/pm_slowclock.S | 43
> > +++++++++++++++++++++++++++++++-----
> > > include/soc/at91/at91sam9_ddrsdr.h | 2 +-
> > > 2 files changed, 39 insertions(+), 6 deletions(-)
> >
> > > diff --git a/arch/arm/mach-at91/pm_slowclock.S
> > > b/arch/arm/mach-at91/pm_slowclock.S
> > > index e2bfaf5..1155217 100644
> > > --- a/arch/arm/mach-at91/pm_slowclock.S
> > > +++ b/arch/arm/mach-at91/pm_slowclock.S
> > [...]
> > > @@ -108,14 +118,26 @@ ddr_sr_enable:
> > >
> > > /* figure out if we use the second ram controller */
> > > cmp ramc1, #0
> > > - ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > > - strne tmp2, .saved_sam9_lpr1
> > > - bicne tmp2, #AT91_DDRSDRC_LPCB
> > > - orrne tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> > > + beq ddr_no_2nd_ctrl
> > > +
> > > + ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > > + str tmp2, .saved_sam9_mdr1
> > > + bic tmp2, tmp2, #~AT91_DDRSDRC_MD
> > > + cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
> > > + ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > > + biceq tmp2, tmp2, #AT91_DDRSDRC_MD
> >
> > Didn't you forget ~? Either that, or ~ above is not needed, I think.
>
> The code is correct, the first bic with ~ clears bits not in the relevant
> field in order to compare if LPDDR mode is active. The second bic(eq)
> w/o ~ clears the field, to make way for the bits in the below orreq
> when actually changing the register content into DDR2 mode.
>
> > > + orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
> > > + streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
> > > +
> > > + ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
> > > + str tmp2, .saved_sam9_lpr1
> > > + bic tmp2, #AT91_DDRSDRC_LPCB
> >
> > Didn't you forget ~? And isn't it 3-operand instruction (as seen in the above
> > code)?
>
> The logic for the LPR register is from the old code, the "only" thing
> I did to it was changing the instruction sequence to not have the
> ???ne form, i.e. ldrne, strne, bicne, orrne became ldr, str, bic, orr
> with a jump around it instead. So, the original code also had a two
> argument bic(ne), which indeed is strange, and I don't know why
> there is no warning from the assembler. Since there is no warning,
> my guess is that the assembler somehow mends it? Or does the
> patch actually break the second controller? It would be a surprise
> it the assembler handles 2-operand bicne differently from a
s/it the/if the/
> 2-operand bic, no?
>
> > > + orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
> >
> > Only 2 operands?
>
> Same argument as above. I didn't touch it (sort of...)
>
> Should I update the patch and fix this collateral 2-operand problem as
> well? To me, it feels like a separate patch, no?
I have now checked the assembler output, and apparently it mends the
input, just as I thought. That might be a fluke, of course, or it might be a
deliberate shorthand when the destination register is the same as the
following operand? But I also note that there are more instances of this
2 vs. 3 argument syntax, and I suggest that they are all fixed in one go,
if it is determined that they need fixing. I am obviously not an authority
when it comes to arm assembler syntax, so someone else will have to
advise...
Cheers,
Peter
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
2015-01-27 21:55 ` Peter Rosin
@ 2015-01-27 22:43 ` Russell King - ARM Linux
-1 siblings, 0 replies; 46+ messages in thread
From: Russell King - ARM Linux @ 2015-01-27 22:43 UTC (permalink / raw)
To: Peter Rosin
Cc: Sergei Shtylyov, Wenyou Yang, nicolas.ferre, linux-arm-kernel,
linux-kernel, alexandre.belloni, sylvain.rochet, linux
On Tue, Jan 27, 2015 at 09:55:52PM +0000, Peter Rosin wrote:
> I have now checked the assembler output, and apparently it mends the
> input, just as I thought. That might be a fluke, of course, or it might be a
> deliberate shorthand when the destination register is the same as the
> following operand?
I believe it is because we have the assembler in unified asm mode, where
such things are legal (due to Thumb2.) That means these two are
legal:
orr r2, #const
orr r2, r2, #const
and equivalent in this context.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.
@ 2015-01-27 22:43 ` Russell King - ARM Linux
0 siblings, 0 replies; 46+ messages in thread
From: Russell King - ARM Linux @ 2015-01-27 22:43 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 27, 2015 at 09:55:52PM +0000, Peter Rosin wrote:
> I have now checked the assembler output, and apparently it mends the
> input, just as I thought. That might be a fluke, of course, or it might be a
> deliberate shorthand when the destination register is the same as the
> following operand?
I believe it is because we have the assembler in unified asm mode, where
such things are legal (due to Thumb2.) That means these two are
legal:
orr r2, #const
orr r2, r2, #const
and equivalent in this context.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2015-01-27 22:43 UTC | newest]
Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-01-27 5:50 [PATCH v3 00/13] AT91 pm cleanup for 3.20 Wenyou Yang
2015-01-27 5:50 ` Wenyou Yang
2015-01-27 5:51 ` [PATCH v3 01/13] pm: at91: pm_slowclock: fix suspend/resume hang up in timeouts Wenyou Yang
2015-01-27 5:51 ` Wenyou Yang
2015-01-27 5:52 ` [PATCH v3 02/13] pm: at91: pm_slowclock: remove clocks which are already stopped when entering slow clock mode Wenyou Yang
2015-01-27 5:52 ` Wenyou Yang
2015-01-27 5:53 ` [PATCH v3 03/13] pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories Wenyou Yang
2015-01-27 5:53 ` Wenyou Yang
2015-01-27 10:24 ` Sergei Shtylyov
2015-01-27 10:24 ` Sergei Shtylyov
2015-01-27 12:14 ` Peter Rosin
2015-01-27 12:14 ` Peter Rosin
2015-01-27 21:55 ` Peter Rosin
2015-01-27 21:55 ` Peter Rosin
2015-01-27 22:43 ` Russell King - ARM Linux
2015-01-27 22:43 ` Russell King - ARM Linux
2015-01-27 5:54 ` [PATCH v3 04/13] pm: at91: pm_slowclock: remove the unused code related with SLOWDOWN_MASTER_CLOCK Wenyou Yang
2015-01-27 5:54 ` Wenyou Yang
2015-01-27 5:55 ` [PATCH v3 05/13] pm: at91: move the copying the sram function to the sram initializationi phase Wenyou Yang
2015-01-27 5:55 ` Wenyou Yang
2015-01-27 5:56 ` [PATCH v3 06/13] ARM: at91: move select SRAM to ARCH_AT91 Wenyou Yang
2015-01-27 5:56 ` Wenyou Yang
2015-01-27 5:57 ` [PATCH v3 07/13] pm: at91: remove the config item CONFIG_AT91_SLOW_CLOCK Wenyou Yang
2015-01-27 5:57 ` Wenyou Yang
2015-01-27 9:55 ` Sylvain Rochet
2015-01-27 9:55 ` Sylvain Rochet
2015-01-27 10:07 ` Alexandre Belloni
2015-01-27 10:07 ` Alexandre Belloni
2015-01-27 10:13 ` Sylvain Rochet
2015-01-27 10:13 ` Sylvain Rochet
2015-01-27 5:58 ` [PATCH v3 08/13] pm: at91: the standby mode uses the same sram function as the suspend to memory mode Wenyou Yang
2015-01-27 5:58 ` Wenyou Yang
2015-01-27 10:08 ` Sylvain Rochet
2015-01-27 10:08 ` Sylvain Rochet
2015-01-27 10:11 ` Yang, Wenyou
2015-01-27 10:11 ` Yang, Wenyou
2015-01-27 5:59 ` [PATCH v3 09/13] pm: at91: rename file name: pm_slowclock.S -->pm_suspend.S Wenyou Yang
2015-01-27 5:59 ` Wenyou Yang
2015-01-27 5:59 ` [PATCH v3 10/13] pm: at91: rename function name: at91_slow_clock()-->at91_pm_suspend_sram_fn Wenyou Yang
2015-01-27 5:59 ` Wenyou Yang
2015-01-27 6:00 ` [PATCH v3 11/13] pm: at91: remove the at91_xxx_standby() function definitions in the pm.h Wenyou Yang
2015-01-27 6:00 ` Wenyou Yang
2015-01-27 6:01 ` [PATCH v3 12/13] pm: at91: setup: remove the struct ramc_ids .data at91_xxx_standby members Wenyou Yang
2015-01-27 6:01 ` Wenyou Yang
2015-01-27 6:01 ` [PATCH v3 13/13] pm: at91: amend the pm_suspend entry for at91_cpuidle_device Wenyou Yang
2015-01-27 6:01 ` Wenyou Yang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.