[PATCH 00/11] MIPS: BCM63XX: add support for Broadcom 6368 CPU.

[PATCH 00/11] MIPS: BCM63XX: add support for Broadcom 6368 CPU.

[Maxime Bizon]

These patches add support for 6368 CPU to the existing bcm63xx code.

Basic CPU support for now, ethernet and board support will come soon.


Maxime Bizon (11):
  MIPS: BCM63XX: set default pci cache line size.
  MIPS: BCM63XX: hook up plat_ioremap to intercept soc registers
    remapping.
  MIPS: BCM63XX: call board_register_device from device_initcall()
  MIPS: BCM63XX: introduce bcm_readll & bcm_writell.
  MIPS: BCM63XX: cleanup cpu registers.
  MIPS: BCM63XX: add more register sets & missing register definitions.
  MIPS: BCM63XX: change irq code to prepare for per-cpu peculiarity.
  MIPS: BCM63XX: prepare irq code to handle different external irq
    hardware implementation.
  MIPS: BCM63XX: handle 64 bits irq stat register in irq code.
  MIPS: BCM63XX: add external irq support for non 6348 CPUs.
  MIPS: BCM63XX: add support for bcm6368 CPU.

 arch/mips/bcm63xx/Kconfig                         |    4 +
 arch/mips/bcm63xx/clk.c                           |   70 +++-
 arch/mips/bcm63xx/cpu.c                           |  221 +++------
 arch/mips/bcm63xx/dev-uart.c                      |    2 +-
 arch/mips/bcm63xx/irq.c                           |  321 ++++++++++--
 arch/mips/bcm63xx/prom.c                          |    7 +-
 arch/mips/bcm63xx/setup.c                         |    2 +-
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  593 +++++++++++++--------
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    2 +
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  213 +++++++-
 arch/mips/include/asm/mach-bcm63xx/ioremap.h      |   42 ++
 arch/mips/pci/pci-bcm63xx.c                       |    6 +-
 13 files changed, 1065 insertions(+), 420 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-bcm63xx/ioremap.h

[PATCH 01/11] MIPS: BCM63XX: set default pci cache line size.

[Maxime Bizon]

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/pci/pci-bcm63xx.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 82e0fde..c7fc92f 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -215,6 +215,8 @@ static int __init bcm63xx_pci_init(void)
 	register_pci_controller(&bcm63xx_cb_controller);
 #endif
 
+	pci_cache_line_size = 4;
+
 	/* mark memory space used for IO mapping as reserved */
 	request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
 			   "bcm63xx PCI IO space");
-- 
1.7.1.1

[PATCH 02/11] MIPS: BCM63XX: hook up plat_ioremap to intercept soc registers remapping.

[Maxime Bizon]

Internal SOC registers can be directly accessed, no need to waste a
TLB entry.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/include/asm/mach-bcm63xx/ioremap.h |   38 ++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-bcm63xx/ioremap.h

diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
new file mode 100644
index 0000000..e3fe04d
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -0,0 +1,38 @@
+#ifndef BCM63XX_IOREMAP_H_
+#define BCM63XX_IOREMAP_H_
+
+#include <bcm63xx_cpu.h>
+
+static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+	return phys_addr;
+}
+
+static inline int is_bcm63xx_internal_registers(phys_t offset)
+{
+	switch (bcm63xx_get_cpu_id()) {
+	case BCM6338_CPU_ID:
+	case BCM6345_CPU_ID:
+	case BCM6348_CPU_ID:
+	case BCM6358_CPU_ID:
+		if (offset >= 0xfff00000)
+			return 1;
+		break;
+	}
+	return 0;
+}
+
+static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
+					 unsigned long flags)
+{
+	if (is_bcm63xx_internal_registers(offset))
+		return (void __iomem *)offset;
+	return NULL;
+}
+
+static inline int plat_iounmap(const volatile void __iomem *addr)
+{
+	return is_bcm63xx_internal_registers((unsigned long)addr);
+}
+
+#endif /* BCM63XX_IOREMAP_H_ */
-- 
1.7.1.1

[PATCH 03/11] MIPS: BCM63XX: call board_register_device from device_initcall()

[Maxime Bizon]

Some device registration (eg leds), expect subsystem initcall to be
run first, so move board device registration to device_initcall().

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/setup.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index d005659..04a3499 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -124,4 +124,4 @@ int __init bcm63xx_register_devices(void)
 	return board_register_devices();
 }
 
-arch_initcall(bcm63xx_register_devices);
+device_initcall(bcm63xx_register_devices);
-- 
1.7.1.1

[PATCH 04/11] MIPS: BCM63XX: introduce bcm_readll & bcm_writell.

[Maxime Bizon]

Needed for upcoming 6368 CPU support.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 91180fa..8bf4a67 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,9 +49,11 @@
 #define bcm_readb(a)	(*(volatile unsigned char *)	BCM_REGS_VA(a))
 #define bcm_readw(a)	(*(volatile unsigned short *)	BCM_REGS_VA(a))
 #define bcm_readl(a)	(*(volatile unsigned int *)	BCM_REGS_VA(a))
+#define bcm_readll(a)	(*(volatile u64 *)		BCM_REGS_VA(a))
 #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
 #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
 #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
+#define bcm_writell(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
 
 /*
  * IO helpers to access register set for current CPU
-- 
1.7.1.1

[PATCH 05/11] MIPS: BCM63XX: cleanup cpu registers.

[Maxime Bizon]

Use preprocessor when possible to avoid duplicated and error-prone
code.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/cpu.c                          |  145 +----------
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |  311 +++++++---------------
 2 files changed, 109 insertions(+), 347 deletions(-)

diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7c7e4d4..027ac30 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -33,162 +33,37 @@ static unsigned int bcm63xx_memory_size;
  * 6338 register sets and irqs
  */
 static const unsigned long bcm96338_regs_base[] = {
-	[RSET_DSL_LMEM]		= BCM_6338_DSL_LMEM_BASE,
-	[RSET_PERF]		= BCM_6338_PERF_BASE,
-	[RSET_TIMER]		= BCM_6338_TIMER_BASE,
-	[RSET_WDT]		= BCM_6338_WDT_BASE,
-	[RSET_UART0]		= BCM_6338_UART0_BASE,
-	[RSET_UART1]		= BCM_6338_UART1_BASE,
-	[RSET_GPIO]		= BCM_6338_GPIO_BASE,
-	[RSET_SPI]		= BCM_6338_SPI_BASE,
-	[RSET_OHCI0]		= BCM_6338_OHCI0_BASE,
-	[RSET_OHCI_PRIV]	= BCM_6338_OHCI_PRIV_BASE,
-	[RSET_USBH_PRIV]	= BCM_6338_USBH_PRIV_BASE,
-	[RSET_UDC0]		= BCM_6338_UDC0_BASE,
-	[RSET_MPI]		= BCM_6338_MPI_BASE,
-	[RSET_PCMCIA]		= BCM_6338_PCMCIA_BASE,
-	[RSET_SDRAM]		= BCM_6338_SDRAM_BASE,
-	[RSET_DSL]		= BCM_6338_DSL_BASE,
-	[RSET_ENET0]		= BCM_6338_ENET0_BASE,
-	[RSET_ENET1]		= BCM_6338_ENET1_BASE,
-	[RSET_ENETDMA]		= BCM_6338_ENETDMA_BASE,
-	[RSET_MEMC]		= BCM_6338_MEMC_BASE,
-	[RSET_DDR]		= BCM_6338_DDR_BASE,
+	__GEN_CPU_REGS_TABLE(6338)
 };
 
 static const int bcm96338_irqs[] = {
-	[IRQ_TIMER]		= BCM_6338_TIMER_IRQ,
-	[IRQ_UART0]		= BCM_6338_UART0_IRQ,
-	[IRQ_DSL]		= BCM_6338_DSL_IRQ,
-	[IRQ_ENET0]		= BCM_6338_ENET0_IRQ,
-	[IRQ_ENET_PHY]		= BCM_6338_ENET_PHY_IRQ,
-	[IRQ_ENET0_RXDMA]	= BCM_6338_ENET0_RXDMA_IRQ,
-	[IRQ_ENET0_TXDMA]	= BCM_6338_ENET0_TXDMA_IRQ,
+	__GEN_CPU_IRQ_TABLE(6338)
 };
 
-/*
- * 6345 register sets and irqs
- */
 static const unsigned long bcm96345_regs_base[] = {
-	[RSET_DSL_LMEM]		= BCM_6345_DSL_LMEM_BASE,
-	[RSET_PERF]		= BCM_6345_PERF_BASE,
-	[RSET_TIMER]		= BCM_6345_TIMER_BASE,
-	[RSET_WDT]		= BCM_6345_WDT_BASE,
-	[RSET_UART0]		= BCM_6345_UART0_BASE,
-	[RSET_UART1]		= BCM_6345_UART1_BASE,
-	[RSET_GPIO]		= BCM_6345_GPIO_BASE,
-	[RSET_SPI]		= BCM_6345_SPI_BASE,
-	[RSET_UDC0]		= BCM_6345_UDC0_BASE,
-	[RSET_OHCI0]		= BCM_6345_OHCI0_BASE,
-	[RSET_OHCI_PRIV]	= BCM_6345_OHCI_PRIV_BASE,
-	[RSET_USBH_PRIV]	= BCM_6345_USBH_PRIV_BASE,
-	[RSET_MPI]		= BCM_6345_MPI_BASE,
-	[RSET_PCMCIA]		= BCM_6345_PCMCIA_BASE,
-	[RSET_DSL]		= BCM_6345_DSL_BASE,
-	[RSET_ENET0]		= BCM_6345_ENET0_BASE,
-	[RSET_ENET1]		= BCM_6345_ENET1_BASE,
-	[RSET_ENETDMA]		= BCM_6345_ENETDMA_BASE,
-	[RSET_EHCI0]		= BCM_6345_EHCI0_BASE,
-	[RSET_SDRAM]		= BCM_6345_SDRAM_BASE,
-	[RSET_MEMC]		= BCM_6345_MEMC_BASE,
-	[RSET_DDR]		= BCM_6345_DDR_BASE,
+	__GEN_CPU_REGS_TABLE(6345)
 };
 
 static const int bcm96345_irqs[] = {
-	[IRQ_TIMER]		= BCM_6345_TIMER_IRQ,
-	[IRQ_UART0]		= BCM_6345_UART0_IRQ,
-	[IRQ_DSL]		= BCM_6345_DSL_IRQ,
-	[IRQ_ENET0]		= BCM_6345_ENET0_IRQ,
-	[IRQ_ENET_PHY]		= BCM_6345_ENET_PHY_IRQ,
-	[IRQ_ENET0_RXDMA]	= BCM_6345_ENET0_RXDMA_IRQ,
-	[IRQ_ENET0_TXDMA]	= BCM_6345_ENET0_TXDMA_IRQ,
+	__GEN_CPU_IRQ_TABLE(6345)
 };
 
-/*
- * 6348 register sets and irqs
- */
 static const unsigned long bcm96348_regs_base[] = {
-	[RSET_DSL_LMEM]		= BCM_6348_DSL_LMEM_BASE,
-	[RSET_PERF]		= BCM_6348_PERF_BASE,
-	[RSET_TIMER]		= BCM_6348_TIMER_BASE,
-	[RSET_WDT]		= BCM_6348_WDT_BASE,
-	[RSET_UART0]		= BCM_6348_UART0_BASE,
-	[RSET_UART1]		= BCM_6348_UART1_BASE,
-	[RSET_GPIO]		= BCM_6348_GPIO_BASE,
-	[RSET_SPI]		= BCM_6348_SPI_BASE,
-	[RSET_OHCI0]		= BCM_6348_OHCI0_BASE,
-	[RSET_OHCI_PRIV]	= BCM_6348_OHCI_PRIV_BASE,
-	[RSET_USBH_PRIV]	= BCM_6348_USBH_PRIV_BASE,
-	[RSET_MPI]		= BCM_6348_MPI_BASE,
-	[RSET_PCMCIA]		= BCM_6348_PCMCIA_BASE,
-	[RSET_SDRAM]		= BCM_6348_SDRAM_BASE,
-	[RSET_DSL]		= BCM_6348_DSL_BASE,
-	[RSET_ENET0]		= BCM_6348_ENET0_BASE,
-	[RSET_ENET1]		= BCM_6348_ENET1_BASE,
-	[RSET_ENETDMA]		= BCM_6348_ENETDMA_BASE,
-	[RSET_MEMC]		= BCM_6348_MEMC_BASE,
-	[RSET_DDR]		= BCM_6348_DDR_BASE,
+	__GEN_CPU_REGS_TABLE(6348)
 };
 
 static const int bcm96348_irqs[] = {
-	[IRQ_TIMER]		= BCM_6348_TIMER_IRQ,
-	[IRQ_UART0]		= BCM_6348_UART0_IRQ,
-	[IRQ_DSL]		= BCM_6348_DSL_IRQ,
-	[IRQ_ENET0]		= BCM_6348_ENET0_IRQ,
-	[IRQ_ENET1]		= BCM_6348_ENET1_IRQ,
-	[IRQ_ENET_PHY]		= BCM_6348_ENET_PHY_IRQ,
-	[IRQ_OHCI0]		= BCM_6348_OHCI0_IRQ,
-	[IRQ_PCMCIA]		= BCM_6348_PCMCIA_IRQ,
-	[IRQ_ENET0_RXDMA]	= BCM_6348_ENET0_RXDMA_IRQ,
-	[IRQ_ENET0_TXDMA]	= BCM_6348_ENET0_TXDMA_IRQ,
-	[IRQ_ENET1_RXDMA]	= BCM_6348_ENET1_RXDMA_IRQ,
-	[IRQ_ENET1_TXDMA]	= BCM_6348_ENET1_TXDMA_IRQ,
-	[IRQ_PCI]		= BCM_6348_PCI_IRQ,
+	__GEN_CPU_IRQ_TABLE(6348)
+
 };
 
-/*
- * 6358 register sets and irqs
- */
 static const unsigned long bcm96358_regs_base[] = {
-	[RSET_DSL_LMEM]		= BCM_6358_DSL_LMEM_BASE,
-	[RSET_PERF]		= BCM_6358_PERF_BASE,
-	[RSET_TIMER]		= BCM_6358_TIMER_BASE,
-	[RSET_WDT]		= BCM_6358_WDT_BASE,
-	[RSET_UART0]		= BCM_6358_UART0_BASE,
-	[RSET_UART1]		= BCM_6358_UART1_BASE,
-	[RSET_GPIO]		= BCM_6358_GPIO_BASE,
-	[RSET_SPI]		= BCM_6358_SPI_BASE,
-	[RSET_OHCI0]		= BCM_6358_OHCI0_BASE,
-	[RSET_EHCI0]		= BCM_6358_EHCI0_BASE,
-	[RSET_OHCI_PRIV]	= BCM_6358_OHCI_PRIV_BASE,
-	[RSET_USBH_PRIV]	= BCM_6358_USBH_PRIV_BASE,
-	[RSET_MPI]		= BCM_6358_MPI_BASE,
-	[RSET_PCMCIA]		= BCM_6358_PCMCIA_BASE,
-	[RSET_SDRAM]		= BCM_6358_SDRAM_BASE,
-	[RSET_DSL]		= BCM_6358_DSL_BASE,
-	[RSET_ENET0]		= BCM_6358_ENET0_BASE,
-	[RSET_ENET1]		= BCM_6358_ENET1_BASE,
-	[RSET_ENETDMA]		= BCM_6358_ENETDMA_BASE,
-	[RSET_MEMC]		= BCM_6358_MEMC_BASE,
-	[RSET_DDR]		= BCM_6358_DDR_BASE,
+	__GEN_CPU_REGS_TABLE(6358)
 };
 
 static const int bcm96358_irqs[] = {
-	[IRQ_TIMER]		= BCM_6358_TIMER_IRQ,
-	[IRQ_UART0]		= BCM_6358_UART0_IRQ,
-	[IRQ_UART1]		= BCM_6358_UART1_IRQ,
-	[IRQ_DSL]		= BCM_6358_DSL_IRQ,
-	[IRQ_ENET0]		= BCM_6358_ENET0_IRQ,
-	[IRQ_ENET1]		= BCM_6358_ENET1_IRQ,
-	[IRQ_ENET_PHY]		= BCM_6358_ENET_PHY_IRQ,
-	[IRQ_OHCI0]		= BCM_6358_OHCI0_IRQ,
-	[IRQ_EHCI0]		= BCM_6358_EHCI0_IRQ,
-	[IRQ_PCMCIA]		= BCM_6358_PCMCIA_IRQ,
-	[IRQ_ENET0_RXDMA]	= BCM_6358_ENET0_RXDMA_IRQ,
-	[IRQ_ENET0_TXDMA]	= BCM_6358_ENET0_TXDMA_IRQ,
-	[IRQ_ENET1_RXDMA]	= BCM_6358_ENET1_RXDMA_IRQ,
-	[IRQ_ENET1_TXDMA]	= BCM_6358_ENET1_TXDMA_IRQ,
-	[IRQ_PCI]		= BCM_6358_PCI_IRQ,
+	__GEN_CPU_IRQ_TABLE(6358)
+
 };
 
 u16 __bcm63xx_get_cpu_id(void)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391..464f948 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -234,202 +234,77 @@ enum bcm63xx_regs_set {
 
 extern const unsigned long *bcm63xx_regs_base;
 
+#define __GEN_RSET_BASE(__cpu, __rset)					\
+	case RSET_## __rset :						\
+		return BCM_## __cpu ##_## __rset ##_BASE;
+
+#define __GEN_RSET(__cpu)						\
+	switch (set) {							\
+	__GEN_RSET_BASE(__cpu, DSL_LMEM)				\
+	__GEN_RSET_BASE(__cpu, PERF)					\
+	__GEN_RSET_BASE(__cpu, TIMER)					\
+	__GEN_RSET_BASE(__cpu, WDT)					\
+	__GEN_RSET_BASE(__cpu, UART0)					\
+	__GEN_RSET_BASE(__cpu, UART1)					\
+	__GEN_RSET_BASE(__cpu, GPIO)					\
+	__GEN_RSET_BASE(__cpu, SPI)					\
+	__GEN_RSET_BASE(__cpu, UDC0)					\
+	__GEN_RSET_BASE(__cpu, OHCI0)					\
+	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
+	__GEN_RSET_BASE(__cpu, USBH_PRIV)				\
+	__GEN_RSET_BASE(__cpu, MPI)					\
+	__GEN_RSET_BASE(__cpu, PCMCIA)					\
+	__GEN_RSET_BASE(__cpu, DSL)					\
+	__GEN_RSET_BASE(__cpu, ENET0)					\
+	__GEN_RSET_BASE(__cpu, ENET1)					\
+	__GEN_RSET_BASE(__cpu, ENETDMA)					\
+	__GEN_RSET_BASE(__cpu, EHCI0)					\
+	__GEN_RSET_BASE(__cpu, SDRAM)					\
+	__GEN_RSET_BASE(__cpu, MEMC)					\
+	__GEN_RSET_BASE(__cpu, DDR)					\
+	}
+
+#define __GEN_CPU_REGS_TABLE(__cpu)					\
+	[RSET_DSL_LMEM]		= BCM_## __cpu ##_DSL_LMEM_BASE,	\
+	[RSET_PERF]		= BCM_## __cpu ##_PERF_BASE,		\
+	[RSET_TIMER]		= BCM_## __cpu ##_TIMER_BASE,		\
+	[RSET_WDT]		= BCM_## __cpu ##_WDT_BASE,		\
+	[RSET_UART0]		= BCM_## __cpu ##_UART0_BASE,		\
+	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
+	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
+	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
+	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
+	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
+	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
+	[RSET_USBH_PRIV]	= BCM_## __cpu ##_USBH_PRIV_BASE,	\
+	[RSET_MPI]		= BCM_## __cpu ##_MPI_BASE,		\
+	[RSET_PCMCIA]		= BCM_## __cpu ##_PCMCIA_BASE,		\
+	[RSET_DSL]		= BCM_## __cpu ##_DSL_BASE,		\
+	[RSET_ENET0]		= BCM_## __cpu ##_ENET0_BASE,		\
+	[RSET_ENET1]		= BCM_## __cpu ##_ENET1_BASE,		\
+	[RSET_ENETDMA]		= BCM_## __cpu ##_ENETDMA_BASE,		\
+	[RSET_EHCI0]		= BCM_## __cpu ##_EHCI0_BASE,		\
+	[RSET_SDRAM]		= BCM_## __cpu ##_SDRAM_BASE,		\
+	[RSET_MEMC]		= BCM_## __cpu ##_MEMC_BASE,		\
+	[RSET_DDR]		= BCM_## __cpu ##_DDR_BASE,		\
+
+
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 {
 #ifdef BCMCPU_RUNTIME_DETECT
 	return bcm63xx_regs_base[set];
 #else
 #ifdef CONFIG_BCM63XX_CPU_6338
-	switch (set) {
-	case RSET_DSL_LMEM:
-		return BCM_6338_DSL_LMEM_BASE;
-	case RSET_PERF:
-		return BCM_6338_PERF_BASE;
-	case RSET_TIMER:
-		return BCM_6338_TIMER_BASE;
-	case RSET_WDT:
-		return BCM_6338_WDT_BASE;
-	case RSET_UART0:
-		return BCM_6338_UART0_BASE;
-	case RSET_UART1:
-		return BCM_6338_UART1_BASE;
-	case RSET_GPIO:
-		return BCM_6338_GPIO_BASE;
-	case RSET_SPI:
-		return BCM_6338_SPI_BASE;
-	case RSET_UDC0:
-		return BCM_6338_UDC0_BASE;
-	case RSET_OHCI0:
-		return BCM_6338_OHCI0_BASE;
-	case RSET_OHCI_PRIV:
-		return BCM_6338_OHCI_PRIV_BASE;
-	case RSET_USBH_PRIV:
-		return BCM_6338_USBH_PRIV_BASE;
-	case RSET_MPI:
-		return BCM_6338_MPI_BASE;
-	case RSET_PCMCIA:
-		return BCM_6338_PCMCIA_BASE;
-	case RSET_DSL:
-		return BCM_6338_DSL_BASE;
-	case RSET_ENET0:
-		return BCM_6338_ENET0_BASE;
-	case RSET_ENET1:
-		return BCM_6338_ENET1_BASE;
-	case RSET_ENETDMA:
-		return BCM_6338_ENETDMA_BASE;
-	case RSET_EHCI0:
-		return BCM_6338_EHCI0_BASE;
-	case RSET_SDRAM:
-		return BCM_6338_SDRAM_BASE;
-	case RSET_MEMC:
-		return BCM_6338_MEMC_BASE;
-	case RSET_DDR:
-		return BCM_6338_DDR_BASE;
-	}
+	__GEN_RSET(6338)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
-	switch (set) {
-	case RSET_DSL_LMEM:
-		return BCM_6345_DSL_LMEM_BASE;
-	case RSET_PERF:
-		return BCM_6345_PERF_BASE;
-	case RSET_TIMER:
-		return BCM_6345_TIMER_BASE;
-	case RSET_WDT:
-		return BCM_6345_WDT_BASE;
-	case RSET_UART0:
-		return BCM_6345_UART0_BASE;
-	case RSET_UART1:
-		return BCM_6345_UART1_BASE;
-	case RSET_GPIO:
-		return BCM_6345_GPIO_BASE;
-	case RSET_SPI:
-		return BCM_6345_SPI_BASE;
-	case RSET_UDC0:
-		return BCM_6345_UDC0_BASE;
-	case RSET_OHCI0:
-		return BCM_6345_OHCI0_BASE;
-	case RSET_OHCI_PRIV:
-		return BCM_6345_OHCI_PRIV_BASE;
-	case RSET_USBH_PRIV:
-		return BCM_6345_USBH_PRIV_BASE;
-	case RSET_MPI:
-		return BCM_6345_MPI_BASE;
-	case RSET_PCMCIA:
-		return BCM_6345_PCMCIA_BASE;
-	case RSET_DSL:
-		return BCM_6345_DSL_BASE;
-	case RSET_ENET0:
-		return BCM_6345_ENET0_BASE;
-	case RSET_ENET1:
-		return BCM_6345_ENET1_BASE;
-	case RSET_ENETDMA:
-		return BCM_6345_ENETDMA_BASE;
-	case RSET_EHCI0:
-		return BCM_6345_EHCI0_BASE;
-	case RSET_SDRAM:
-		return BCM_6345_SDRAM_BASE;
-	case RSET_MEMC:
-		return BCM_6345_MEMC_BASE;
-	case RSET_DDR:
-		return BCM_6345_DDR_BASE;
-	}
+	__GEN_RSET(6345)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
-	switch (set) {
-	case RSET_DSL_LMEM:
-		return BCM_6348_DSL_LMEM_BASE;
-	case RSET_PERF:
-		return BCM_6348_PERF_BASE;
-	case RSET_TIMER:
-		return BCM_6348_TIMER_BASE;
-	case RSET_WDT:
-		return BCM_6348_WDT_BASE;
-	case RSET_UART0:
-		return BCM_6348_UART0_BASE;
-	case RSET_UART1:
-		return BCM_6348_UART1_BASE;
-	case RSET_GPIO:
-		return BCM_6348_GPIO_BASE;
-	case RSET_SPI:
-		return BCM_6348_SPI_BASE;
-	case RSET_UDC0:
-		return BCM_6348_UDC0_BASE;
-	case RSET_OHCI0:
-		return BCM_6348_OHCI0_BASE;
-	case RSET_OHCI_PRIV:
-		return BCM_6348_OHCI_PRIV_BASE;
-	case RSET_USBH_PRIV:
-		return BCM_6348_USBH_PRIV_BASE;
-	case RSET_MPI:
-		return BCM_6348_MPI_BASE;
-	case RSET_PCMCIA:
-		return BCM_6348_PCMCIA_BASE;
-	case RSET_DSL:
-		return BCM_6348_DSL_BASE;
-	case RSET_ENET0:
-		return BCM_6348_ENET0_BASE;
-	case RSET_ENET1:
-		return BCM_6348_ENET1_BASE;
-	case RSET_ENETDMA:
-		return BCM_6348_ENETDMA_BASE;
-	case RSET_EHCI0:
-		return BCM_6348_EHCI0_BASE;
-	case RSET_SDRAM:
-		return BCM_6348_SDRAM_BASE;
-	case RSET_MEMC:
-		return BCM_6348_MEMC_BASE;
-	case RSET_DDR:
-		return BCM_6348_DDR_BASE;
-	}
+	__GEN_RSET(6348)
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6358
-	switch (set) {
-	case RSET_DSL_LMEM:
-		return BCM_6358_DSL_LMEM_BASE;
-	case RSET_PERF:
-		return BCM_6358_PERF_BASE;
-	case RSET_TIMER:
-		return BCM_6358_TIMER_BASE;
-	case RSET_WDT:
-		return BCM_6358_WDT_BASE;
-	case RSET_UART0:
-		return BCM_6358_UART0_BASE;
-	case RSET_UART1:
-		return BCM_6358_UART1_BASE;
-	case RSET_GPIO:
-		return BCM_6358_GPIO_BASE;
-	case RSET_SPI:
-		return BCM_6358_SPI_BASE;
-	case RSET_UDC0:
-		return BCM_6358_UDC0_BASE;
-	case RSET_OHCI0:
-		return BCM_6358_OHCI0_BASE;
-	case RSET_OHCI_PRIV:
-		return BCM_6358_OHCI_PRIV_BASE;
-	case RSET_USBH_PRIV:
-		return BCM_6358_USBH_PRIV_BASE;
-	case RSET_MPI:
-		return BCM_6358_MPI_BASE;
-	case RSET_PCMCIA:
-		return BCM_6358_PCMCIA_BASE;
-	case RSET_ENET0:
-		return BCM_6358_ENET0_BASE;
-	case RSET_ENET1:
-		return BCM_6358_ENET1_BASE;
-	case RSET_ENETDMA:
-		return BCM_6358_ENETDMA_BASE;
-	case RSET_DSL:
-		return BCM_6358_DSL_BASE;
-	case RSET_EHCI0:
-		return BCM_6358_EHCI0_BASE;
-	case RSET_SDRAM:
-		return BCM_6358_SDRAM_BASE;
-	case RSET_MEMC:
-		return BCM_6358_MEMC_BASE;
-	case RSET_DDR:
-		return BCM_6358_DDR_BASE;
-	}
+	__GEN_RSET(6358)
 #endif
 #endif
 	/* unreached */
@@ -449,7 +324,6 @@ enum bcm63xx_irq {
 	IRQ_ENET_PHY,
 	IRQ_OHCI0,
 	IRQ_EHCI0,
-	IRQ_PCMCIA0,
 	IRQ_ENET0_RXDMA,
 	IRQ_ENET0_TXDMA,
 	IRQ_ENET1_RXDMA,
@@ -462,62 +336,58 @@ enum bcm63xx_irq {
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
-#define BCM_6338_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
-#define BCM_6338_DG_IRQ			(IRQ_INTERNAL_BASE + 4)
+#define BCM_6338_UART1_IRQ		0
 #define BCM_6338_DSL_IRQ		(IRQ_INTERNAL_BASE + 5)
-#define BCM_6338_ATM_IRQ		(IRQ_INTERNAL_BASE + 6)
-#define BCM_6338_UDC0_IRQ		(IRQ_INTERNAL_BASE + 7)
 #define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET1_IRQ		0
 #define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-#define BCM_6338_SDRAM_IRQ		(IRQ_INTERNAL_BASE + 10)
-#define BCM_6338_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 11)
-#define BCM_6338_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 12)
-#define BCM_6338_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13)
-#define BCM_6338_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 14)
+#define BCM_6338_OHCI0_IRQ		0
+#define BCM_6338_EHCI0_IRQ		0
 #define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
-#define BCM_6338_SDIO_IRQ		(IRQ_INTERNAL_BASE + 17)
+#define BCM_6338_ENET1_RXDMA_IRQ	0
+#define BCM_6338_ENET1_TXDMA_IRQ	0
+#define BCM_6338_PCI_IRQ		0
+#define BCM_6338_PCMCIA_IRQ		0
 
 /*
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
 #define BCM_6345_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
+#define BCM_6345_UART1_IRQ		0
 #define BCM_6345_DSL_IRQ		(IRQ_INTERNAL_BASE + 3)
-#define BCM_6345_ATM_IRQ		(IRQ_INTERNAL_BASE + 4)
-#define BCM_6345_USB_IRQ		(IRQ_INTERNAL_BASE + 5)
 #define BCM_6345_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+#define BCM_6345_ENET1_IRQ		0
 #define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
+#define BCM_6345_OHCI0_IRQ		0
+#define BCM_6345_EHCI0_IRQ		0
 #define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 2)
-#define BCM_6345_EBI_RX_IRQ		(IRQ_INTERNAL_BASE + 13 + 5)
-#define BCM_6345_EBI_TX_IRQ		(IRQ_INTERNAL_BASE + 13 + 6)
-#define BCM_6345_RESERVED_RX_IRQ	(IRQ_INTERNAL_BASE + 13 + 9)
-#define BCM_6345_RESERVED_TX_IRQ	(IRQ_INTERNAL_BASE + 13 + 10)
-#define BCM_6345_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 13)
-#define BCM_6345_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 14)
-#define BCM_6345_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 15)
-#define BCM_6345_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 16)
-#define BCM_6345_USB_ISO_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 17)
-#define BCM_6345_USB_ISO_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 18)
+#define BCM_6345_ENET1_RXDMA_IRQ	0
+#define BCM_6345_ENET1_TXDMA_IRQ	0
+#define BCM_6345_PCI_IRQ		0
+#define BCM_6345_PCMCIA_IRQ		0
 
 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
 #define BCM_6348_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
+#define BCM_6348_UART1_IRQ		0
 #define BCM_6348_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
-#define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+#define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
+#define BCM_6348_EHCI0_IRQ		0
 #define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 22)
 #define BCM_6348_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 23)
-#define BCM_6348_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
 #define BCM_6348_PCI_IRQ		(IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
 
 /*
  * 6358 irqs
@@ -525,21 +395,38 @@ enum bcm63xx_irq {
 #define BCM_6358_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
 #define BCM_6358_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
-#define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
-#define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
+#define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+#define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
 #define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
+#define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
 #define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 17)
 #define BCM_6358_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 18)
-#define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_PCI_IRQ		(IRQ_INTERNAL_BASE + 31)
 #define BCM_6358_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
 
 extern const int *bcm63xx_irqs;
 
+#define __GEN_CPU_IRQ_TABLE(__cpu)					\
+	[IRQ_TIMER]		= BCM_## __cpu ##_TIMER_IRQ,		\
+	[IRQ_UART0]		= BCM_## __cpu ##_UART0_IRQ,		\
+	[IRQ_UART1]		= BCM_## __cpu ##_UART1_IRQ,		\
+	[IRQ_DSL]		= BCM_## __cpu ##_DSL_IRQ,		\
+	[IRQ_ENET0]		= BCM_## __cpu ##_ENET0_IRQ,		\
+	[IRQ_ENET1]		= BCM_## __cpu ##_ENET1_IRQ,		\
+	[IRQ_ENET_PHY]		= BCM_## __cpu ##_ENET_PHY_IRQ,		\
+	[IRQ_OHCI0]		= BCM_## __cpu ##_OHCI0_IRQ,		\
+	[IRQ_EHCI0]		= BCM_## __cpu ##_EHCI0_IRQ,		\
+	[IRQ_ENET0_RXDMA]	= BCM_## __cpu ##_ENET0_RXDMA_IRQ,	\
+	[IRQ_ENET0_TXDMA]	= BCM_## __cpu ##_ENET0_TXDMA_IRQ,	\
+	[IRQ_ENET1_RXDMA]	= BCM_## __cpu ##_ENET1_RXDMA_IRQ,	\
+	[IRQ_ENET1_TXDMA]	= BCM_## __cpu ##_ENET1_TXDMA_IRQ,	\
+	[IRQ_PCI]		= BCM_## __cpu ##_PCI_IRQ,		\
+	[IRQ_PCMCIA]		= BCM_## __cpu ##_PCMCIA_IRQ,		\
+
 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 {
 	return bcm63xx_irqs[irq];
-- 
1.7.1.1

[PATCH 06/11] MIPS: BCM63XX: add more register sets & missing register definitions.

[Maxime Bizon]

Needed for upcoming 6368 CPU support.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  183 +++++++++++++++++++++
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   78 +++++++++
 2 files changed, 261 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 464f948..ce6b3ca 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -88,6 +88,7 @@ enum bcm63xx_regs_set {
 	RSET_UART1,
 	RSET_GPIO,
 	RSET_SPI,
+	RSET_SPI2,
 	RSET_UDC0,
 	RSET_OHCI0,
 	RSET_OHCI_PRIV,
@@ -98,10 +99,23 @@ enum bcm63xx_regs_set {
 	RSET_ENET0,
 	RSET_ENET1,
 	RSET_ENETDMA,
+	RSET_ENETDMAC,
+	RSET_ENETDMAS,
+	RSET_ENETSW,
 	RSET_EHCI0,
 	RSET_SDRAM,
 	RSET_MEMC,
 	RSET_DDR,
+	RSET_M2M,
+	RSET_ATM,
+	RSET_XTM,
+	RSET_XTMDMA,
+	RSET_XTMDMAC,
+	RSET_XTMDMAS,
+	RSET_PCM,
+	RSET_PCMDMA,
+	RSET_PCMDMAC,
+	RSET_PCMDMAS,
 };
 
 #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
@@ -109,11 +123,18 @@ enum bcm63xx_regs_set {
 #define RSET_WDT_SIZE			12
 #define RSET_ENET_SIZE			2048
 #define RSET_ENETDMA_SIZE		2048
+#define RSET_ENETSW_SIZE		65536
 #define RSET_UART_SIZE			24
 #define RSET_UDC_SIZE			256
 #define RSET_OHCI_SIZE			256
 #define RSET_EHCI_SIZE			256
 #define RSET_PCMCIA_SIZE		12
+#define RSET_M2M_SIZE			256
+#define RSET_ATM_SIZE			4096
+#define RSET_XTM_SIZE			10240
+#define RSET_XTMDMA_SIZE		256
+#define RSET_XTMDMAC_SIZE(chans)	(16 * (chans))
+#define RSET_XTMDMAS_SIZE(chans)	(16 * (chans))
 
 /*
  * 6338 register sets base address
@@ -127,6 +148,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE		(0xdeadbeef)
 #define BCM_6338_GPIO_BASE		(0xfffe0400)
 #define BCM_6338_SPI_BASE		(0xfffe0c00)
+#define BCM_6338_SPI2_BASE		(0xdeadbeef)
 #define BCM_6338_UDC0_BASE		(0xdeadbeef)
 #define BCM_6338_USBDMA_BASE		(0xfffe2400)
 #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
@@ -141,10 +163,23 @@ enum bcm63xx_regs_set {
 #define BCM_6338_ENET0_BASE		(0xfffe2800)
 #define BCM_6338_ENET1_BASE		(0xdeadbeef)
 #define BCM_6338_ENETDMA_BASE		(0xfffe2400)
+#define BCM_6338_ENETDMAC_BASE		(0xfffe2500)
+#define BCM_6338_ENETDMAS_BASE		(0xfffe2600)
+#define BCM_6338_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6338_EHCI0_BASE		(0xdeadbeef)
 #define BCM_6338_SDRAM_BASE		(0xfffe3100)
 #define BCM_6338_MEMC_BASE		(0xdeadbeef)
 #define BCM_6338_DDR_BASE		(0xdeadbeef)
+#define BCM_6338_M2M_BASE		(0xdeadbeef)
+#define BCM_6338_ATM_BASE		(0xdeadbeef)
+#define BCM_6338_XTM_BASE		(0xdeadbeef)
+#define BCM_6338_XTMDMA_BASE		(0xdeadbeef)
+#define BCM_6338_XTMDMAC_BASE		(0xdeadbeef)
+#define BCM_6338_XTMDMAS_BASE		(0xdeadbeef)
+#define BCM_6338_PCM_BASE		(0xdeadbeef)
+#define BCM_6338_PCMDMA_BASE		(0xdeadbeef)
+#define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
+#define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
 
 /*
  * 6345 register sets base address
@@ -158,10 +193,14 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE		(0xdeadbeef)
 #define BCM_6345_GPIO_BASE		(0xfffe0400)
 #define BCM_6345_SPI_BASE		(0xdeadbeef)
+#define BCM_6345_SPI2_BASE		(0xdeadbeef)
 #define BCM_6345_UDC0_BASE		(0xdeadbeef)
 #define BCM_6345_USBDMA_BASE		(0xfffe2800)
 #define BCM_6345_ENET0_BASE		(0xfffe1800)
 #define BCM_6345_ENETDMA_BASE		(0xfffe2800)
+#define BCM_6345_ENETDMAC_BASE		(0xfffe2900)
+#define BCM_6345_ENETDMAS_BASE		(0xfffe2a00)
+#define BCM_6345_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE		(0xfffe2028)
 #define BCM_6345_MPI_BASE		(0xdeadbeef)
 #define BCM_6345_OHCI0_BASE		(0xfffe2100)
@@ -176,6 +215,16 @@ enum bcm63xx_regs_set {
 #define BCM_6345_SDRAM_BASE		(0xfffe2300)
 #define BCM_6345_MEMC_BASE		(0xdeadbeef)
 #define BCM_6345_DDR_BASE		(0xdeadbeef)
+#define BCM_6345_M2M_BASE		(0xdeadbeef)
+#define BCM_6345_ATM_BASE		(0xdeadbeef)
+#define BCM_6345_XTM_BASE		(0xdeadbeef)
+#define BCM_6345_XTMDMA_BASE		(0xdeadbeef)
+#define BCM_6345_XTMDMAC_BASE		(0xdeadbeef)
+#define BCM_6345_XTMDMAS_BASE		(0xdeadbeef)
+#define BCM_6345_PCM_BASE		(0xdeadbeef)
+#define BCM_6345_PCMDMA_BASE		(0xdeadbeef)
+#define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
+#define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
 
 /*
  * 6348 register sets base address
@@ -188,6 +237,7 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE		(0xdeadbeef)
 #define BCM_6348_GPIO_BASE		(0xfffe0400)
 #define BCM_6348_SPI_BASE		(0xfffe0c00)
+#define BCM_6348_SPI2_BASE		(0xdeadbeef)
 #define BCM_6348_UDC0_BASE		(0xfffe1000)
 #define BCM_6348_OHCI0_BASE		(0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
@@ -195,14 +245,27 @@ enum bcm63xx_regs_set {
 #define BCM_6348_MPI_BASE		(0xfffe2000)
 #define BCM_6348_PCMCIA_BASE		(0xfffe2054)
 #define BCM_6348_SDRAM_REGS_BASE	(0xfffe2300)
+#define BCM_6348_M2M_BASE		(0xfffe2800)
 #define BCM_6348_DSL_BASE		(0xfffe3000)
 #define BCM_6348_ENET0_BASE		(0xfffe6000)
 #define BCM_6348_ENET1_BASE		(0xfffe6800)
 #define BCM_6348_ENETDMA_BASE		(0xfffe7000)
+#define BCM_6348_ENETDMAC_BASE		(0xfffe7100)
+#define BCM_6348_ENETDMAS_BASE		(0xfffe7200)
+#define BCM_6348_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6348_EHCI0_BASE		(0xdeadbeef)
 #define BCM_6348_SDRAM_BASE		(0xfffe2300)
 #define BCM_6348_MEMC_BASE		(0xdeadbeef)
 #define BCM_6348_DDR_BASE		(0xdeadbeef)
+#define BCM_6348_ATM_BASE		(0xfffe4000)
+#define BCM_6348_XTM_BASE		(0xdeadbeef)
+#define BCM_6348_XTMDMA_BASE		(0xdeadbeef)
+#define BCM_6348_XTMDMAC_BASE		(0xdeadbeef)
+#define BCM_6348_XTMDMAS_BASE		(0xdeadbeef)
+#define BCM_6348_PCM_BASE		(0xdeadbeef)
+#define BCM_6348_PCMDMA_BASE		(0xdeadbeef)
+#define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
+#define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
 
 /*
  * 6358 register sets base address
@@ -215,6 +278,7 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART1_BASE		(0xfffe0120)
 #define BCM_6358_GPIO_BASE		(0xfffe0080)
 #define BCM_6358_SPI_BASE		(0xdeadbeef)
+#define BCM_6358_SPI2_BASE		(0xfffe0800)
 #define BCM_6358_UDC0_BASE		(0xfffe0800)
 #define BCM_6358_OHCI0_BASE		(0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
@@ -222,14 +286,28 @@ enum bcm63xx_regs_set {
 #define BCM_6358_MPI_BASE		(0xfffe1000)
 #define BCM_6358_PCMCIA_BASE		(0xfffe1054)
 #define BCM_6358_SDRAM_REGS_BASE	(0xfffe2300)
+#define BCM_6358_M2M_BASE		(0xdeadbeef)
 #define BCM_6358_DSL_BASE		(0xfffe3000)
 #define BCM_6358_ENET0_BASE		(0xfffe4000)
 #define BCM_6358_ENET1_BASE		(0xfffe4800)
 #define BCM_6358_ENETDMA_BASE		(0xfffe5000)
+#define BCM_6358_ENETDMAC_BASE		(0xfffe5100)
+#define BCM_6358_ENETDMAS_BASE		(0xfffe5200)
+#define BCM_6358_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6358_EHCI0_BASE		(0xfffe1300)
 #define BCM_6358_SDRAM_BASE		(0xdeadbeef)
 #define BCM_6358_MEMC_BASE		(0xfffe1200)
 #define BCM_6358_DDR_BASE		(0xfffe12a0)
+#define BCM_6358_ATM_BASE		(0xfffe2000)
+#define BCM_6358_XTM_BASE		(0xdeadbeef)
+#define BCM_6358_XTMDMA_BASE		(0xdeadbeef)
+#define BCM_6358_XTMDMAC_BASE		(0xdeadbeef)
+#define BCM_6358_XTMDMAS_BASE		(0xdeadbeef)
+#define BCM_6358_PCM_BASE		(0xfffe1600)
+#define BCM_6358_PCMDMA_BASE		(0xfffe1800)
+#define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
+#define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
+
 
 
 extern const unsigned long *bcm63xx_regs_base;
@@ -248,6 +326,7 @@ extern const unsigned long *bcm63xx_regs_base;
 	__GEN_RSET_BASE(__cpu, UART1)					\
 	__GEN_RSET_BASE(__cpu, GPIO)					\
 	__GEN_RSET_BASE(__cpu, SPI)					\
+	__GEN_RSET_BASE(__cpu, SPI2)					\
 	__GEN_RSET_BASE(__cpu, UDC0)					\
 	__GEN_RSET_BASE(__cpu, OHCI0)					\
 	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
@@ -258,10 +337,23 @@ extern const unsigned long *bcm63xx_regs_base;
 	__GEN_RSET_BASE(__cpu, ENET0)					\
 	__GEN_RSET_BASE(__cpu, ENET1)					\
 	__GEN_RSET_BASE(__cpu, ENETDMA)					\
+	__GEN_RSET_BASE(__cpu, ENETDMAC)				\
+	__GEN_RSET_BASE(__cpu, ENETDMAS)				\
+	__GEN_RSET_BASE(__cpu, ENETSW)					\
 	__GEN_RSET_BASE(__cpu, EHCI0)					\
 	__GEN_RSET_BASE(__cpu, SDRAM)					\
 	__GEN_RSET_BASE(__cpu, MEMC)					\
 	__GEN_RSET_BASE(__cpu, DDR)					\
+	__GEN_RSET_BASE(__cpu, M2M)					\
+	__GEN_RSET_BASE(__cpu, ATM)					\
+	__GEN_RSET_BASE(__cpu, XTM)					\
+	__GEN_RSET_BASE(__cpu, XTMDMA)					\
+	__GEN_RSET_BASE(__cpu, XTMDMAC)					\
+	__GEN_RSET_BASE(__cpu, XTMDMAS)					\
+	__GEN_RSET_BASE(__cpu, PCM)					\
+	__GEN_RSET_BASE(__cpu, PCMDMA)					\
+	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
+	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
 	}
 
 #define __GEN_CPU_REGS_TABLE(__cpu)					\
@@ -273,6 +365,7 @@ extern const unsigned long *bcm63xx_regs_base;
 	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
 	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
 	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
+	[RSET_SPI2]		= BCM_## __cpu ##_SPI2_BASE,		\
 	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
 	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
 	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
@@ -283,10 +376,23 @@ extern const unsigned long *bcm63xx_regs_base;
 	[RSET_ENET0]		= BCM_## __cpu ##_ENET0_BASE,		\
 	[RSET_ENET1]		= BCM_## __cpu ##_ENET1_BASE,		\
 	[RSET_ENETDMA]		= BCM_## __cpu ##_ENETDMA_BASE,		\
+	[RSET_ENETDMAC]		= BCM_## __cpu ##_ENETDMAC_BASE,	\
+	[RSET_ENETDMAS]		= BCM_## __cpu ##_ENETDMAS_BASE,	\
+	[RSET_ENETSW]		= BCM_## __cpu ##_ENETSW_BASE,		\
 	[RSET_EHCI0]		= BCM_## __cpu ##_EHCI0_BASE,		\
 	[RSET_SDRAM]		= BCM_## __cpu ##_SDRAM_BASE,		\
 	[RSET_MEMC]		= BCM_## __cpu ##_MEMC_BASE,		\
 	[RSET_DDR]		= BCM_## __cpu ##_DDR_BASE,		\
+	[RSET_M2M]		= BCM_## __cpu ##_M2M_BASE,		\
+	[RSET_ATM]		= BCM_## __cpu ##_ATM_BASE,		\
+	[RSET_XTM]		= BCM_## __cpu ##_XTM_BASE,		\
+	[RSET_XTMDMA]		= BCM_## __cpu ##_XTMDMA_BASE,		\
+	[RSET_XTMDMAC]		= BCM_## __cpu ##_XTMDMAC_BASE,		\
+	[RSET_XTMDMAS]		= BCM_## __cpu ##_XTMDMAS_BASE,		\
+	[RSET_PCM]		= BCM_## __cpu ##_PCM_BASE,		\
+	[RSET_PCMDMA]		= BCM_## __cpu ##_PCMDMA_BASE,		\
+	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
+	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
 
 
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
@@ -330,6 +436,17 @@ enum bcm63xx_irq {
 	IRQ_ENET1_TXDMA,
 	IRQ_PCI,
 	IRQ_PCMCIA,
+	IRQ_ATM,
+	IRQ_ENETSW_RXDMA0,
+	IRQ_ENETSW_RXDMA1,
+	IRQ_ENETSW_RXDMA2,
+	IRQ_ENETSW_RXDMA3,
+	IRQ_ENETSW_TXDMA0,
+	IRQ_ENETSW_TXDMA1,
+	IRQ_ENETSW_TXDMA2,
+	IRQ_ENETSW_TXDMA3,
+	IRQ_XTM,
+	IRQ_XTM_DMA0,
 };
 
 /*
@@ -350,6 +467,17 @@ enum bcm63xx_irq {
 #define BCM_6338_ENET1_TXDMA_IRQ	0
 #define BCM_6338_PCI_IRQ		0
 #define BCM_6338_PCMCIA_IRQ		0
+#define BCM_6338_ATM_IRQ		0
+#define BCM_6338_ENETSW_RXDMA0_IRQ	0
+#define BCM_6338_ENETSW_RXDMA1_IRQ	0
+#define BCM_6338_ENETSW_RXDMA2_IRQ	0
+#define BCM_6338_ENETSW_RXDMA3_IRQ	0
+#define BCM_6338_ENETSW_TXDMA0_IRQ	0
+#define BCM_6338_ENETSW_TXDMA1_IRQ	0
+#define BCM_6338_ENETSW_TXDMA2_IRQ	0
+#define BCM_6338_ENETSW_TXDMA3_IRQ	0
+#define BCM_6338_XTM_IRQ		0
+#define BCM_6338_XTM_DMA0_IRQ		0
 
 /*
  * 6345 irqs
@@ -369,6 +497,17 @@ enum bcm63xx_irq {
 #define BCM_6345_ENET1_TXDMA_IRQ	0
 #define BCM_6345_PCI_IRQ		0
 #define BCM_6345_PCMCIA_IRQ		0
+#define BCM_6345_ATM_IRQ		0
+#define BCM_6345_ENETSW_RXDMA0_IRQ	0
+#define BCM_6345_ENETSW_RXDMA1_IRQ	0
+#define BCM_6345_ENETSW_RXDMA2_IRQ	0
+#define BCM_6345_ENETSW_RXDMA3_IRQ	0
+#define BCM_6345_ENETSW_TXDMA0_IRQ	0
+#define BCM_6345_ENETSW_TXDMA1_IRQ	0
+#define BCM_6345_ENETSW_TXDMA2_IRQ	0
+#define BCM_6345_ENETSW_TXDMA3_IRQ	0
+#define BCM_6345_XTM_IRQ		0
+#define BCM_6345_XTM_DMA0_IRQ		0
 
 /*
  * 6348 irqs
@@ -388,6 +527,17 @@ enum bcm63xx_irq {
 #define BCM_6348_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 23)
 #define BCM_6348_PCI_IRQ		(IRQ_INTERNAL_BASE + 24)
 #define BCM_6348_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
+#define BCM_6348_ATM_IRQ		(IRQ_INTERNAL_BASE + 5)
+#define BCM_6348_ENETSW_RXDMA0_IRQ	0
+#define BCM_6348_ENETSW_RXDMA1_IRQ	0
+#define BCM_6348_ENETSW_RXDMA2_IRQ	0
+#define BCM_6348_ENETSW_RXDMA3_IRQ	0
+#define BCM_6348_ENETSW_TXDMA0_IRQ	0
+#define BCM_6348_ENETSW_TXDMA1_IRQ	0
+#define BCM_6348_ENETSW_TXDMA2_IRQ	0
+#define BCM_6348_ENETSW_TXDMA3_IRQ	0
+#define BCM_6348_XTM_IRQ		0
+#define BCM_6348_XTM_DMA0_IRQ		0
 
 /*
  * 6358 irqs
@@ -407,6 +557,24 @@ enum bcm63xx_irq {
 #define BCM_6358_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 18)
 #define BCM_6358_PCI_IRQ		(IRQ_INTERNAL_BASE + 31)
 #define BCM_6358_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_ATM_IRQ		(IRQ_INTERNAL_BASE + 19)
+#define BCM_6358_ENETSW_RXDMA0_IRQ	0
+#define BCM_6358_ENETSW_RXDMA1_IRQ	0
+#define BCM_6358_ENETSW_RXDMA2_IRQ	0
+#define BCM_6358_ENETSW_RXDMA3_IRQ	0
+#define BCM_6358_ENETSW_TXDMA0_IRQ	0
+#define BCM_6358_ENETSW_TXDMA1_IRQ	0
+#define BCM_6358_ENETSW_TXDMA2_IRQ	0
+#define BCM_6358_ENETSW_TXDMA3_IRQ	0
+#define BCM_6358_XTM_IRQ		0
+#define BCM_6358_XTM_DMA0_IRQ		0
+
+#define BCM_6358_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 23)
+#define BCM_6358_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 24)
+#define BCM_6358_EXT_IRQ0		(IRQ_INTERNAL_BASE + 25)
+#define BCM_6358_EXT_IRQ1		(IRQ_INTERNAL_BASE + 26)
+#define BCM_6358_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
+#define BCM_6358_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)
 
 extern const int *bcm63xx_irqs;
 
@@ -426,6 +594,17 @@ extern const int *bcm63xx_irqs;
 	[IRQ_ENET1_TXDMA]	= BCM_## __cpu ##_ENET1_TXDMA_IRQ,	\
 	[IRQ_PCI]		= BCM_## __cpu ##_PCI_IRQ,		\
 	[IRQ_PCMCIA]		= BCM_## __cpu ##_PCMCIA_IRQ,		\
+	[IRQ_ATM]		= BCM_## __cpu ##_ATM_IRQ,		\
+	[IRQ_ENETSW_RXDMA0]	= BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,	\
+	[IRQ_ENETSW_RXDMA1]	= BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,	\
+	[IRQ_ENETSW_RXDMA2]	= BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,	\
+	[IRQ_ENETSW_RXDMA3]	= BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,	\
+	[IRQ_ENETSW_TXDMA0]	= BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,	\
+	[IRQ_ENETSW_TXDMA1]	= BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,	\
+	[IRQ_ENETSW_TXDMA2]	= BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,	\
+	[IRQ_ENETSW_TXDMA3]	= BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,	\
+	[IRQ_XTM]		= BCM_## __cpu ##_XTM_IRQ,		\
+	[IRQ_XTM_DMA0]		= BCM_## __cpu ##_XTM_DMA0_IRQ,		\
 
 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 {
@@ -437,4 +616,8 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
  */
 unsigned int bcm63xx_get_memory_size(void);
 
+void bcm63xx_machine_halt(void);
+
+void bcm63xx_machine_reboot(void);
+
 #endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0ed5230..3ea2681 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -548,6 +548,56 @@
 
 
 /*************************************************************************
+ * _REG relative to RSET_ENETDMAC
+ *************************************************************************/
+
+/* Channel Configuration register */
+#define ENETDMAC_CHANCFG_REG(x)		((x) * 0x10)
+#define ENETDMAC_CHANCFG_EN_SHIFT	0
+#define ENETDMAC_CHANCFG_EN_MASK	(1 << ENETDMA_CHANCFG_EN_SHIFT)
+#define ENETDMAC_CHANCFG_PKTHALT_SHIFT	1
+#define ENETDMAC_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
+
+/* Interrupt Control/Status register */
+#define ENETDMAC_IR_REG(x)		(0x4 + (x) * 0x10)
+#define ENETDMAC_IR_BUFDONE_MASK	(1 << 0)
+#define ENETDMAC_IR_PKTDONE_MASK	(1 << 1)
+#define ENETDMAC_IR_NOTOWNER_MASK	(1 << 2)
+
+/* Interrupt Mask register */
+#define ENETDMAC_IRMASK_REG(x)		(0x8 + (x) * 0x10)
+
+/* Maximum Burst Length */
+#define ENETDMAC_MAXBURST_REG(x)	(0xc + (x) * 0x10)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETDMAS
+ *************************************************************************/
+
+/* Ring Start Address register */
+#define ENETDMAS_RSTART_REG(x)		((x) * 0x10)
+
+/* State Ram Word 2 */
+#define ENETDMAS_SRAM2_REG(x)		(0x4 + (x) * 0x10)
+
+/* State Ram Word 3 */
+#define ENETDMAS_SRAM3_REG(x)		(0x8 + (x) * 0x10)
+
+/* State Ram Word 4 */
+#define ENETDMAS_SRAM4_REG(x)		(0xc + (x) * 0x10)
+
+
+/*************************************************************************
+ * _REG relative to RSET_ENETSW
+ *************************************************************************/
+
+/* MIB register */
+#define ENETSW_MIB_REG(x)		(0x2800 + (x) * 4)
+#define ENETSW_MIB_REG_COUNT		47
+
+
+/*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
  *************************************************************************/
 
@@ -768,4 +818,32 @@
 #define DMIPSPLLCFG_N2_SHIFT		29
 #define DMIPSPLLCFG_N2_MASK		(0x7 << DMIPSPLLCFG_N2_SHIFT)
 
+/*************************************************************************
+ * _REG relative to RSET_M2M
+ *************************************************************************/
+
+#define M2M_RX				0
+#define M2M_TX				1
+
+#define M2M_SRC_REG(x)			((x) * 0x40 + 0x00)
+#define M2M_DST_REG(x)			((x) * 0x40 + 0x04)
+#define M2M_SIZE_REG(x)			((x) * 0x40 + 0x08)
+
+#define M2M_CTRL_REG(x)			((x) * 0x40 + 0x0c)
+#define M2M_CTRL_ENABLE_MASK		(1 << 0)
+#define M2M_CTRL_IRQEN_MASK		(1 << 1)
+#define M2M_CTRL_ERROR_CLR_MASK		(1 << 6)
+#define M2M_CTRL_DONE_CLR_MASK		(1 << 7)
+#define M2M_CTRL_NOINC_MASK		(1 << 8)
+#define M2M_CTRL_PCMCIASWAP_MASK	(1 << 9)
+#define M2M_CTRL_SWAPBYTE_MASK		(1 << 10)
+#define M2M_CTRL_ENDIAN_MASK		(1 << 11)
+
+#define M2M_STAT_REG(x)			((x) * 0x40 + 0x10)
+#define M2M_STAT_DONE			(1 << 0)
+#define M2M_STAT_ERROR			(1 << 1)
+
+#define M2M_SRCID_REG(x)		((x) * 0x40 + 0x14)
+#define M2M_DSTID_REG(x)		((x) * 0x40 + 0x18)
+
 #endif /* BCM63XX_REGS_H_ */
-- 
1.7.1.1

[PATCH 07/11] MIPS: BCM63XX: change irq code to prepare for per-cpu peculiarity.

[Maxime Bizon]

No functionnal change is introduced by this patch.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/irq.c                           |   86 ++++++++++++++++++--
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    9 ++
 2 files changed, 86 insertions(+), 9 deletions(-)

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index cea6021..d002831 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -19,19 +19,86 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_irq.h>
 
+static void __dispatch_internal(void) __maybe_unused;
+
+#ifndef BCMCPU_RUNTIME_DETECT
+#ifdef CONFIG_BCM63XX_CPU_6338
+#define irq_stat_reg		PERF_IRQSTAT_6338_REG
+#define irq_mask_reg		PERF_IRQMASK_6338_REG
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6345
+#define irq_stat_reg		PERF_IRQSTAT_6345_REG
+#define irq_mask_reg		PERF_IRQMASK_6345_REG
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+#define irq_stat_reg		PERF_IRQSTAT_6348_REG
+#define irq_mask_reg		PERF_IRQMASK_6348_REG
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+#define irq_stat_reg		PERF_IRQSTAT_6358_REG
+#define irq_mask_reg		PERF_IRQMASK_6358_REG
+#endif
+
+#define dispatch_internal	__dispatch_internal
+
+#define irq_stat_addr	(bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
+#define irq_mask_addr	(bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
+
+static inline void bcm63xx_init_irq(void)
+{
+}
+#else /* ! BCMCPU_RUNTIME_DETECT */
+
+static u32 irq_stat_addr, irq_mask_addr;
+static void (*dispatch_internal)(void);
+
+static void bcm63xx_init_irq(void)
+{
+	irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
+	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
+
+	switch (bcm63xx_get_cpu_id()) {
+	case BCM6338_CPU_ID:
+		irq_stat_addr += PERF_IRQSTAT_6338_REG;
+		irq_mask_addr += PERF_IRQMASK_6338_REG;
+		break;
+	case BCM6345_CPU_ID:
+		irq_stat_addr += PERF_IRQSTAT_6345_REG;
+		irq_mask_addr += PERF_IRQMASK_6345_REG;
+		break;
+	case BCM6348_CPU_ID:
+		irq_stat_addr += PERF_IRQSTAT_6348_REG;
+		irq_mask_addr += PERF_IRQMASK_6348_REG;
+		break;
+	case BCM6358_CPU_ID:
+		irq_stat_addr += PERF_IRQSTAT_6358_REG;
+		irq_mask_addr += PERF_IRQMASK_6358_REG;
+		break;
+	default:
+		BUG();
+	}
+
+	dispatch_internal = __dispatch_internal;
+}
+#endif /* ! BCMCPU_RUNTIME_DETECT */
+
+static inline void handle_internal(int intbit)
+{
+	do_IRQ(intbit + IRQ_INTERNAL_BASE);
+}
+
 /*
  * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  * prioritize any interrupt relatively to another. the static counter
  * will resume the loop where it ended the last time we left this
  * function.
  */
-static void bcm63xx_irq_dispatch_internal(void)
+static void __dispatch_internal(void)
 {
 	u32 pending;
 	static int i;
 
-	pending = bcm_perf_readl(PERF_IRQMASK_REG) &
-		bcm_perf_readl(PERF_IRQSTAT_REG);
+	pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
 
 	if (!pending)
 		return ;
@@ -41,7 +108,7 @@ static void bcm63xx_irq_dispatch_internal(void)
 
 		i = (i + 1) & 0x1f;
 		if (pending & (1 << to_call)) {
-			do_IRQ(to_call + IRQ_INTERNAL_BASE);
+			handle_internal(to_call);
 			break;
 		}
 	}
@@ -60,7 +127,7 @@ asmlinkage void plat_irq_dispatch(void)
 		if (cause & CAUSEF_IP7)
 			do_IRQ(7);
 		if (cause & CAUSEF_IP2)
-			bcm63xx_irq_dispatch_internal();
+			dispatch_internal();
 		if (cause & CAUSEF_IP3)
 			do_IRQ(IRQ_EXT_0);
 		if (cause & CAUSEF_IP4)
@@ -81,9 +148,9 @@ static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
 	unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
 	u32 mask;
 
-	mask = bcm_perf_readl(PERF_IRQMASK_REG);
+	mask = bcm_readl(irq_mask_addr);
 	mask &= ~(1 << irq);
-	bcm_perf_writel(mask, PERF_IRQMASK_REG);
+	bcm_writel(mask, irq_mask_addr);
 }
 
 static void bcm63xx_internal_irq_unmask(struct irq_data *d)
@@ -91,9 +158,9 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
 	unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
 	u32 mask;
 
-	mask = bcm_perf_readl(PERF_IRQMASK_REG);
+	mask = bcm_readl(irq_mask_addr);
 	mask |= (1 << irq);
-	bcm_perf_writel(mask, PERF_IRQMASK_REG);
+	bcm_writel(mask, irq_mask_addr);
 }
 
 /*
@@ -228,6 +295,7 @@ void __init arch_init_irq(void)
 {
 	int i;
 
+	bcm63xx_init_irq();
 	mips_cpu_irq_init();
 	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
 		irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3ea2681..4354be1 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -89,9 +89,18 @@
 
 /* Interrupt Mask register */
 #define PERF_IRQMASK_REG		0xc
+#define PERF_IRQSTAT_REG		0x10
+#define PERF_IRQMASK_6338_REG		0xc
+#define PERF_IRQMASK_6345_REG		0xc
+#define PERF_IRQMASK_6348_REG		0xc
+#define PERF_IRQMASK_6358_REG		0xc
 
 /* Interrupt Status register */
 #define PERF_IRQSTAT_REG		0x10
+#define PERF_IRQSTAT_6338_REG		0x10
+#define PERF_IRQSTAT_6345_REG		0x10
+#define PERF_IRQSTAT_6348_REG		0x10
+#define PERF_IRQSTAT_6358_REG		0x10
 
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG		0x14
-- 
1.7.1.1

[PATCH 08/11] MIPS: BCM63XX: prepare irq code to handle different external irq hardware implementation.

[Maxime Bizon]

External irq only works for 6348, change code to prepare support of
other CPUs.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/irq.c |   77 ++++++++++++++++++++++++++++++++++++----------
 1 files changed, 60 insertions(+), 17 deletions(-)

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index d002831..2e4f317 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -25,18 +25,32 @@ static void __dispatch_internal(void) __maybe_unused;
 #ifdef CONFIG_BCM63XX_CPU_6338
 #define irq_stat_reg		PERF_IRQSTAT_6338_REG
 #define irq_mask_reg		PERF_IRQMASK_6338_REG
+#define is_ext_irq_cascaded	0
+#define ext_irq_start		0
+#define ext_irq_end		0
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
 #define irq_stat_reg		PERF_IRQSTAT_6345_REG
 #define irq_mask_reg		PERF_IRQMASK_6345_REG
+#define is_ext_irq_cascaded	0
+#define ext_irq_start		0
+#define ext_irq_end		0
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
 #define irq_stat_reg		PERF_IRQSTAT_6348_REG
 #define irq_mask_reg		PERF_IRQMASK_6348_REG
+#define dispatch_internal	__dispatch_internal
+#define is_ext_irq_cascaded	0
+#define ext_irq_start		0
+#define ext_irq_end		0
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6358
 #define irq_stat_reg		PERF_IRQSTAT_6358_REG
 #define irq_mask_reg		PERF_IRQMASK_6358_REG
+#define dispatch_internal	__dispatch_internal
+#define is_ext_irq_cascaded	1
+#define ext_irq_start		(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end		(BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
 #endif
 
 #define dispatch_internal	__dispatch_internal
@@ -51,6 +65,8 @@ static inline void bcm63xx_init_irq(void)
 
 static u32 irq_stat_addr, irq_mask_addr;
 static void (*dispatch_internal)(void);
+static int is_ext_irq_cascaded;
+static unsigned int ext_irq_start, ext_irq_end;
 
 static void bcm63xx_init_irq(void)
 {
@@ -73,6 +89,9 @@ static void bcm63xx_init_irq(void)
 	case BCM6358_CPU_ID:
 		irq_stat_addr += PERF_IRQSTAT_6358_REG;
 		irq_mask_addr += PERF_IRQMASK_6358_REG;
+		is_ext_irq_cascaded = 1;
+		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 		break;
 	default:
 		BUG();
@@ -84,7 +103,11 @@ static void bcm63xx_init_irq(void)
 
 static inline void handle_internal(int intbit)
 {
-	do_IRQ(intbit + IRQ_INTERNAL_BASE);
+	if (is_ext_irq_cascaded &&
+	    intbit >= ext_irq_start && intbit <= ext_irq_end)
+		do_IRQ(intbit - ext_irq_start + IRQ_EXT_BASE);
+	else
+		do_IRQ(intbit + IRQ_INTERNAL_BASE);
 }
 
 /*
@@ -128,14 +151,16 @@ asmlinkage void plat_irq_dispatch(void)
 			do_IRQ(7);
 		if (cause & CAUSEF_IP2)
 			dispatch_internal();
-		if (cause & CAUSEF_IP3)
-			do_IRQ(IRQ_EXT_0);
-		if (cause & CAUSEF_IP4)
-			do_IRQ(IRQ_EXT_1);
-		if (cause & CAUSEF_IP5)
-			do_IRQ(IRQ_EXT_2);
-		if (cause & CAUSEF_IP6)
-			do_IRQ(IRQ_EXT_3);
+		if (!is_ext_irq_cascaded) {
+			if (cause & CAUSEF_IP3)
+				do_IRQ(IRQ_EXT_0);
+			if (cause & CAUSEF_IP4)
+				do_IRQ(IRQ_EXT_1);
+			if (cause & CAUSEF_IP5)
+				do_IRQ(IRQ_EXT_2);
+			if (cause & CAUSEF_IP6)
+				do_IRQ(IRQ_EXT_3);
+		}
 	} while (1);
 }
 
@@ -143,9 +168,8 @@ asmlinkage void plat_irq_dispatch(void)
  * internal IRQs operations: only mask/unmask on PERF irq mask
  * register.
  */
-static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
+static void internal_irq_mask(unsigned int irq)
 {
-	unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
 	u32 mask;
 
 	mask = bcm_readl(irq_mask_addr);
@@ -153,9 +177,8 @@ static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
 	bcm_writel(mask, irq_mask_addr);
 }
 
-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+static void internal_irq_unmask(unsigned int irq)
 {
-	unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
 	u32 mask;
 
 	mask = bcm_readl(irq_mask_addr);
@@ -163,6 +186,16 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
 	bcm_writel(mask, irq_mask_addr);
 }
 
+static void bcm63xx_internal_irq_mask(struct irq_data *d)
+{
+	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
+}
+
+static void bcm63xx_internal_irq_unmask(struct irq_data *d)
+{
+	internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
+}
+
 /*
  * external IRQs operations: mask/unmask and clear on PERF external
  * irq control register.
@@ -175,6 +208,8 @@ static void bcm63xx_external_irq_mask(struct irq_data *d)
 	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
 	reg &= ~EXTIRQ_CFG_MASK(irq);
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+	if (is_ext_irq_cascaded)
+		internal_irq_mask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_unmask(struct irq_data *d)
@@ -185,6 +220,8 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d)
 	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
 	reg |= EXTIRQ_CFG_MASK(irq);
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+	if (is_ext_irq_cascaded)
+		internal_irq_unmask(irq + ext_irq_start);
 }
 
 static void bcm63xx_external_irq_clear(struct irq_data *d)
@@ -195,12 +232,16 @@ static void bcm63xx_external_irq_clear(struct irq_data *d)
 	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
 	reg |= EXTIRQ_CFG_CLEAR(irq);
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+	if (is_ext_irq_cascaded)
+		internal_irq_mask(irq + ext_irq_start);
 }
 
 static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
 {
-	set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-	irq_enable_hazard();
+	if (!is_ext_irq_cascaded) {
+		set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
+		irq_enable_hazard();
+	}
 	bcm63xx_external_irq_unmask(d);
 	return 0;
 }
@@ -208,8 +249,10 @@ static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
 static void bcm63xx_external_irq_shutdown(struct irq_data *d)
 {
 	bcm63xx_external_irq_mask(d);
-	clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
-	irq_disable_hazard();
+	if (!is_ext_irq_cascaded) {
+		clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
+		irq_disable_hazard();
+	}
 }
 
 static int bcm63xx_external_irq_set_type(struct irq_data *d,
-- 
1.7.1.1

[PATCH 09/11] MIPS: BCM63XX: handle 64 bits irq stat register in irq code.

[Maxime Bizon]

bcm6368 has larger irq registers, prepare for this.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/irq.c |   82 +++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 2e4f317..07909a9 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -20,11 +20,17 @@
 #include <bcm63xx_irq.h>
 
 static void __dispatch_internal(void) __maybe_unused;
+static void __dispatch_internal_64(void) __maybe_unused;
+static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
+static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 
 #ifndef BCMCPU_RUNTIME_DETECT
 #ifdef CONFIG_BCM63XX_CPU_6338
 #define irq_stat_reg		PERF_IRQSTAT_6338_REG
 #define irq_mask_reg		PERF_IRQMASK_6338_REG
+#define irq_bits		32
 #define is_ext_irq_cascaded	0
 #define ext_irq_start		0
 #define ext_irq_end		0
@@ -32,6 +38,7 @@ static void __dispatch_internal(void) __maybe_unused;
 #ifdef CONFIG_BCM63XX_CPU_6345
 #define irq_stat_reg		PERF_IRQSTAT_6345_REG
 #define irq_mask_reg		PERF_IRQMASK_6345_REG
+#define irq_bits		32
 #define is_ext_irq_cascaded	0
 #define ext_irq_start		0
 #define ext_irq_end		0
@@ -39,7 +46,7 @@ static void __dispatch_internal(void) __maybe_unused;
 #ifdef CONFIG_BCM63XX_CPU_6348
 #define irq_stat_reg		PERF_IRQSTAT_6348_REG
 #define irq_mask_reg		PERF_IRQMASK_6348_REG
-#define dispatch_internal	__dispatch_internal
+#define irq_bits		32
 #define is_ext_irq_cascaded	0
 #define ext_irq_start		0
 #define ext_irq_end		0
@@ -47,13 +54,21 @@ static void __dispatch_internal(void) __maybe_unused;
 #ifdef CONFIG_BCM63XX_CPU_6358
 #define irq_stat_reg		PERF_IRQSTAT_6358_REG
 #define irq_mask_reg		PERF_IRQMASK_6358_REG
-#define dispatch_internal	__dispatch_internal
+#define irq_bits		32
 #define is_ext_irq_cascaded	1
 #define ext_irq_start		(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
 #define ext_irq_end		(BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
 #endif
 
-#define dispatch_internal	__dispatch_internal
+#if irq_bits == 32
+#define dispatch_internal			__dispatch_internal
+#define internal_irq_mask			__internal_irq_mask_32
+#define internal_irq_unmask			__internal_irq_unmask_32
+#else
+#define dispatch_internal			__dispatch_internal_64
+#define internal_irq_mask			__internal_irq_mask_64
+#define internal_irq_unmask			__internal_irq_unmask_64
+#endif
 
 #define irq_stat_addr	(bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
 #define irq_mask_addr	(bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
@@ -67,9 +82,13 @@ static u32 irq_stat_addr, irq_mask_addr;
 static void (*dispatch_internal)(void);
 static int is_ext_irq_cascaded;
 static unsigned int ext_irq_start, ext_irq_end;
+static void (*internal_irq_mask)(unsigned int irq);
+static void (*internal_irq_unmask)(unsigned int irq);
 
 static void bcm63xx_init_irq(void)
 {
+	int irq_bits;
+
 	irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
 	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
 
@@ -77,18 +96,22 @@ static void bcm63xx_init_irq(void)
 	case BCM6338_CPU_ID:
 		irq_stat_addr += PERF_IRQSTAT_6338_REG;
 		irq_mask_addr += PERF_IRQMASK_6338_REG;
+		irq_bits = 32;
 		break;
 	case BCM6345_CPU_ID:
 		irq_stat_addr += PERF_IRQSTAT_6345_REG;
 		irq_mask_addr += PERF_IRQMASK_6345_REG;
+		irq_bits = 32;
 		break;
 	case BCM6348_CPU_ID:
 		irq_stat_addr += PERF_IRQSTAT_6348_REG;
 		irq_mask_addr += PERF_IRQMASK_6348_REG;
+		irq_bits = 32;
 		break;
 	case BCM6358_CPU_ID:
 		irq_stat_addr += PERF_IRQSTAT_6358_REG;
 		irq_mask_addr += PERF_IRQMASK_6358_REG;
+		irq_bits = 32;
 		is_ext_irq_cascaded = 1;
 		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
@@ -97,7 +120,15 @@ static void bcm63xx_init_irq(void)
 		BUG();
 	}
 
-	dispatch_internal = __dispatch_internal;
+	if (irq_bits == 32) {
+		dispatch_internal = __dispatch_internal;
+		internal_irq_mask = __internal_irq_mask_32;
+		internal_irq_unmask = __internal_irq_unmask_32;
+	} else {
+		dispatch_internal = __dispatch_internal_64;
+		internal_irq_mask = __internal_irq_mask_64;
+		internal_irq_unmask = __internal_irq_unmask_64;
+	}
 }
 #endif /* ! BCMCPU_RUNTIME_DETECT */
 
@@ -137,6 +168,27 @@ static void __dispatch_internal(void)
 	}
 }
 
+static void __dispatch_internal_64(void)
+{
+	u64 pending;
+	static int i;
+
+	pending = bcm_readll(irq_stat_addr) & bcm_readll(irq_mask_addr);
+
+	if (!pending)
+		return ;
+
+	while (1) {
+		int to_call = i;
+
+		i = (i + 1) & 0x3f;
+		if (pending & (1ull << to_call)) {
+			handle_internal(to_call);
+			break;
+		}
+	}
+}
+
 asmlinkage void plat_irq_dispatch(void)
 {
 	u32 cause;
@@ -168,7 +220,7 @@ asmlinkage void plat_irq_dispatch(void)
  * internal IRQs operations: only mask/unmask on PERF irq mask
  * register.
  */
-static void internal_irq_mask(unsigned int irq)
+static void __internal_irq_mask_32(unsigned int irq)
 {
 	u32 mask;
 
@@ -177,7 +229,16 @@ static void internal_irq_mask(unsigned int irq)
 	bcm_writel(mask, irq_mask_addr);
 }
 
-static void internal_irq_unmask(unsigned int irq)
+static void __internal_irq_mask_64(unsigned int irq)
+{
+	u64 mask;
+
+	mask = bcm_readll(irq_mask_addr);
+	mask &= ~(1ull << irq);
+	bcm_writell(mask, irq_mask_addr);
+}
+
+static void __internal_irq_unmask_32(unsigned int irq)
 {
 	u32 mask;
 
@@ -186,6 +247,15 @@ static void internal_irq_unmask(unsigned int irq)
 	bcm_writel(mask, irq_mask_addr);
 }
 
+static void __internal_irq_unmask_64(unsigned int irq)
+{
+	u64 mask;
+
+	mask = bcm_readll(irq_mask_addr);
+	mask |= (1ull << irq);
+	bcm_writell(mask, irq_mask_addr);
+}
+
 static void bcm63xx_internal_irq_mask(struct irq_data *d)
 {
 	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
-- 
1.7.1.1

[PATCH 10/11] MIPS: BCM63XX: add external irq support for non 6348 CPUs.

[Maxime Bizon]

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/irq.c                           |   74 ++++++++++++++++-----
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   20 ++++--
 2 files changed, 73 insertions(+), 21 deletions(-)

diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 07909a9..f2d5e30 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -276,7 +276,12 @@ static void bcm63xx_external_irq_mask(struct irq_data *d)
 	u32 reg;
 
 	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-	reg &= ~EXTIRQ_CFG_MASK(irq);
+
+	if (BCMCPU_IS_6348())
+		reg &= ~EXTIRQ_CFG_MASK_6348(irq);
+	else
+		reg &= ~EXTIRQ_CFG_MASK(irq);
+
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 	if (is_ext_irq_cascaded)
 		internal_irq_mask(irq + ext_irq_start);
@@ -288,7 +293,12 @@ static void bcm63xx_external_irq_unmask(struct irq_data *d)
 	u32 reg;
 
 	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-	reg |= EXTIRQ_CFG_MASK(irq);
+
+	if (BCMCPU_IS_6348())
+		reg |= EXTIRQ_CFG_MASK_6348(irq);
+	else
+		reg |= EXTIRQ_CFG_MASK(irq);
+
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 	if (is_ext_irq_cascaded)
 		internal_irq_unmask(irq + ext_irq_start);
@@ -300,7 +310,12 @@ static void bcm63xx_external_irq_clear(struct irq_data *d)
 	u32 reg;
 
 	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
-	reg |= EXTIRQ_CFG_CLEAR(irq);
+
+	if (BCMCPU_IS_6348())
+		reg |= EXTIRQ_CFG_CLEAR_6348(irq);
+	else
+		reg |= EXTIRQ_CFG_CLEAR(irq);
+
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 	if (is_ext_irq_cascaded)
 		internal_irq_mask(irq + ext_irq_start);
@@ -330,45 +345,72 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
 {
 	unsigned int irq = d->irq - IRQ_EXT_BASE;
 	u32 reg;
+	int levelsense, sense, bothedge;
 
 	flow_type &= IRQ_TYPE_SENSE_MASK;
 
 	if (flow_type == IRQ_TYPE_NONE)
 		flow_type = IRQ_TYPE_LEVEL_LOW;
 
-	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+	levelsense = sense = bothedge = 0;
 	switch (flow_type) {
 	case IRQ_TYPE_EDGE_BOTH:
-		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-		reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+		bothedge = 1;
 		break;
 
 	case IRQ_TYPE_EDGE_RISING:
-		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-		reg |= EXTIRQ_CFG_SENSE(irq);
-		reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+		sense = 1;
 		break;
 
 	case IRQ_TYPE_EDGE_FALLING:
-		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-		reg &= ~EXTIRQ_CFG_SENSE(irq);
-		reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_HIGH:
-		reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-		reg |= EXTIRQ_CFG_SENSE(irq);
+		levelsense = 1;
+		sense = 1;
 		break;
 
 	case IRQ_TYPE_LEVEL_LOW:
-		reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-		reg &= ~EXTIRQ_CFG_SENSE(irq);
+		levelsense = 1;
 		break;
 
 	default:
 		printk(KERN_ERR "bogus flow type combination given !\n");
 		return -EINVAL;
 	}
+
+	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+
+	if (BCMCPU_IS_6348()) {
+		if (levelsense)
+			reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
+		else
+			reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
+		if (sense)
+			reg |= EXTIRQ_CFG_SENSE_6348(irq);
+		else
+			reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
+		if (bothedge)
+			reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
+		else
+			reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
+	}
+
+	if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+		if (levelsense)
+			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+		else
+			reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+		if (sense)
+			reg |= EXTIRQ_CFG_SENSE(irq);
+		else
+			reg &= ~EXTIRQ_CFG_SENSE(irq);
+		if (bothedge)
+			reg |= EXTIRQ_CFG_BOTHEDGE(irq);
+		else
+			reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
+	}
+
 	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 
 	irqd_set_trigger_type(d, flow_type);
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 4354be1..0fa613c 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -104,12 +104,22 @@
 
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG		0x14
+
+/* for 6348 only */
+#define EXTIRQ_CFG_SENSE_6348(x)	(1 << (x))
+#define EXTIRQ_CFG_STAT_6348(x)		(1 << (x + 5))
+#define EXTIRQ_CFG_CLEAR_6348(x)	(1 << (x + 10))
+#define EXTIRQ_CFG_MASK_6348(x)		(1 << (x + 15))
+#define EXTIRQ_CFG_BOTHEDGE_6348(x)	(1 << (x + 20))
+#define EXTIRQ_CFG_LEVELSENSE_6348(x)	(1 << (x + 25))
+
+/* for all others */
 #define EXTIRQ_CFG_SENSE(x)		(1 << (x))
-#define EXTIRQ_CFG_STAT(x)		(1 << (x + 5))
-#define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 10))
-#define EXTIRQ_CFG_MASK(x)		(1 << (x + 15))
-#define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 20))
-#define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 25))
+#define EXTIRQ_CFG_STAT(x)		(1 << (x + 4))
+#define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 8))
+#define EXTIRQ_CFG_MASK(x)		(1 << (x + 12))
+#define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 16))
+#define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 20))
 
 #define EXTIRQ_CFG_CLEAR_ALL		(0xf << 10)
 #define EXTIRQ_CFG_MASK_ALL		(0xf << 15)
-- 
1.7.1.1

[PATCH 11/11] MIPS: BCM63XX: add support for bcm6368 CPU.

[Maxime Bizon]

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
---
 arch/mips/bcm63xx/Kconfig                         |    4 +
 arch/mips/bcm63xx/clk.c                           |   70 +++++++++++++-
 arch/mips/bcm63xx/cpu.c                           |   76 ++++++++++++---
 arch/mips/bcm63xx/dev-uart.c                      |    2 +-
 arch/mips/bcm63xx/irq.c                           |   16 +++
 arch/mips/bcm63xx/prom.c                          |    7 +-
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   99 +++++++++++++++++++
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  106 ++++++++++++++++++++-
 arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    4 +
 arch/mips/pci/pci-bcm63xx.c                       |    4 +-
 11 files changed, 364 insertions(+), 26 deletions(-)

diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index fb177d6..6b1b9ad 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
 config BCM63XX_CPU_6358
 	bool "support 6358 CPU"
 	select HW_HAS_PCI
+
+config BCM63XX_CPU_6368
+	bool "support 6368 CPU"
+	select HW_HAS_PCI
 endmenu
 
 source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9..9d57c71 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/clk.h>
+#include <linux/delay.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
 };
 
 /*
+ * Ethernet switch clock
+ */
+static void enetsw_set(struct clk *clk, int enable)
+{
+	if (!BCMCPU_IS_6368())
+		return;
+	bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
+			CKCTL_6368_SWPKT_USB_EN |
+			CKCTL_6368_SWPKT_SAR_EN, enable);
+	if (enable) {
+		u32 val;
+
+		/* reset switch core afer clock change */
+		val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+		val &= ~SOFTRESET_6368_ENETSW_MASK;
+		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+		msleep(10);
+		val |= SOFTRESET_6368_ENETSW_MASK;
+		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+		msleep(10);
+	}
+}
+
+static struct clk clk_enetsw = {
+	.set	= enetsw_set,
+};
+
+/*
  * PCM clock
  */
 static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-	if (!BCMCPU_IS_6348())
-		return;
-	bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+	if (BCMCPU_IS_6348())
+		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
+	else if (BCMCPU_IS_6368())
+		bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
 };
 
 /*
+ * XTM clock
+ */
+static void xtm_set(struct clk *clk, int enable)
+{
+	if (!BCMCPU_IS_6368())
+		return;
+
+	bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
+			CKCTL_6368_SWPKT_SAR_EN, enable);
+
+	if (enable) {
+		u32 val;
+
+		/* reset sar core afer clock change */
+		val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
+		val &= ~SOFTRESET_6368_SAR_MASK;
+		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+		mdelay(1);
+		val |= SOFTRESET_6368_SAR_MASK;
+		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
+		mdelay(1);
+	}
+}
+
+
+static struct clk clk_xtm = {
+	.set	= xtm_set,
+};
+
+/*
  * Internal peripheral clock
  */
 static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
 		return &clk_enet0;
 	if (!strcmp(id, "enet1"))
 		return &clk_enet1;
+	if (!strcmp(id, "enetsw"))
+		return &clk_enetsw;
 	if (!strcmp(id, "ephy"))
 		return &clk_ephy;
 	if (!strcmp(id, "usbh"))
 		return &clk_usbh;
 	if (!strcmp(id, "spi"))
 		return &clk_spi;
+	if (!strcmp(id, "xtm"))
+		return &clk_xtm;
 	if (!strcmp(id, "periph"))
 		return &clk_periph;
 	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 027ac30..3ea2533 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -66,6 +66,15 @@ static const int bcm96358_irqs[] = {
 
 };
 
+static const unsigned long bcm96368_regs_base[] = {
+	__GEN_CPU_REGS_TABLE(6368)
+};
+
+static const int bcm96368_irqs[] = {
+	__GEN_CPU_IRQ_TABLE(6368)
+
+};
+
 u16 __bcm63xx_get_cpu_id(void)
 {
 	return bcm63xx_cpu_id;
@@ -92,20 +101,19 @@ unsigned int bcm63xx_get_memory_size(void)
 
 static unsigned int detect_cpu_clock(void)
 {
-	unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
-
-	/* BCM6338 has a fixed 240 Mhz frequency */
-	if (BCMCPU_IS_6338())
+	switch (bcm63xx_get_cpu_id()) {
+	case BCM6338_CPU_ID:
+		/* BCM6338 has a fixed 240 Mhz frequency */
 		return 240000000;
 
-	/* BCM6345 has a fixed 140Mhz frequency */
-	if (BCMCPU_IS_6345())
+	case BCM6345_CPU_ID:
+		/* BCM6345 has a fixed 140Mhz frequency */
 		return 140000000;
 
-	/*
-	 * frequency depends on PLL configuration:
-	 */
-	if (BCMCPU_IS_6348()) {
+	case BCM6348_CPU_ID:
+	{
+		unsigned int tmp, n1, n2, m1;
+
 		/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 		tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 		n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -114,17 +122,47 @@ static unsigned int detect_cpu_clock(void)
 		n1 += 1;
 		n2 += 2;
 		m1 += 1;
+		return (16 * 1000000 * n1 * n2) / m1;
 	}
 
-	if (BCMCPU_IS_6358()) {
+	case BCM6358_CPU_ID:
+	{
+		unsigned int tmp, n1, n2, m1;
+
 		/* 16MHz * N1 * N2 / M1_CPU */
 		tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 		n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 		n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 		m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
+		return (16 * 1000000 * n1 * n2) / m1;
 	}
 
-	return (16 * 1000000 * n1 * n2) / m1;
+	case BCM6368_CPU_ID:
+	{
+		unsigned int tmp, p1, p2, ndiv, m1;
+
+		/* (64MHz / P1) * P2 * NDIV / M1_CPU */
+		tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
+
+		p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
+			DMIPSPLLCFG_6368_P1_SHIFT;
+
+		p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
+			DMIPSPLLCFG_6368_P2_SHIFT;
+
+		ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
+			DMIPSPLLCFG_6368_NDIV_SHIFT;
+
+		tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
+		m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
+			DMIPSPLLDIV_6368_MDIV_SHIFT;
+
+		return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
+	}
+
+	default:
+		BUG();
+	}
 }
 
 /*
@@ -146,7 +184,7 @@ static unsigned int detect_memory_size(void)
 		banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 	}
 
-	if (BCMCPU_IS_6358()) {
+	if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
 		val = bcm_memc_readl(MEMC_CFG_REG);
 		rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 		cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -191,9 +229,15 @@ void __init bcm63xx_cpu_init(void)
 		bcm63xx_irqs = bcm96345_irqs;
 		break;
 	case CPU_BMIPS4350:
-		expected_cpu_id = BCM6358_CPU_ID;
-		bcm63xx_regs_base = bcm96358_regs_base;
-		bcm63xx_irqs = bcm96358_irqs;
+		if ((read_c0_prid() & 0xf0) == 0x0030) {
+			expected_cpu_id = BCM6368_CPU_ID;
+			bcm63xx_regs_base = bcm96368_regs_base;
+			bcm63xx_irqs = bcm96368_irqs;
+		} else {
+			expected_cpu_id = BCM6358_CPU_ID;
+			bcm63xx_regs_base = bcm96358_regs_base;
+			bcm63xx_irqs = bcm96358_irqs;
+		}
 		break;
 	}
 
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index c2963da..d6e42c6 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
 	if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
 		return -ENODEV;
 
-	if (id == 1 && !BCMCPU_IS_6358())
+	if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
 		return -ENODEV;
 
 	if (id == 0) {
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index f2d5e30..f111ccd 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -59,6 +59,14 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 #define ext_irq_start		(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
 #define ext_irq_end		(BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
 #endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+#define irq_stat_reg		PERF_IRQSTAT_6368_REG
+#define irq_mask_reg		PERF_IRQMASK_6368_REG
+#define irq_bits		64
+#define is_ext_irq_cascaded	1
+#define ext_irq_start		(BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end		(BCM_6368_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#endif
 
 #if irq_bits == 32
 #define dispatch_internal			__dispatch_internal
@@ -116,6 +124,14 @@ static void bcm63xx_init_irq(void)
 		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
 		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
 		break;
+	case BCM6368_CPU_ID:
+		irq_stat_addr += PERF_IRQSTAT_6368_REG;
+		irq_mask_addr += PERF_IRQMASK_6368_REG;
+		irq_bits = 64;
+		is_ext_irq_cascaded = 1;
+		ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+		ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
+		break;
 	default:
 		BUG();
 	}
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index be252ef..99d7f40 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -32,9 +32,12 @@ void __init prom_init(void)
 		mask = CKCTL_6345_ALL_SAFE_EN;
 	else if (BCMCPU_IS_6348())
 		mask = CKCTL_6348_ALL_SAFE_EN;
-	else
-		/* BCMCPU_IS_6358() */
+	else if (BCMCPU_IS_6358())
 		mask = CKCTL_6358_ALL_SAFE_EN;
+	else if (BCMCPU_IS_6368())
+		mask = CKCTL_6368_ALL_SAFE_EN;
+	else
+		mask = 0;
 
 	reg = bcm_perf_readl(PERF_CKCTL_REG);
 	reg &= ~mask;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index ce6b3ca..cf145ea 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
 #define BCM6345_CPU_ID		0x6345
 #define BCM6348_CPU_ID		0x6348
 #define BCM6358_CPU_ID		0x6358
+#define BCM6368_CPU_ID		0x6368
 
 void __init bcm63xx_cpu_init(void);
 u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6358()	(0)
 #endif
 
+#ifdef CONFIG_BCM63XX_CPU_6368
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()	BCM6368_CPU_ID
+# endif
+# define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
+#else
+# define BCMCPU_IS_6368()	(0)
+#endif
+
 #ifndef bcm63xx_get_cpu_id
 #error "No CPU support configured"
 #endif
@@ -309,6 +323,47 @@ enum bcm63xx_regs_set {
 #define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
 
 
+/*
+ * 6368 register sets base address
+ */
+#define BCM_6368_DSL_LMEM_BASE		(0xdeadbeef)
+#define BCM_6368_PERF_BASE		(0xb0000000)
+#define BCM_6368_TIMER_BASE		(0xb0000040)
+#define BCM_6368_WDT_BASE		(0xb000005c)
+#define BCM_6368_UART0_BASE		(0xb0000100)
+#define BCM_6368_UART1_BASE		(0xb0000120)
+#define BCM_6368_GPIO_BASE		(0xb0000080)
+#define BCM_6368_SPI_BASE		(0xdeadbeef)
+#define BCM_6368_SPI2_BASE		(0xb0000800)
+#define BCM_6368_UDC0_BASE		(0xdeadbeef)
+#define BCM_6368_OHCI0_BASE		(0xb0001600)
+#define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
+#define BCM_6368_USBH_PRIV_BASE		(0xb0001700)
+#define BCM_6368_MPI_BASE		(0xb0001000)
+#define BCM_6368_PCMCIA_BASE		(0xb0001054)
+#define BCM_6368_SDRAM_REGS_BASE	(0xdeadbeef)
+#define BCM_6368_M2M_BASE		(0xdeadbeef)
+#define BCM_6368_DSL_BASE		(0xdeadbeef)
+#define BCM_6368_ENET0_BASE		(0xdeadbeef)
+#define BCM_6368_ENET1_BASE		(0xdeadbeef)
+#define BCM_6368_ENETDMA_BASE		(0xb0006800)
+#define BCM_6368_ENETDMAC_BASE		(0xb0006a00)
+#define BCM_6368_ENETDMAS_BASE		(0xb0006c00)
+#define BCM_6368_ENETSW_BASE		(0xb0f00000)
+#define BCM_6368_EHCI0_BASE		(0xb0001500)
+#define BCM_6368_SDRAM_BASE		(0xdeadbeef)
+#define BCM_6368_MEMC_BASE		(0xb0001200)
+#define BCM_6368_DDR_BASE		(0xb0001280)
+#define BCM_6368_ATM_BASE		(0xdeadbeef)
+#define BCM_6368_XTM_BASE		(0xb0001800)
+#define BCM_6368_XTMDMA_BASE		(0xb0005000)
+#define BCM_6368_XTMDMAC_BASE		(0xb0005200)
+#define BCM_6368_XTMDMAS_BASE		(0xb0005400)
+#define BCM_6368_PCM_BASE		(0xb0004000)
+#define BCM_6368_PCMDMA_BASE		(0xb0005800)
+#define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
+#define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
+
 
 extern const unsigned long *bcm63xx_regs_base;
 
@@ -412,6 +467,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef CONFIG_BCM63XX_CPU_6358
 	__GEN_RSET(6358)
 #endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+	__GEN_RSET(6368)
+#endif
 #endif
 	/* unreached */
 	return 0;
@@ -576,6 +634,47 @@ enum bcm63xx_irq {
 #define BCM_6358_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
 #define BCM_6358_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)
 
+/*
+ * 6368 irqs
+ */
+#define BCM_6368_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6368_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
+#define BCM_6368_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
+#define BCM_6368_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
+#define BCM_6368_ENET0_IRQ		0
+#define BCM_6368_ENET1_IRQ		0
+#define BCM_6368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 15)
+#define BCM_6368_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
+#define BCM_6368_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 7)
+#define BCM_6368_PCMCIA_IRQ		0
+#define BCM_6368_ENET0_RXDMA_IRQ	0
+#define BCM_6368_ENET0_TXDMA_IRQ	0
+#define BCM_6368_ENET1_RXDMA_IRQ	0
+#define BCM_6368_ENET1_TXDMA_IRQ	0
+#define BCM_6368_PCI_IRQ		(IRQ_INTERNAL_BASE + 13)
+#define BCM_6368_ATM_IRQ		0
+#define BCM_6368_ENETSW_RXDMA0_IRQ	(BCM_6368_HIGH_IRQ_BASE + 0)
+#define BCM_6368_ENETSW_RXDMA1_IRQ	(BCM_6368_HIGH_IRQ_BASE + 1)
+#define BCM_6368_ENETSW_RXDMA2_IRQ	(BCM_6368_HIGH_IRQ_BASE + 2)
+#define BCM_6368_ENETSW_RXDMA3_IRQ	(BCM_6368_HIGH_IRQ_BASE + 3)
+#define BCM_6368_ENETSW_TXDMA0_IRQ	(BCM_6368_HIGH_IRQ_BASE + 4)
+#define BCM_6368_ENETSW_TXDMA1_IRQ	(BCM_6368_HIGH_IRQ_BASE + 5)
+#define BCM_6368_ENETSW_TXDMA2_IRQ	(BCM_6368_HIGH_IRQ_BASE + 6)
+#define BCM_6368_ENETSW_TXDMA3_IRQ	(BCM_6368_HIGH_IRQ_BASE + 7)
+#define BCM_6368_XTM_IRQ		(IRQ_INTERNAL_BASE + 11)
+#define BCM_6368_XTM_DMA0_IRQ		(BCM_6368_HIGH_IRQ_BASE + 8)
+
+#define BCM_6368_PCM_DMA0_IRQ		(BCM_6368_HIGH_IRQ_BASE + 30)
+#define BCM_6368_PCM_DMA1_IRQ		(BCM_6368_HIGH_IRQ_BASE + 31)
+#define BCM_6368_EXT_IRQ0		(IRQ_INTERNAL_BASE + 20)
+#define BCM_6368_EXT_IRQ1		(IRQ_INTERNAL_BASE + 21)
+#define BCM_6368_EXT_IRQ2		(IRQ_INTERNAL_BASE + 22)
+#define BCM_6368_EXT_IRQ3		(IRQ_INTERNAL_BASE + 23)
+#define BCM_6368_EXT_IRQ4		(IRQ_INTERNAL_BASE + 24)
+#define BCM_6368_EXT_IRQ5		(IRQ_INTERNAL_BASE + 25)
+
 extern const int *bcm63xx_irqs;
 
 #define __GEN_CPU_IRQ_TABLE(__cpu)					\
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0..3d5de96 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
 		return 8;
 	case BCM6345_CPU_ID:
 		return 16;
+	case BCM6368_CPU_ID:
+		return 38;
 	case BCM6348_CPU_ID:
 	default:
 		return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 0fa613c..f237b41 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,6 +83,37 @@
 					CKCTL_6358_USBSU_EN |		\
 					CKCTL_6358_EPHY_EN)
 
+#define CKCTL_6368_VDSL_QPROC_EN	(1 << 2)
+#define CKCTL_6368_VDSL_AFE_EN		(1 << 3)
+#define CKCTL_6368_VDSL_BONDING_EN	(1 << 4)
+#define CKCTL_6368_VDSL_EN		(1 << 5)
+#define CKCTL_6368_PHYMIPS_EN		(1 << 6)
+#define CKCTL_6368_SWPKT_USB_EN		(1 << 7)
+#define CKCTL_6368_SWPKT_SAR_EN		(1 << 8)
+#define CKCTL_6368_SPI_CLK_EN		(1 << 9)
+#define CKCTL_6368_USBD_CLK_EN		(1 << 10)
+#define CKCTL_6368_SAR_CLK_EN		(1 << 11)
+#define CKCTL_6368_ROBOSW_CLK_EN	(1 << 12)
+#define CKCTL_6368_UTOPIA_CLK_EN	(1 << 13)
+#define CKCTL_6368_PCM_CLK_EN		(1 << 14)
+#define CKCTL_6368_USBH_CLK_EN		(1 << 15)
+#define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
+#define CKCTL_6368_NAND_CLK_EN		(1 << 17)
+#define CKCTL_6368_IPSEC_CLK_EN		(1 << 17)
+
+#define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
+					CKCTL_6368_SWPKT_SAR_EN |	\
+					CKCTL_6368_SPI_CLK_EN |		\
+					CKCTL_6368_USBD_CLK_EN |	\
+					CKCTL_6368_SAR_CLK_EN |		\
+					CKCTL_6368_ROBOSW_CLK_EN |	\
+					CKCTL_6368_UTOPIA_CLK_EN |	\
+					CKCTL_6368_PCM_CLK_EN |		\
+					CKCTL_6368_USBH_CLK_EN |	\
+					CKCTL_6368_DISABLE_GLESS_EN |	\
+					CKCTL_6368_NAND_CLK_EN |	\
+					CKCTL_6368_IPSEC_CLK_EN)
+
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG		0x8
 #define SYS_PLL_SOFT_RESET		0x1
@@ -94,6 +125,7 @@
 #define PERF_IRQMASK_6345_REG		0xc
 #define PERF_IRQMASK_6348_REG		0xc
 #define PERF_IRQMASK_6358_REG		0xc
+#define PERF_IRQMASK_6368_REG		0x20
 
 /* Interrupt Status register */
 #define PERF_IRQSTAT_REG		0x10
@@ -101,6 +133,7 @@
 #define PERF_IRQSTAT_6345_REG		0x10
 #define PERF_IRQSTAT_6348_REG		0x10
 #define PERF_IRQSTAT_6358_REG		0x10
+#define PERF_IRQSTAT_6368_REG		0x28
 
 /* External Interrupt Configuration register */
 #define PERF_EXTIRQ_CFG_REG		0x14
@@ -126,6 +159,7 @@
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG		0x28
+#define PERF_SOFTRESET_6368_REG		0x10
 
 #define SOFTRESET_6338_SPI_MASK		(1 << 0)
 #define SOFTRESET_6338_ENET_MASK	(1 << 2)
@@ -166,6 +200,15 @@
 				  SOFTRESET_6348_ACLC_MASK |		\
 				  SOFTRESET_6348_ADSLMIPSPLL_MASK)
 
+#define SOFTRESET_6368_SPI_MASK		(1 << 0)
+#define SOFTRESET_6368_MPI_MASK		(1 << 3)
+#define SOFTRESET_6368_EPHY_MASK	(1 << 6)
+#define SOFTRESET_6368_SAR_MASK		(1 << 7)
+#define SOFTRESET_6368_ENETSW_MASK	(1 << 10)
+#define SOFTRESET_6368_USBS_MASK	(1 << 11)
+#define SOFTRESET_6368_USBH_MASK	(1 << 12)
+#define SOFTRESET_6368_PCM_MASK		(1 << 13)
+
 /* MIPS PLL control register */
 #define PERF_MIPSPLLCTL_REG		0x34
 #define MIPSPLLCTL_N1_SHIFT		20
@@ -421,6 +464,44 @@
 #define GPIO_MODE_6358_SERIAL_LED	(1 << 10)
 #define GPIO_MODE_6358_UTOPIA		(1 << 12)
 
+#define GPIO_MODE_6368_ANALOG_AFE_0	(1 << 0)
+#define GPIO_MODE_6368_ANALOG_AFE_1	(1 << 1)
+#define GPIO_MODE_6368_SYS_IRQ		(1 << 2)
+#define GPIO_MODE_6368_SERIAL_LED_DATA	(1 << 3)
+#define GPIO_MODE_6368_SERIAL_LED_CLK	(1 << 4)
+#define GPIO_MODE_6368_INET_LED		(1 << 5)
+#define GPIO_MODE_6368_EPHY0_LED	(1 << 6)
+#define GPIO_MODE_6368_EPHY1_LED	(1 << 7)
+#define GPIO_MODE_6368_EPHY2_LED	(1 << 8)
+#define GPIO_MODE_6368_EPHY3_LED	(1 << 9)
+#define GPIO_MODE_6368_ROBOSW_LED_DAT	(1 << 10)
+#define GPIO_MODE_6368_ROBOSW_LED_CLK	(1 << 11)
+#define GPIO_MODE_6368_ROBOSW_LED0	(1 << 12)
+#define GPIO_MODE_6368_ROBOSW_LED1	(1 << 13)
+#define GPIO_MODE_6368_USBD_LED		(1 << 14)
+#define GPIO_MODE_6368_NTR_PULSE	(1 << 15)
+#define GPIO_MODE_6368_PCI_REQ1		(1 << 16)
+#define GPIO_MODE_6368_PCI_GNT1		(1 << 17)
+#define GPIO_MODE_6368_PCI_INTB		(1 << 18)
+#define GPIO_MODE_6368_PCI_REQ0		(1 << 19)
+#define GPIO_MODE_6368_PCI_GNT0		(1 << 20)
+#define GPIO_MODE_6368_PCMCIA_CD1	(1 << 22)
+#define GPIO_MODE_6368_PCMCIA_CD2	(1 << 23)
+#define GPIO_MODE_6368_PCMCIA_VS1	(1 << 24)
+#define GPIO_MODE_6368_PCMCIA_VS2	(1 << 25)
+#define GPIO_MODE_6368_EBI_CS2		(1 << 26)
+#define GPIO_MODE_6368_EBI_CS3		(1 << 27)
+#define GPIO_MODE_6368_SPI_SSN2		(1 << 28)
+#define GPIO_MODE_6368_SPI_SSN3		(1 << 29)
+#define GPIO_MODE_6368_SPI_SSN4		(1 << 30)
+#define GPIO_MODE_6368_SPI_SSN5		(1 << 31)
+
+
+#define GPIO_BASEMODE_6368_REG		0x38
+#define GPIO_BASEMODE_6368_UART2	0x1
+#define GPIO_BASEMODE_6368_GPIO		0x0
+#define GPIO_BASEMODE_6368_MASK		0x7
+/* those bits must be kept as read in gpio basemode register*/
 
 /*************************************************************************
  * _REG relative to RSET_ENET
@@ -631,7 +712,9 @@
  * _REG relative to RSET_USBH_PRIV
  *************************************************************************/
 
-#define USBH_PRIV_SWAP_REG		0x0
+#define USBH_PRIV_SWAP_6358_REG		0x0
+#define USBH_PRIV_SWAP_6368_REG		0x1c
+
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT	4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT	3
@@ -641,7 +724,13 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT	0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
-#define USBH_PRIV_TEST_REG		0x24
+#define USBH_PRIV_TEST_6358_REG		0x24
+#define USBH_PRIV_TEST_6368_REG		0x14
+
+#define USBH_PRIV_SETUP_6368_REG	0x28
+#define USBH_PRIV_SETUP_IOC_SHIFT	4
+#define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
+
 
 
 /*************************************************************************
@@ -837,6 +926,19 @@
 #define DMIPSPLLCFG_N2_SHIFT		29
 #define DMIPSPLLCFG_N2_MASK		(0x7 << DMIPSPLLCFG_N2_SHIFT)
 
+#define DDR_DMIPSPLLCFG_6368_REG	0x20
+#define DMIPSPLLCFG_6368_P1_SHIFT	0
+#define DMIPSPLLCFG_6368_P1_MASK	(0xf << DMIPSPLLCFG_6368_P1_SHIFT)
+#define DMIPSPLLCFG_6368_P2_SHIFT	4
+#define DMIPSPLLCFG_6368_P2_MASK	(0xf << DMIPSPLLCFG_6368_P2_SHIFT)
+#define DMIPSPLLCFG_6368_NDIV_SHIFT	16
+#define DMIPSPLLCFG_6368_NDIV_MASK	(0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
+
+#define DDR_DMIPSPLLDIV_6368_REG	0x24
+#define DMIPSPLLDIV_6368_MDIV_SHIFT	0
+#define DMIPSPLLDIV_6368_MDIV_MASK	(0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
+
+
 /*************************************************************************
  * _REG relative to RSET_M2M
  *************************************************************************/
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index e3fe04d..ef94ba7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,10 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
 		if (offset >= 0xfff00000)
 			return 1;
 		break;
+	case BCM6368_CPU_ID:
+		if (offset >= 0xb0000000 && offset < 0xb1000000)
+			return 1;
+		break;
 	}
 	return 0;
 }
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index c7fc92f..24e7bcf 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
 	unsigned int mem_size;
 	u32 val;
 
-	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
+	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
 		return -ENODEV;
 
 	if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
 	/* setup PCI to local bus access, used by PCI device to target
 	 * local RAM while bus mastering */
 	bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
-	if (BCMCPU_IS_6358())
+	if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
 		val = MPI_SP0_REMAP_ENABLE_MASK;
 	else
 		val = 0;
-- 
1.7.1.1

Re: [PATCH 05/11] MIPS: BCM63XX: cleanup cpu registers.

[Jonas Gorski]

Hi Maxime,

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> Use preprocessor when possible to avoid duplicated and error-prone
> code.
>
> Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
> ---
>  arch/mips/bcm63xx/cpu.c                          |  145 +----------
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h |  311 +++++++---------------
>  2 files changed, 109 insertions(+), 347 deletions(-)
>
> diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
> index 7c7e4d4..027ac30 100644
> --- a/arch/mips/bcm63xx/cpu.c
> +++ b/arch/mips/bcm63xx/cpu.c
> @@ -33,162 +33,37 @@ static unsigned int bcm63xx_memory_size;
>  * 6338 register sets and irqs
>  */
>  static const unsigned long bcm96338_regs_base[] = {

I would propose naming these bcm63??_regs_base; it would be more in
line with the rest of the code.

> -       [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
> -       [RSET_PERF]             = BCM_6338_PERF_BASE,
> -       [RSET_TIMER]            = BCM_6338_TIMER_BASE,
> -       [RSET_WDT]              = BCM_6338_WDT_BASE,
> -       [RSET_UART0]            = BCM_6338_UART0_BASE,
> -       [RSET_UART1]            = BCM_6338_UART1_BASE,
> -       [RSET_GPIO]             = BCM_6338_GPIO_BASE,
> -       [RSET_SPI]              = BCM_6338_SPI_BASE,
> -       [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
> -       [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
> -       [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
> -       [RSET_UDC0]             = BCM_6338_UDC0_BASE,
> -       [RSET_MPI]              = BCM_6338_MPI_BASE,
> -       [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
> -       [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
> -       [RSET_DSL]              = BCM_6338_DSL_BASE,
> -       [RSET_ENET0]            = BCM_6338_ENET0_BASE,
> -       [RSET_ENET1]            = BCM_6338_ENET1_BASE,
> -       [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
> -       [RSET_MEMC]             = BCM_6338_MEMC_BASE,
> -       [RSET_DDR]              = BCM_6338_DDR_BASE,
> +       __GEN_CPU_REGS_TABLE(6338)
>  };
>
>  static const int bcm96338_irqs[] = {
> -       [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
> -       [IRQ_UART0]             = BCM_6338_UART0_IRQ,
> -       [IRQ_DSL]               = BCM_6338_DSL_IRQ,
> -       [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
> -       [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
> -       [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
> -       [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
> +       __GEN_CPU_IRQ_TABLE(6338)
>  };
>
> -/*
> - * 6345 register sets and irqs
> - */

You should leave the comment here (or also delete the 6338 one on top).

>  static const unsigned long bcm96345_regs_base[] = {
> -       [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
> -       [RSET_PERF]             = BCM_6345_PERF_BASE,
> -       [RSET_TIMER]            = BCM_6345_TIMER_BASE,
> -       [RSET_WDT]              = BCM_6345_WDT_BASE,
> -       [RSET_UART0]            = BCM_6345_UART0_BASE,
> -       [RSET_UART1]            = BCM_6345_UART1_BASE,
> -       [RSET_GPIO]             = BCM_6345_GPIO_BASE,
> -       [RSET_SPI]              = BCM_6345_SPI_BASE,
> -       [RSET_UDC0]             = BCM_6345_UDC0_BASE,
> -       [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
> -       [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
> -       [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
> -       [RSET_MPI]              = BCM_6345_MPI_BASE,
> -       [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
> -       [RSET_DSL]              = BCM_6345_DSL_BASE,
> -       [RSET_ENET0]            = BCM_6345_ENET0_BASE,
> -       [RSET_ENET1]            = BCM_6345_ENET1_BASE,
> -       [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
> -       [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
> -       [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
> -       [RSET_MEMC]             = BCM_6345_MEMC_BASE,
> -       [RSET_DDR]              = BCM_6345_DDR_BASE,
> +       __GEN_CPU_REGS_TABLE(6345)
>  };
>
>  static const int bcm96345_irqs[] = {
> -       [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
> -       [IRQ_UART0]             = BCM_6345_UART0_IRQ,
> -       [IRQ_DSL]               = BCM_6345_DSL_IRQ,
> -       [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
> -       [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
> -       [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
> -       [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
> +       __GEN_CPU_IRQ_TABLE(6345)
>  };
>
> -/*
> - * 6348 register sets and irqs
> - */

Same comment comment.

>  static const unsigned long bcm96348_regs_base[] = {
> -       [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
> -       [RSET_PERF]             = BCM_6348_PERF_BASE,
> -       [RSET_TIMER]            = BCM_6348_TIMER_BASE,
> -       [RSET_WDT]              = BCM_6348_WDT_BASE,
> -       [RSET_UART0]            = BCM_6348_UART0_BASE,
> -       [RSET_UART1]            = BCM_6348_UART1_BASE,
> -       [RSET_GPIO]             = BCM_6348_GPIO_BASE,
> -       [RSET_SPI]              = BCM_6348_SPI_BASE,
> -       [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
> -       [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
> -       [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
> -       [RSET_MPI]              = BCM_6348_MPI_BASE,
> -       [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
> -       [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
> -       [RSET_DSL]              = BCM_6348_DSL_BASE,
> -       [RSET_ENET0]            = BCM_6348_ENET0_BASE,
> -       [RSET_ENET1]            = BCM_6348_ENET1_BASE,
> -       [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
> -       [RSET_MEMC]             = BCM_6348_MEMC_BASE,
> -       [RSET_DDR]              = BCM_6348_DDR_BASE,
> +       __GEN_CPU_REGS_TABLE(6348)
>  };
>
>  static const int bcm96348_irqs[] = {
> -       [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
> -       [IRQ_UART0]             = BCM_6348_UART0_IRQ,
> -       [IRQ_DSL]               = BCM_6348_DSL_IRQ,
> -       [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
> -       [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
> -       [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
> -       [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
> -       [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
> -       [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
> -       [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
> -       [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
> -       [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
> -       [IRQ_PCI]               = BCM_6348_PCI_IRQ,
> +       __GEN_CPU_IRQ_TABLE(6348)
> +
>  };
>
> -/*
> - * 6358 register sets and irqs
> - */

Same comment comment.


Jonas

Re: [PATCH 06/11] MIPS: BCM63XX: add more register sets & missing register definitions.

[Jonas Gorski]

Hi,

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> Needed for upcoming 6368 CPU support.
>
> Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
> ---
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |  183 +++++++++++++++++++++
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   78 +++++++++
>  2 files changed, 261 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> index 464f948..ce6b3ca 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> @@ -88,6 +88,7 @@ enum bcm63xx_regs_set {
>        RSET_UART1,
>        RSET_GPIO,
>        RSET_SPI,
> +       RSET_SPI2,

What's the difference between SPI and SPI2?

As far as I can tell the biggest difference between the bcm6338/48 SPI
controller and the bcm6358/68 one is the order of the registers (and
some bit positions), but the general way it works is the same. Unless
you have two drivers (which will then probably have a lot of common
code), you'll need to check the chipid anyway to know which RSET to
use, so you could also just direcly use this to use the correct
register offsets.

The High-Speed SPI controller on the bcm6328, bcm63268 and bcm6362 is
a totally different beast though, that one should get it's own
register set (but that's in the future ;-).

>        RSET_UDC0,
>        RSET_OHCI0,
>        RSET_OHCI_PRIV,
> @@ -98,10 +99,23 @@ enum bcm63xx_regs_set {
>        RSET_ENET0,
>        RSET_ENET1,
>        RSET_ENETDMA,
> +       RSET_ENETDMAC,
> +       RSET_ENETDMAS,
> +       RSET_ENETSW,
>        RSET_EHCI0,
>        RSET_SDRAM,
>        RSET_MEMC,
>        RSET_DDR,
> +       RSET_M2M,
> +       RSET_ATM,
> +       RSET_XTM,
> +       RSET_XTMDMA,
> +       RSET_XTMDMAC,
> +       RSET_XTMDMAS,
> +       RSET_PCM,
> +       RSET_PCMDMA,
> +       RSET_PCMDMAC,
> +       RSET_PCMDMAS,
>  };
>
>  #define RSET_DSL_LMEM_SIZE             (64 * 1024 * 4)
> @@ -109,11 +123,18 @@ enum bcm63xx_regs_set {
>  #define RSET_WDT_SIZE                  12
>  #define RSET_ENET_SIZE                 2048
>  #define RSET_ENETDMA_SIZE              2048
> +#define RSET_ENETSW_SIZE               65536
>  #define RSET_UART_SIZE                 24
>  #define RSET_UDC_SIZE                  256
>  #define RSET_OHCI_SIZE                 256
>  #define RSET_EHCI_SIZE                 256
>  #define RSET_PCMCIA_SIZE               12
> +#define RSET_M2M_SIZE                  256
> +#define RSET_ATM_SIZE                  4096
> +#define RSET_XTM_SIZE                  10240
> +#define RSET_XTMDMA_SIZE               256
> +#define RSET_XTMDMAC_SIZE(chans)       (16 * (chans))
> +#define RSET_XTMDMAS_SIZE(chans)       (16 * (chans))
>
>  /*
>  * 6338 register sets base address
> @@ -127,6 +148,7 @@ enum bcm63xx_regs_set {
>  #define BCM_6338_UART1_BASE            (0xdeadbeef)
>  #define BCM_6338_GPIO_BASE             (0xfffe0400)
>  #define BCM_6338_SPI_BASE              (0xfffe0c00)
> +#define BCM_6338_SPI2_BASE             (0xdeadbeef)
>  #define BCM_6338_UDC0_BASE             (0xdeadbeef)
>  #define BCM_6338_USBDMA_BASE           (0xfffe2400)
>  #define BCM_6338_OHCI0_BASE            (0xdeadbeef)
> @@ -141,10 +163,23 @@ enum bcm63xx_regs_set {
>  #define BCM_6338_ENET0_BASE            (0xfffe2800)
>  #define BCM_6338_ENET1_BASE            (0xdeadbeef)
>  #define BCM_6338_ENETDMA_BASE          (0xfffe2400)
> +#define BCM_6338_ENETDMAC_BASE         (0xfffe2500)
> +#define BCM_6338_ENETDMAS_BASE         (0xfffe2600)
> +#define BCM_6338_ENETSW_BASE           (0xdeadbeef)
>  #define BCM_6338_EHCI0_BASE            (0xdeadbeef)
>  #define BCM_6338_SDRAM_BASE            (0xfffe3100)
>  #define BCM_6338_MEMC_BASE             (0xdeadbeef)
>  #define BCM_6338_DDR_BASE              (0xdeadbeef)
> +#define BCM_6338_M2M_BASE              (0xdeadbeef)
> +#define BCM_6338_ATM_BASE              (0xdeadbeef)

That one is already there, it's called BCM_6338_SAR_BASE. You should
just rename that one.

> +#define BCM_6338_XTM_BASE              (0xdeadbeef)
> +#define BCM_6338_XTMDMA_BASE           (0xdeadbeef)
> +#define BCM_6338_XTMDMAC_BASE          (0xdeadbeef)
> +#define BCM_6338_XTMDMAS_BASE          (0xdeadbeef)
> +#define BCM_6338_PCM_BASE              (0xdeadbeef)
> +#define BCM_6338_PCMDMA_BASE           (0xdeadbeef)
> +#define BCM_6338_PCMDMAC_BASE          (0xdeadbeef)
> +#define BCM_6338_PCMDMAS_BASE          (0xdeadbeef)
>
>  /*
>  * 6345 register sets base address
> @@ -158,10 +193,14 @@ enum bcm63xx_regs_set {
>  #define BCM_6345_UART1_BASE            (0xdeadbeef)
>  #define BCM_6345_GPIO_BASE             (0xfffe0400)
>  #define BCM_6345_SPI_BASE              (0xdeadbeef)
> +#define BCM_6345_SPI2_BASE             (0xdeadbeef)
>  #define BCM_6345_UDC0_BASE             (0xdeadbeef)
>  #define BCM_6345_USBDMA_BASE           (0xfffe2800)
>  #define BCM_6345_ENET0_BASE            (0xfffe1800)
>  #define BCM_6345_ENETDMA_BASE          (0xfffe2800)
> +#define BCM_6345_ENETDMAC_BASE         (0xfffe2900)
> +#define BCM_6345_ENETDMAS_BASE         (0xfffe2a00)
> +#define BCM_6345_ENETSW_BASE           (0xdeadbeef)
>  #define BCM_6345_PCMCIA_BASE           (0xfffe2028)
>  #define BCM_6345_MPI_BASE              (0xdeadbeef)
>  #define BCM_6345_OHCI0_BASE            (0xfffe2100)
> @@ -176,6 +215,16 @@ enum bcm63xx_regs_set {
>  #define BCM_6345_SDRAM_BASE            (0xfffe2300)
>  #define BCM_6345_MEMC_BASE             (0xdeadbeef)
>  #define BCM_6345_DDR_BASE              (0xdeadbeef)
> +#define BCM_6345_M2M_BASE              (0xdeadbeef)
> +#define BCM_6345_ATM_BASE              (0xdeadbeef)

Actually that would be 0xfffe4000 (same as the bcm6348). There's also
a SAR_BASE which should be removed.


Jonas

Re: [PATCH 07/11] MIPS: BCM63XX: change irq code to prepare for per-cpu peculiarity.

[Jonas Gorski]

Hi,

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> index 3ea2681..4354be1 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> @@ -89,9 +89,18 @@
>
>  /* Interrupt Mask register */
>  #define PERF_IRQMASK_REG               0xc
> +#define PERF_IRQSTAT_REG               0x10

You are re-adding the duplicate PERF_IRQSTAT_REG I just removed.

> +#define PERF_IRQMASK_6338_REG          0xc
> +#define PERF_IRQMASK_6345_REG          0xc
> +#define PERF_IRQMASK_6348_REG          0xc
> +#define PERF_IRQMASK_6358_REG          0xc

If you are adding one for each SoC, why keep the "generic"
PERF_IRQMASK_REG at all? AFAICS it isn't used it any more.

>
>  /* Interrupt Status register */
>  #define PERF_IRQSTAT_REG               0x10
> +#define PERF_IRQSTAT_6338_REG          0x10
> +#define PERF_IRQSTAT_6345_REG          0x10
> +#define PERF_IRQSTAT_6348_REG          0x10
> +#define PERF_IRQSTAT_6358_REG          0x10

The same applies to the "generic" PERF_IRQSTAT_REG, you can also remove it.


Jonas

Re: [PATCH 11/11] MIPS: BCM63XX: add support for bcm6368 CPU.

[Jonas Gorski]

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
> ---
>  arch/mips/bcm63xx/Kconfig                         |    4 +
>  arch/mips/bcm63xx/clk.c                           |   70 +++++++++++++-
>  arch/mips/bcm63xx/cpu.c                           |   76 ++++++++++++---
>  arch/mips/bcm63xx/dev-uart.c                      |    2 +-
>  arch/mips/bcm63xx/irq.c                           |   16 +++
>  arch/mips/bcm63xx/prom.c                          |    7 +-
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   99 +++++++++++++++++++
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h |    2 +
>  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |  106 ++++++++++++++++++++-
>  arch/mips/include/asm/mach-bcm63xx/ioremap.h      |    4 +
>  arch/mips/pci/pci-bcm63xx.c                       |    4 +-
>  11 files changed, 364 insertions(+), 26 deletions(-)
>
> diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
> index fb177d6..6b1b9ad 100644
> --- a/arch/mips/bcm63xx/Kconfig
> +++ b/arch/mips/bcm63xx/Kconfig
> @@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
>  config BCM63XX_CPU_6358
>        bool "support 6358 CPU"
>        select HW_HAS_PCI
> +
> +config BCM63XX_CPU_6368
> +       bool "support 6368 CPU"
> +       select HW_HAS_PCI
>  endmenu
>
>  source "arch/mips/bcm63xx/boards/Kconfig"
> diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
> index 2c68ee9..9d57c71 100644
> --- a/arch/mips/bcm63xx/clk.c
> +++ b/arch/mips/bcm63xx/clk.c
> @@ -10,6 +10,7 @@
>  #include <linux/mutex.h>
>  #include <linux/err.h>
>  #include <linux/clk.h>
> +#include <linux/delay.h>
>  #include <bcm63xx_cpu.h>
>  #include <bcm63xx_io.h>
>  #include <bcm63xx_regs.h>
> @@ -113,6 +114,34 @@ static struct clk clk_ephy = {
>  };
>
>  /*
> + * Ethernet switch clock
> + */
> +static void enetsw_set(struct clk *clk, int enable)
> +{
> +       if (!BCMCPU_IS_6368())
> +               return;
> +       bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
> +                       CKCTL_6368_SWPKT_USB_EN |
> +                       CKCTL_6368_SWPKT_SAR_EN, enable);
> +       if (enable) {
> +               u32 val;
> +
> +               /* reset switch core afer clock change */
> +               val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
> +               val &= ~SOFTRESET_6368_ENETSW_MASK;
> +               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> +               msleep(10);
> +               val |= SOFTRESET_6368_ENETSW_MASK;
> +               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> +               msleep(10);
> +       }
> +}
> +
> +static struct clk clk_enetsw = {
> +       .set    = enetsw_set,
> +};
> +
> +/*
>  * PCM clock
>  */
>  static void pcm_set(struct clk *clk, int enable)
> @@ -131,9 +160,10 @@ static struct clk clk_pcm = {
>  */
>  static void usbh_set(struct clk *clk, int enable)
>  {
> -       if (!BCMCPU_IS_6348())
> -               return;
> -       bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
> +       if (BCMCPU_IS_6348())
> +               bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
> +       else if (BCMCPU_IS_6368())
> +               bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
>  }
>
>  static struct clk clk_usbh = {
> @@ -162,6 +192,36 @@ static struct clk clk_spi = {
>  };
>
>  /*
> + * XTM clock
> + */
> +static void xtm_set(struct clk *clk, int enable)
> +{
> +       if (!BCMCPU_IS_6368())
> +               return;
> +
> +       bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
> +                       CKCTL_6368_SWPKT_SAR_EN, enable);
> +
> +       if (enable) {
> +               u32 val;
> +
> +               /* reset sar core afer clock change */
> +               val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
> +               val &= ~SOFTRESET_6368_SAR_MASK;
> +               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> +               mdelay(1);
> +               val |= SOFTRESET_6368_SAR_MASK;
> +               bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
> +               mdelay(1);
> +       }
> +}
> +
> +
> +static struct clk clk_xtm = {
> +       .set    = xtm_set,
> +};
> +
> +/*
>  * Internal peripheral clock
>  */
>  static struct clk clk_periph = {
> @@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
>                return &clk_enet0;
>        if (!strcmp(id, "enet1"))
>                return &clk_enet1;
> +       if (!strcmp(id, "enetsw"))
> +               return &clk_enetsw;
>        if (!strcmp(id, "ephy"))
>                return &clk_ephy;
>        if (!strcmp(id, "usbh"))
>                return &clk_usbh;
>        if (!strcmp(id, "spi"))
>                return &clk_spi;
> +       if (!strcmp(id, "xtm"))
> +               return &clk_xtm;
>        if (!strcmp(id, "periph"))
>                return &clk_periph;
>        if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
> diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
> index 027ac30..3ea2533 100644
> --- a/arch/mips/bcm63xx/cpu.c
> +++ b/arch/mips/bcm63xx/cpu.c
> @@ -66,6 +66,15 @@ static const int bcm96358_irqs[] = {
>
>  };
>
> +static const unsigned long bcm96368_regs_base[] = {
> +       __GEN_CPU_REGS_TABLE(6368)
> +};
> +
> +static const int bcm96368_irqs[] = {
> +       __GEN_CPU_IRQ_TABLE(6368)
> +
> +};
> +
>  u16 __bcm63xx_get_cpu_id(void)
>  {
>        return bcm63xx_cpu_id;
> @@ -92,20 +101,19 @@ unsigned int bcm63xx_get_memory_size(void)
>
>  static unsigned int detect_cpu_clock(void)
>  {
> -       unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
> -
> -       /* BCM6338 has a fixed 240 Mhz frequency */
> -       if (BCMCPU_IS_6338())
> +       switch (bcm63xx_get_cpu_id()) {
> +       case BCM6338_CPU_ID:
> +               /* BCM6338 has a fixed 240 Mhz frequency */
>                return 240000000;
>
> -       /* BCM6345 has a fixed 140Mhz frequency */
> -       if (BCMCPU_IS_6345())
> +       case BCM6345_CPU_ID:
> +               /* BCM6345 has a fixed 140Mhz frequency */
>                return 140000000;
>
> -       /*
> -        * frequency depends on PLL configuration:
> -        */
> -       if (BCMCPU_IS_6348()) {
> +       case BCM6348_CPU_ID:
> +       {
> +               unsigned int tmp, n1, n2, m1;
> +
>                /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
>                tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
>                n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
> @@ -114,17 +122,47 @@ static unsigned int detect_cpu_clock(void)
>                n1 += 1;
>                n2 += 2;
>                m1 += 1;
> +               return (16 * 1000000 * n1 * n2) / m1;
>        }
>
> -       if (BCMCPU_IS_6358()) {
> +       case BCM6358_CPU_ID:
> +       {
> +               unsigned int tmp, n1, n2, m1;
> +
>                /* 16MHz * N1 * N2 / M1_CPU */
>                tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
>                n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
>                n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
>                m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
> +               return (16 * 1000000 * n1 * n2) / m1;
>        }
>
> -       return (16 * 1000000 * n1 * n2) / m1;
> +       case BCM6368_CPU_ID:
> +       {
> +               unsigned int tmp, p1, p2, ndiv, m1;
> +
> +               /* (64MHz / P1) * P2 * NDIV / M1_CPU */
> +               tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
> +
> +               p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
> +                       DMIPSPLLCFG_6368_P1_SHIFT;
> +
> +               p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
> +                       DMIPSPLLCFG_6368_P2_SHIFT;
> +
> +               ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
> +                       DMIPSPLLCFG_6368_NDIV_SHIFT;
> +
> +               tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
> +               m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
> +                       DMIPSPLLDIV_6368_MDIV_SHIFT;
> +
> +               return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
> +       }
> +
> +       default:
> +               BUG();
> +       }
>  }
>
>  /*
> @@ -146,7 +184,7 @@ static unsigned int detect_memory_size(void)
>                banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
>        }
>
> -       if (BCMCPU_IS_6358()) {
> +       if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
>                val = bcm_memc_readl(MEMC_CFG_REG);
>                rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
>                cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
> @@ -191,9 +229,15 @@ void __init bcm63xx_cpu_init(void)
>                bcm63xx_irqs = bcm96345_irqs;
>                break;
>        case CPU_BMIPS4350:
> -               expected_cpu_id = BCM6358_CPU_ID;
> -               bcm63xx_regs_base = bcm96358_regs_base;
> -               bcm63xx_irqs = bcm96358_irqs;
> +               if ((read_c0_prid() & 0xf0) == 0x0030) {
> +                       expected_cpu_id = BCM6368_CPU_ID;
> +                       bcm63xx_regs_base = bcm96368_regs_base;
> +                       bcm63xx_irqs = bcm96368_irqs;
> +               } else {
> +                       expected_cpu_id = BCM6358_CPU_ID;
> +                       bcm63xx_regs_base = bcm96358_regs_base;
> +                       bcm63xx_irqs = bcm96358_irqs;
> +               }

You might want to change that to an explicitly check for the BCM6358 -
at least mine evaluates to 0x0010, while for my BCM6328 it does to
0x0070.

>                break;
>        }
>
> diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
> index c2963da..d6e42c6 100644
> --- a/arch/mips/bcm63xx/dev-uart.c
> +++ b/arch/mips/bcm63xx/dev-uart.c
> @@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
>        if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
>                return -ENODEV;
>
> -       if (id == 1 && !BCMCPU_IS_6358())
> +       if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))

No need for brackets around the CPU checks (but I didn't find anything
in the code style documentation about this).

>                return -ENODEV;
>
>        if (id == 0) {
> diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
> index f2d5e30..f111ccd 100644
> --- a/arch/mips/bcm63xx/irq.c
> +++ b/arch/mips/bcm63xx/irq.c
> @@ -59,6 +59,14 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
>  #define ext_irq_start          (BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
>  #define ext_irq_end            (BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
>  #endif
> +#ifdef CONFIG_BCM63XX_CPU_6368
> +#define irq_stat_reg           PERF_IRQSTAT_6368_REG
> +#define irq_mask_reg           PERF_IRQMASK_6368_REG
> +#define irq_bits               64
> +#define is_ext_irq_cascaded    1
> +#define ext_irq_start          (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
> +#define ext_irq_end            (BCM_6368_EXT_IRQ3 - IRQ_INTERNAL_BASE)

This is different from ...

> +#endif
>
>  #if irq_bits == 32
>  #define dispatch_internal                      __dispatch_internal
> @@ -116,6 +124,14 @@ static void bcm63xx_init_irq(void)
>                ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
>                ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
>                break;
> +       case BCM6368_CPU_ID:
> +               irq_stat_addr += PERF_IRQSTAT_6368_REG;
> +               irq_mask_addr += PERF_IRQMASK_6368_REG;
> +               irq_bits = 64;
> +               is_ext_irq_cascaded = 1;
> +               ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
> +               ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;

... this one - you should fix the non runtime detection case.

> +               break;
>        default:
>                BUG();
>        }

You are missing in bcm63xx_external_irq_mask,
bcm63xx_external_irq_unmask and bcm63xx_external_irq_clear special
handling for 6368's external IRQs. According to the Broadcom sources,
PERF_EXTIRQ_CFG_REG is at 0x18 for the 6368; for IRQ4 and IRQ5 it's at
0x1c.

> diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
> index be252ef..99d7f40 100644
> --- a/arch/mips/bcm63xx/prom.c
> +++ b/arch/mips/bcm63xx/prom.c
> @@ -32,9 +32,12 @@ void __init prom_init(void)
>                mask = CKCTL_6345_ALL_SAFE_EN;
>        else if (BCMCPU_IS_6348())
>                mask = CKCTL_6348_ALL_SAFE_EN;
> -       else
> -               /* BCMCPU_IS_6358() */
> +       else if (BCMCPU_IS_6358())
>                mask = CKCTL_6358_ALL_SAFE_EN;
> +       else if (BCMCPU_IS_6368())
> +               mask = CKCTL_6368_ALL_SAFE_EN;
> +       else
> +               mask = 0;
>
>        reg = bcm_perf_readl(PERF_CKCTL_REG);
>        reg &= ~mask;
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> index ce6b3ca..cf145ea 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
> @@ -13,6 +13,7 @@
>  #define BCM6345_CPU_ID         0x6345
>  #define BCM6348_CPU_ID         0x6348
>  #define BCM6358_CPU_ID         0x6358
> +#define BCM6368_CPU_ID         0x6368
>
>  void __init bcm63xx_cpu_init(void);
>  u16 __bcm63xx_get_cpu_id(void);
> @@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
>  # define BCMCPU_IS_6358()      (0)
>  #endif
>
> +#ifdef CONFIG_BCM63XX_CPU_6368
> +# ifdef bcm63xx_get_cpu_id
> +#  undef bcm63xx_get_cpu_id
> +#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
> +#  define BCMCPU_RUNTIME_DETECT
> +# else
> +#  define bcm63xx_get_cpu_id() BCM6368_CPU_ID
> +# endif
> +# define BCMCPU_IS_6368()      (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
> +#else
> +# define BCMCPU_IS_6368()      (0)
> +#endif
> +
>  #ifndef bcm63xx_get_cpu_id
>  #error "No CPU support configured"
>  #endif
> @@ -309,6 +323,47 @@ enum bcm63xx_regs_set {
>  #define BCM_6358_PCMDMAS_BASE          (0xfffe1a00)
>
>
> +/*
> + * 6368 register sets base address
> + */
> +#define BCM_6368_DSL_LMEM_BASE         (0xdeadbeef)

0xb0f80000 ;-)

> +#define BCM_6368_PERF_BASE             (0xb0000000)
> +#define BCM_6368_TIMER_BASE            (0xb0000040)
> +#define BCM_6368_WDT_BASE              (0xb000005c)
> +#define BCM_6368_UART0_BASE            (0xb0000100)
> +#define BCM_6368_UART1_BASE            (0xb0000120)
> +#define BCM_6368_GPIO_BASE             (0xb0000080)
> +#define BCM_6368_SPI_BASE              (0xdeadbeef)
> +#define BCM_6368_SPI2_BASE             (0xb0000800)
> +#define BCM_6368_UDC0_BASE             (0xdeadbeef)
> +#define BCM_6368_OHCI0_BASE            (0xb0001600)
> +#define BCM_6368_OHCI_PRIV_BASE                (0xdeadbeef)
> +#define BCM_6368_USBH_PRIV_BASE                (0xb0001700)
> +#define BCM_6368_MPI_BASE              (0xb0001000)
> +#define BCM_6368_PCMCIA_BASE           (0xb0001054)
> +#define BCM_6368_SDRAM_REGS_BASE       (0xdeadbeef)
> +#define BCM_6368_M2M_BASE              (0xdeadbeef)
> +#define BCM_6368_DSL_BASE              (0xdeadbeef)

0xb0f56000


Jonas

Re: [PATCH 10/11] MIPS: BCM63XX: add external irq support for non 6348 CPUs.

[Jonas Gorski]

Hi,

On 10 June 2011 23:47, Maxime Bizon <mbizon@freebox.fr> wrote:
> diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> index 4354be1..0fa613c 100644
> --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
> @@ -104,12 +104,22 @@
>
>  /* External Interrupt Configuration register */
>  #define PERF_EXTIRQ_CFG_REG            0x14
> +
> +/* for 6348 only */
> +#define EXTIRQ_CFG_SENSE_6348(x)       (1 << (x))
> +#define EXTIRQ_CFG_STAT_6348(x)                (1 << (x + 5))
> +#define EXTIRQ_CFG_CLEAR_6348(x)       (1 << (x + 10))
> +#define EXTIRQ_CFG_MASK_6348(x)                (1 << (x + 15))
> +#define EXTIRQ_CFG_BOTHEDGE_6348(x)    (1 << (x + 20))
> +#define EXTIRQ_CFG_LEVELSENSE_6348(x)  (1 << (x + 25))
> +
> +/* for all others */
>  #define EXTIRQ_CFG_SENSE(x)            (1 << (x))
> -#define EXTIRQ_CFG_STAT(x)             (1 << (x + 5))
> -#define EXTIRQ_CFG_CLEAR(x)            (1 << (x + 10))
> -#define EXTIRQ_CFG_MASK(x)             (1 << (x + 15))
> -#define EXTIRQ_CFG_BOTHEDGE(x)         (1 << (x + 20))
> -#define EXTIRQ_CFG_LEVELSENSE(x)       (1 << (x + 25))
> +#define EXTIRQ_CFG_STAT(x)             (1 << (x + 4))
> +#define EXTIRQ_CFG_CLEAR(x)            (1 << (x + 8))
> +#define EXTIRQ_CFG_MASK(x)             (1 << (x + 12))
> +#define EXTIRQ_CFG_BOTHEDGE(x)         (1 << (x + 16))
> +#define EXTIRQ_CFG_LEVELSENSE(x)       (1 << (x + 20))
>
>  #define EXTIRQ_CFG_CLEAR_ALL           (0xf << 10)
>  #define EXTIRQ_CFG_MASK_ALL            (0xf << 15)

These two are still based on the 6348 definition, you should also add
these for non 6348 SoCs.
<http://lxr.linux.no/#linux+v2.6.39/arch/mips/bcm63xx/setup.c#L64>,
where these get used, needs also to be changed to then use the
appropriate one.


Jonas