flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[naveen yadav]

Dear All,

We are working on 2.6.35.9 linux kernel on MIPS 34kce core and our
cache is VIVT having cache aliasing .
When I check the implementation on ARM I can check the implemenation
exists , but there is not similar implementation exists on MIPS.
These API's are used by XFS module:

static inline void flush_kernel_vmap_range(void *vaddr, int size)
static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
static inline void flush_kernel_dcache_page(struct page *page)


I can check implementation on ARM at
http://git.kernel.org/?p=linux/kernel/git/longterm/linux-2.6.34.y.git;a=commit;h=252a9afff76097667429b583e8b5b170b47665a4
 and
----------------------------------------------------------------------------------------------------------------------------
--- a/arch/arm/include/asm/cacheflush.h+++ b/arch/arm/include/asm/cacheflush.h
@@ -432,6 +432,16
 @@ static inline void __flush_icache_all(void)
  : "r" (0)); #endif }
+static inline void flush_kernel_vmap_range(void *addr, int size)
+{
+       if ((cache_is_vivt() || cache_is_vipt_aliasing()))
+         __cpuc_flush_dcache_area(addr, (size_t)size);
+}
+static inline void invalidate_kernel_vmap_range(void *addr, int size)
+{
+       if ((cache_is_vivt() || cache_is_vipt_aliasing()))
+         __cpuc_flush_dcache_area(addr, (size_t)size);
+}
-------------------------------------------------------------------------------------------------------------------------------------


http://git.kernel.org/?p=linux/kernel/git/longterm/linux-2.6.34.y.git;a=blobdiff;f=arch/arm/include/asm/cacheflush.h;h=1a711ea8418b6045c581a576caa3f85496ee2673;hp=bb7d695f3900f70d635a3597cd19d7cb68c0d732;hb=73be1591579084a8103a7005dd3172f3e9dd7362;hpb=44b7532b8b464f606053562400719c9c21276037

======================================================
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+       /* highmem pages are always flushed upon kunmap already */
+       if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
+               __cpuc_flush_dcache_page(page_address(page));
+}
+
==========================================================


Is there any similar API exists for MIPS.  I want to use for XFS these API's

thanks

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Ralf Baechle]

On Fri, Mar 25, 2011 at 02:38:13PM +0530, naveen yadav wrote:

> We are working on 2.6.35.9 linux kernel on MIPS 34kce core and our
> cache is VIVT having cache aliasing .

No, they're VIPT unless you successfully modified your 34K core to
change it from a less than perfect cache design to the most lunatic
cache policy known to man kind ...

> When I check the implementation on ARM I can check the implemenation
> exists , but there is not similar implementation exists on MIPS.
> These API's are used by XFS module:
> 
> static inline void flush_kernel_vmap_range(void *vaddr, int size)
> static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
> static inline void flush_kernel_dcache_page(struct page *page)

A known problem for (too ...) long.  I'll finally take care of it.

  Ralf

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[naveen yadav]

I am sorry, Yes they are VIPT,


On Fri, Mar 25, 2011 at 10:57 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Fri, Mar 25, 2011 at 02:38:13PM +0530, naveen yadav wrote:
>
>> We are working on 2.6.35.9 linux kernel on MIPS 34kce core and our
>> cache is VIVT having cache aliasing .
>
> No, they're VIPT unless you successfully modified your 34K core to
> change it from a less than perfect cache design to the most lunatic
> cache policy known to man kind ...
>
>> When I check the implementation on ARM I can check the implemenation
>> exists , but there is not similar implementation exists on MIPS.
>> These API's are used by XFS module:
>>
>> static inline void flush_kernel_vmap_range(void *vaddr, int size)
>> static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
>> static inline void flush_kernel_dcache_page(struct page *page)
>
> A known problem for (too ...) long.  I'll finally take care of it.
>
>  Ralf
>

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[naveen yadav]

Hi Ralf,

Have you got time to look into this issue.

Regards


On Tue, Mar 29, 2011 at 11:24 AM, naveen yadav <yad.naveen@gmail.com> wrote:
> I am sorry, Yes they are VIPT,
>
>
> On Fri, Mar 25, 2011 at 10:57 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
>> On Fri, Mar 25, 2011 at 02:38:13PM +0530, naveen yadav wrote:
>>
>>> We are working on 2.6.35.9 linux kernel on MIPS 34kce core and our
>>> cache is VIVT having cache aliasing .
>>
>> No, they're VIPT unless you successfully modified your 34K core to
>> change it from a less than perfect cache design to the most lunatic
>> cache policy known to man kind ...
>>
>>> When I check the implementation on ARM I can check the implemenation
>>> exists , but there is not similar implementation exists on MIPS.
>>> These API's are used by XFS module:
>>>
>>> static inline void flush_kernel_vmap_range(void *vaddr, int size)
>>> static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
>>> static inline void flush_kernel_dcache_page(struct page *page)
>>
>> A known problem for (too ...) long.  I'll finally take care of it.
>>
>>  Ralf
>>
>

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[naveen yadav]

[-- Attachment #1: Type: text/plain, Size: 1067 bytes --]

Dear Ralf Baechle,

I have made one patch for below API's for 2.6.35.9 kernel. Pls provide
me your feedback about this .

Regards

On Fri, Mar 25, 2011 at 10:57 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Fri, Mar 25, 2011 at 02:38:13PM +0530, naveen yadav wrote:
>
>> We are working on 2.6.35.9 linux kernel on MIPS 34kce core and our
>> cache is VIVT having cache aliasing .
>
> No, they're VIPT unless you successfully modified your 34K core to
> change it from a less than perfect cache design to the most lunatic
> cache policy known to man kind ...
>
>> When I check the implementation on ARM I can check the implemenation
>> exists , but there is not similar implementation exists on MIPS.
>> These API's are used by XFS module:
>>
>> static inline void flush_kernel_vmap_range(void *vaddr, int size)
>> static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
>> static inline void flush_kernel_dcache_page(struct page *page)
>
> A known problem for (too ...) long.  I'll finally take care of it.
>
>  Ralf
>

[-- Attachment #2: mips_dma_api.patch --]
[-- Type: application/octet-stream, Size: 1310 bytes --]

diff -Nrup clean/linux-2.6.35.9/arch/mips/include/asm/cacheflush.h linux-2.6.35.9/arch/mips/include/asm/cacheflush.h
--- clean/linux-2.6.35.9/arch/mips/include/asm/cacheflush.h	2010-11-23 04:01:26.000000000 +0900
+++ linux-2.6.35.9/arch/mips/include/asm/cacheflush.h	2011-06-14 11:08:16.000000000 +0900
@@ -114,4 +114,31 @@ unsigned long run_uncached(void *func);
 extern void *kmap_coherent(struct page *page, unsigned long addr);
 extern void kunmap_coherent(void);
 
+/* New function added which are missed in  MIPS */
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_vmap_range(void *addr, int size)
+{
+/*	if ((cache_is_vivt() || cache_is_vipt_aliasing()))*/
+	if ((c->icache.flags & MIPS_CACHE_VTAG) ||	\
+			(c->dcache.flags & MIPS_CACHE_ALIASES)) {
+			unsigned long start = (unsigned long)addr;
+			dma_cache_wback_inv(start, (size_t)size);
+	}
+}
+static inline void invalidate_kernel_vmap_range(void *addr, int size)
+{
+/*	if ((cache_is_vivt() || cache_is_vipt_aliasing()))*/
+	if ((c->icache.flags & MIPS_CACHE_VTAG) ||	\
+		(c->dcache.flags & MIPS_CACHE_ALIASES)) {
+			unsigned long start = (unsigned long)addr;
+			dma_cache_inv(start, (size_t)size);
+}
+}
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+
+}
+
+
+
 #endif /* _ASM_CACHEFLUSH_H */

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Christoph Hellwig]

On Wed, Jun 15, 2011 at 11:58:24AM +0530, naveen yadav wrote:
> Dear Ralf Baechle,
> 
> I have made one patch for below API's for 2.6.35.9 kernel. Pls provide
> me your feedback about this .

Ralf,

I'll second that request.  We'll really need this, right now embedded XFS
users are hacking around it in horrible ways.

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Ralf Baechle]

On Wed, Jun 15, 2011 at 11:58:24AM +0530, naveen yadav wrote:

> diff -Nrup clean/linux-2.6.35.9/arch/mips/include/asm/cacheflush.h linux-2.6.35.9/arch/mips/include/asm/cacheflush.h
> --- clean/linux-2.6.35.9/arch/mips/include/asm/cacheflush.h	2010-11-23 04:01:26.000000000 +0900
> +++ linux-2.6.35.9/arch/mips/include/asm/cacheflush.h	2011-06-14 11:08:16.000000000 +0900
> @@ -114,4 +114,31 @@ unsigned long run_uncached(void *func);
>  extern void *kmap_coherent(struct page *page, unsigned long addr);
>  extern void kunmap_coherent(void);
>  
> +/* New function added which are missed in  MIPS */
> +#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
> +static inline void flush_kernel_vmap_range(void *addr, int size)
> +{
> +/*	if ((cache_is_vivt() || cache_is_vipt_aliasing()))*/
> +	if ((c->icache.flags & MIPS_CACHE_VTAG) ||	\
> +			(c->dcache.flags & MIPS_CACHE_ALIASES)) {

Don't access the flags fields directly but use the feature test macros
like cpu_has_vtag_icache or cpu_has_dc_aliases.  These macros allow the
compiler to optimize unused parts of the cache code.

cache_is_vivt is an ARM CPU feature test macro.  I guess you ported it but
don't quite understand what it meant.  The good news is there are no such
VIVT data caches on MIPS.  And the Icache we just don't care about.

You're accessing c->icache.flags - but I see nothing like "struct
cpuinfo_mips *c;" anywhere.  This doesn't even compile.

> +			unsigned long start = (unsigned long)addr;
> +			dma_cache_wback_inv(start, (size_t)size);

This is a function used for DMA I/O.  On a system that has DMA coherence
in hardware it will do nothing at all!

> +	}
> +}
> +static inline void invalidate_kernel_vmap_range(void *addr, int size)
> +{
> +/*	if ((cache_is_vivt() || cache_is_vipt_aliasing()))*/
> +	if ((c->icache.flags & MIPS_CACHE_VTAG) ||	\
> +		(c->dcache.flags & MIPS_CACHE_ALIASES)) {
> +			unsigned long start = (unsigned long)addr;
> +			dma_cache_inv(start, (size_t)size);
> +}
> +}

Same problems.

> +static inline void flush_kernel_dcache_page(struct page *page)
> +{
> +
> +}

This function should also be implemented if your target has highmem.

  Ralf

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Ralf Baechle]

On Thu, Jun 16, 2011 at 08:02:50PM +0200, Christoph Hellwig wrote:

> Ralf,
> 
> I'll second that request.  We'll really need this, right now embedded XFS
> users are hacking around it in horrible ways.

Here's my shot at the problem.  I don't have the time to setup a XFS
filesystem and tools for testing before the weekend so all I claim is this
patch builds for R4000-class CPUs but it should be pretty close to the
real thing.

Naveen, can you give this patch a spin?  Thanks!

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 arch/mips/include/asm/cacheflush.h |   24 ++++++++++++++++++++++++
 arch/mips/mm/c-octeon.c            |    6 ++++++
 arch/mips/mm/c-r3k.c               |    7 +++++++
 arch/mips/mm/c-r4k.c               |   35 +++++++++++++++++++++++++++++++++++
 arch/mips/mm/c-tx39.c              |    7 +++++++
 arch/mips/mm/cache.c               |    5 +++++
 6 files changed, 84 insertions(+), 0 deletions(-)

diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 40bb9fd..69468de 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -114,4 +114,28 @@ unsigned long run_uncached(void *func);
 extern void *kmap_coherent(struct page *page, unsigned long addr);
 extern void kunmap_coherent(void);
 
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+	BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
+}
+
+/*
+ * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
+ * cache writeback and invalidate operation.
+ */
+extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
+
+static inline void flush_kernel_vmap_range(void *vaddr, int size)
+{
+	if (cpu_has_dc_aliases)
+		__flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
+{
+	if (cpu_has_dc_aliases)
+		__flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
 #endif /* _ASM_CACHEFLUSH_H */
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 16c4d25..daa81f7 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -169,6 +169,10 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
 		octeon_flush_icache_all_cores(vma);
 }
 
+static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+	BUG();
+}
 
 /**
  * Probe Octeon's caches
@@ -273,6 +277,8 @@ void __cpuinit octeon_cache_init(void)
 	flush_icache_range		= octeon_flush_icache_range;
 	local_flush_icache_range	= local_octeon_flush_icache_range;
 
+	__flush_kernel_vmap_range	= octeon_flush_kernel_vmap_range;
+
 	build_clear_page();
 	build_copy_page();
 }
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index e6b0efd..0765583 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -299,6 +299,11 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
 	write_c0_status(flags);
 }
 
+static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+	BUG();
+}
+
 static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
 {
 	/* Catch bad driver code */
@@ -323,6 +328,8 @@ void __cpuinit r3k_cache_init(void)
 	flush_icache_range = r3k_flush_icache_range;
 	local_flush_icache_range = r3k_flush_icache_range;
 
+	__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
+
 	flush_cache_sigtramp = r3k_flush_cache_sigtramp;
 	local_flush_data_cache_page = local_r3k_flush_data_cache_page;
 	flush_data_cache_page = r3k_flush_data_cache_page;
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index eeb642e..38a593e 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -718,6 +718,39 @@ static void r4k_flush_icache_all(void)
 		r4k_blast_icache();
 }
 
+struct flush_kernel_vmap_range_args {
+	unsigned long	vaddr;
+	int		size;
+};
+
+static inline void local_r4k_flush_kernel_vmap_range(void *args)
+{
+	struct flush_kernel_vmap_range_args *vmra = args;
+	unsigned long vaddr = vmra->vaddr;
+	int size = vmra->size;
+
+	/*
+	 * Aliases only affect the primary caches so don't bother with
+	 * S-caches or T-caches.
+	 */
+	if (cpu_has_safe_index_cacheops && size >= dcache_size)
+		r4k_blast_dcache();
+	else {
+		R4600_HIT_CACHEOP_WAR_IMPL;
+		blast_dcache_range(vaddr, vaddr + size);
+	}
+}
+
+static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+	struct flush_kernel_vmap_range_args args;
+
+	args.vaddr = (unsigned long) vaddr;
+	args.size = size;
+
+	r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
+}
+
 static inline void rm7k_erratum31(void)
 {
 	const unsigned long ic_lsize = 32;
@@ -1399,6 +1432,8 @@ void __cpuinit r4k_cache_init(void)
 	flush_cache_page	= r4k_flush_cache_page;
 	flush_cache_range	= r4k_flush_cache_range;
 
+	__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
+
 	flush_cache_sigtramp	= r4k_flush_cache_sigtramp;
 	flush_icache_all	= r4k_flush_icache_all;
 	local_flush_data_cache_page	= local_r4k_flush_data_cache_page;
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index d352fad..a43c197c 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -253,6 +253,11 @@ static void tx39_flush_icache_range(unsigned long start, unsigned long end)
 	}
 }
 
+static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+	BUG();
+}
+
 static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 {
 	unsigned long end;
@@ -394,6 +399,8 @@ void __cpuinit tx39_cache_init(void)
 		flush_icache_range = tx39_flush_icache_range;
 		local_flush_icache_range = tx39_flush_icache_range;
 
+		__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
+
 		flush_cache_sigtramp = tx39_flush_cache_sigtramp;
 		local_flush_data_cache_page = local_tx39_flush_data_cache_page;
 		flush_data_cache_page = tx39_flush_data_cache_page;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 12af739..829320c 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -35,6 +35,11 @@ void (*local_flush_icache_range)(unsigned long start, unsigned long end);
 void (*__flush_cache_vmap)(void);
 void (*__flush_cache_vunmap)(void);
 
+void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
+void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
+
+EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
+
 /* MIPS specific cache operations */
 void (*flush_cache_sigtramp)(unsigned long addr);
 void (*local_flush_data_cache_page)(void * addr);

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[naveen yadav]

[-- Attachment #1: Type: text/plain, Size: 8460 bytes --]

Thanks Ralf for your patch,

My target is MIPS 34Kc, and I check your patch , Since my target
machine is on 2.6.35, so I need to do small modification, I am
attaching my patch for reference.

Modification done.
1.  r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args); ->
r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args,1);
2. My target is enabled with High mem, so I modify like below, if
there is any problem with below code pls let me know.

static inline void flush_kernel_dcache_page(struct page *page)
{
       /* BUG_ON(cpu_has_dc_aliases && PageHighMem(page)); */
       if(cpu_has_dc_aliases && !PageHighMem(page))
                 __flush_kernel_vmap_range((unsigned
long)page_address(page), PAGE_SIZE);
}


with above modification this works fine for me.

Regards
Naveen

On Fri, Jun 17, 2011 at 8:50 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Thu, Jun 16, 2011 at 08:02:50PM +0200, Christoph Hellwig wrote:
>
>> Ralf,
>>
>> I'll second that request.  We'll really need this, right now embedded XFS
>> users are hacking around it in horrible ways.
>
> Here's my shot at the problem.  I don't have the time to setup a XFS
> filesystem and tools for testing before the weekend so all I claim is this
> patch builds for R4000-class CPUs but it should be pretty close to the
> real thing.
>
> Naveen, can you give this patch a spin?  Thanks!
>
>  Ralf
>
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
>
>  arch/mips/include/asm/cacheflush.h |   24 ++++++++++++++++++++++++
>  arch/mips/mm/c-octeon.c            |    6 ++++++
>  arch/mips/mm/c-r3k.c               |    7 +++++++
>  arch/mips/mm/c-r4k.c               |   35 +++++++++++++++++++++++++++++++++++
>  arch/mips/mm/c-tx39.c              |    7 +++++++
>  arch/mips/mm/cache.c               |    5 +++++
>  6 files changed, 84 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
> index 40bb9fd..69468de 100644
> --- a/arch/mips/include/asm/cacheflush.h
> +++ b/arch/mips/include/asm/cacheflush.h
> @@ -114,4 +114,28 @@ unsigned long run_uncached(void *func);
>  extern void *kmap_coherent(struct page *page, unsigned long addr);
>  extern void kunmap_coherent(void);
>
> +#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
> +static inline void flush_kernel_dcache_page(struct page *page)
> +{
> +       BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
> +}
> +
> +/*
> + * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
> + * cache writeback and invalidate operation.
> + */
> +extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
> +
> +static inline void flush_kernel_vmap_range(void *vaddr, int size)
> +{
> +       if (cpu_has_dc_aliases)
> +               __flush_kernel_vmap_range((unsigned long) vaddr, size);
> +}
> +
> +static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
> +{
> +       if (cpu_has_dc_aliases)
> +               __flush_kernel_vmap_range((unsigned long) vaddr, size);
> +}
> +
>  #endif /* _ASM_CACHEFLUSH_H */
> diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
> index 16c4d25..daa81f7 100644
> --- a/arch/mips/mm/c-octeon.c
> +++ b/arch/mips/mm/c-octeon.c
> @@ -169,6 +169,10 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma,
>                octeon_flush_icache_all_cores(vma);
>  }
>
> +static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
> +{
> +       BUG();
> +}
>
>  /**
>  * Probe Octeon's caches
> @@ -273,6 +277,8 @@ void __cpuinit octeon_cache_init(void)
>        flush_icache_range              = octeon_flush_icache_range;
>        local_flush_icache_range        = local_octeon_flush_icache_range;
>
> +       __flush_kernel_vmap_range       = octeon_flush_kernel_vmap_range;
> +
>        build_clear_page();
>        build_copy_page();
>  }
> diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
> index e6b0efd..0765583 100644
> --- a/arch/mips/mm/c-r3k.c
> +++ b/arch/mips/mm/c-r3k.c
> @@ -299,6 +299,11 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
>        write_c0_status(flags);
>  }
>
> +static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
> +{
> +       BUG();
> +}
> +
>  static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
>  {
>        /* Catch bad driver code */
> @@ -323,6 +328,8 @@ void __cpuinit r3k_cache_init(void)
>        flush_icache_range = r3k_flush_icache_range;
>        local_flush_icache_range = r3k_flush_icache_range;
>
> +       __flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
> +
>        flush_cache_sigtramp = r3k_flush_cache_sigtramp;
>        local_flush_data_cache_page = local_r3k_flush_data_cache_page;
>        flush_data_cache_page = r3k_flush_data_cache_page;
> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index eeb642e..38a593e 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -718,6 +718,39 @@ static void r4k_flush_icache_all(void)
>                r4k_blast_icache();
>  }
>
> +struct flush_kernel_vmap_range_args {
> +       unsigned long   vaddr;
> +       int             size;
> +};
> +
> +static inline void local_r4k_flush_kernel_vmap_range(void *args)
> +{
> +       struct flush_kernel_vmap_range_args *vmra = args;
> +       unsigned long vaddr = vmra->vaddr;
> +       int size = vmra->size;
> +
> +       /*
> +        * Aliases only affect the primary caches so don't bother with
> +        * S-caches or T-caches.
> +        */
> +       if (cpu_has_safe_index_cacheops && size >= dcache_size)
> +               r4k_blast_dcache();
> +       else {
> +               R4600_HIT_CACHEOP_WAR_IMPL;
> +               blast_dcache_range(vaddr, vaddr + size);
> +       }
> +}
> +
> +static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
> +{
> +       struct flush_kernel_vmap_range_args args;
> +
> +       args.vaddr = (unsigned long) vaddr;
> +       args.size = size;
> +
> +       r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
> +}
> +
>  static inline void rm7k_erratum31(void)
>  {
>        const unsigned long ic_lsize = 32;
> @@ -1399,6 +1432,8 @@ void __cpuinit r4k_cache_init(void)
>        flush_cache_page        = r4k_flush_cache_page;
>        flush_cache_range       = r4k_flush_cache_range;
>
> +       __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
> +
>        flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
>        flush_icache_all        = r4k_flush_icache_all;
>        local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
> diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
> index d352fad..a43c197c 100644
> --- a/arch/mips/mm/c-tx39.c
> +++ b/arch/mips/mm/c-tx39.c
> @@ -253,6 +253,11 @@ static void tx39_flush_icache_range(unsigned long start, unsigned long end)
>        }
>  }
>
> +static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
> +{
> +       BUG();
> +}
> +
>  static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
>  {
>        unsigned long end;
> @@ -394,6 +399,8 @@ void __cpuinit tx39_cache_init(void)
>                flush_icache_range = tx39_flush_icache_range;
>                local_flush_icache_range = tx39_flush_icache_range;
>
> +               __flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
> +
>                flush_cache_sigtramp = tx39_flush_cache_sigtramp;
>                local_flush_data_cache_page = local_tx39_flush_data_cache_page;
>                flush_data_cache_page = tx39_flush_data_cache_page;
> diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
> index 12af739..829320c 100644
> --- a/arch/mips/mm/cache.c
> +++ b/arch/mips/mm/cache.c
> @@ -35,6 +35,11 @@ void (*local_flush_icache_range)(unsigned long start, unsigned long end);
>  void (*__flush_cache_vmap)(void);
>  void (*__flush_cache_vunmap)(void);
>
> +void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
> +void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
> +
> +EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
> +
>  /* MIPS specific cache operations */
>  void (*flush_cache_sigtramp)(unsigned long addr);
>  void (*local_flush_data_cache_page)(void * addr);
>

[-- Attachment #2: vmap_range.patch --]
[-- Type: application/octet-stream, Size: 6683 bytes --]

diff -Nurp linux-2.6.35.13_org/arch/mips/include/asm/cacheflush.h linux-2.6.35.13/arch/mips/include/asm/cacheflush.h
--- linux-2.6.35.13_org/arch/mips/include/asm/cacheflush.h	2010-11-23 04:01:26.000000000 +0900
+++ linux-2.6.35.13/arch/mips/include/asm/cacheflush.h	2011-06-17 13:51:48.000000000 +0900
@@ -113,5 +113,33 @@ unsigned long run_uncached(void *func);
 
 extern void *kmap_coherent(struct page *page, unsigned long addr);
 extern void kunmap_coherent(void);
+#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
+
+/*
+ * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
+ * cache writeback and invalidate operation.
+ */
+extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
+
+static inline void flush_kernel_dcache_page(struct page *page)
+{
+       //BUG_ON(cpu_has_dc_aliases && PageHighMem(page));
+       if(cpu_has_dc_aliases && !PageHighMem(page))
+	   	  __flush_kernel_vmap_range((unsigned long)page_address(page), PAGE_SIZE);
+}
+
+
+
+static inline void flush_kernel_vmap_range(void *vaddr, int size)
+{
+       if (cpu_has_dc_aliases)
+               __flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
+
+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
+{
+       if (cpu_has_dc_aliases)
+               __flush_kernel_vmap_range((unsigned long) vaddr, size);
+}
 
 #endif /* _ASM_CACHEFLUSH_H */
diff -Nurp linux-2.6.35.13_org/arch/mips/mm/cache.c linux-2.6.35.13/arch/mips/mm/cache.c
--- linux-2.6.35.13_org/arch/mips/mm/cache.c	2011-03-30 14:09:11.000000000 +0900
+++ linux-2.6.35.13/arch/mips/mm/cache.c	2011-06-17 13:07:37.000000000 +0900
@@ -32,6 +32,11 @@ void (*flush_cache_page)(struct vm_area_
 void (*flush_icache_range)(unsigned long start, unsigned long end);
 void (*local_flush_icache_range)(unsigned long start, unsigned long end);
 
+void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
+void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
+
+EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
+
 void (*__flush_cache_vmap)(void);
 void (*__flush_cache_vunmap)(void);
 
diff -Nurp linux-2.6.35.13_org/arch/mips/mm/c-octeon.c linux-2.6.35.13/arch/mips/mm/c-octeon.c
--- linux-2.6.35.13_org/arch/mips/mm/c-octeon.c	2010-11-23 04:01:26.000000000 +0900
+++ linux-2.6.35.13/arch/mips/mm/c-octeon.c	2011-06-17 13:01:36.000000000 +0900
@@ -169,6 +169,11 @@ static void octeon_flush_cache_page(stru
 		octeon_flush_icache_all_cores(vma);
 }
 
+static void octeon_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+       BUG();
+}
+
 
 /**
  * Probe Octeon's caches
@@ -258,6 +263,7 @@ void __cpuinit octeon_cache_init(void)
 	flush_data_cache_page		= octeon_flush_data_cache_page;
 	flush_icache_range		= octeon_flush_icache_range;
 	local_flush_icache_range	= local_octeon_flush_icache_range;
+	__flush_kernel_vmap_range       = octeon_flush_kernel_vmap_range;
 
 	build_clear_page();
 	build_copy_page();
diff -Nurp linux-2.6.35.13_org/arch/mips/mm/c-r3k.c linux-2.6.35.13/arch/mips/mm/c-r3k.c
--- linux-2.6.35.13_org/arch/mips/mm/c-r3k.c	2010-11-23 04:01:26.000000000 +0900
+++ linux-2.6.35.13/arch/mips/mm/c-r3k.c	2011-06-17 13:03:26.000000000 +0900
@@ -299,6 +299,12 @@ static void r3k_flush_cache_sigtramp(uns
 	write_c0_status(flags);
 }
 
+static void r3k_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+       BUG();
+}
+
+
 static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size)
 {
 	/* Catch bad driver code */
@@ -322,7 +328,7 @@ void __cpuinit r3k_cache_init(void)
 	flush_cache_page = r3k_flush_cache_page;
 	flush_icache_range = r3k_flush_icache_range;
 	local_flush_icache_range = r3k_flush_icache_range;
-
+	__flush_kernel_vmap_range = r3k_flush_kernel_vmap_range;
 	flush_cache_sigtramp = r3k_flush_cache_sigtramp;
 	local_flush_data_cache_page = local_r3k_flush_data_cache_page;
 	flush_data_cache_page = r3k_flush_data_cache_page;
diff -Nurp linux-2.6.35.13_org/arch/mips/mm/c-r4k.c linux-2.6.35.13/arch/mips/mm/c-r4k.c
--- linux-2.6.35.13_org/arch/mips/mm/c-r4k.c	2011-03-30 14:09:11.000000000 +0900
+++ linux-2.6.35.13/arch/mips/mm/c-r4k.c	2011-06-17 13:17:00.000000000 +0900
@@ -719,6 +719,39 @@ static void r4k_flush_icache_all(void)
 		r4k_blast_icache();
 }
 
+struct flush_kernel_vmap_range_args {
+       unsigned long   vaddr;
+       int             size;
+};
+
+static inline void local_r4k_flush_kernel_vmap_range(void *args)
+{
+       struct flush_kernel_vmap_range_args *vmra = args;
+       unsigned long vaddr = vmra->vaddr;
+       int size = vmra->size;
+
+       /*
+        * Aliases only affect the primary caches so don't bother with
+        * S-caches or T-caches.
+        */
+       if (cpu_has_safe_index_cacheops && size >= dcache_size)
+               r4k_blast_dcache();
+       else {
+               R4600_HIT_CACHEOP_WAR_IMPL;
+               blast_dcache_range(vaddr, vaddr + size);
+       }
+}
+
+static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+       struct flush_kernel_vmap_range_args args;
+
+       args.vaddr = (unsigned long) vaddr;
+       args.size = size;
+
+       r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args,1);
+}
+
 static inline void rm7k_erratum31(void)
 {
 	const unsigned long ic_lsize = 32;
@@ -1400,7 +1400,7 @@ void __cpuinit r4k_cache_init(void)
 	flush_cache_mm		= r4k_flush_cache_mm;
 	flush_cache_page	= r4k_flush_cache_page;
 	flush_cache_range	= r4k_flush_cache_range;
-
+	__flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
 	flush_cache_sigtramp	= r4k_flush_cache_sigtramp;
 	flush_icache_all	= r4k_flush_icache_all;
 	local_flush_data_cache_page	= local_r4k_flush_data_cache_page;
diff -Nurp linux-2.6.35.13_org/arch/mips/mm/c-tx39.c linux-2.6.35.13/arch/mips/mm/c-tx39.c
--- linux-2.6.35.13_org/arch/mips/mm/c-tx39.c	2010-11-23 04:01:26.000000000 +0900
+++ linux-2.6.35.13/arch/mips/mm/c-tx39.c	2011-06-17 13:06:53.000000000 +0900
@@ -253,6 +253,11 @@ static void tx39_flush_icache_range(unsi
 	}
 }
 
+static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
+{
+       BUG();
+}
+
 static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 {
 	unsigned long end;
@@ -364,7 +369,7 @@ void __cpuinit tx39_cache_init(void)
 		flush_cache_page	= (void *) tx39h_flush_icache_all;
 		flush_icache_range	= (void *) tx39h_flush_icache_all;
 		local_flush_icache_range = (void *) tx39h_flush_icache_all;
-
+		__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
 		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;
 		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;
 		flush_data_cache_page	= (void *) tx39h_flush_icache_all;

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Sergei Shtylyov]

Hello.

On 17-06-2011 19:20, Ralf Baechle wrote:

>> Ralf,

>> I'll second that request.  We'll really need this, right now embedded XFS
>> users are hacking around it in horrible ways.

> Here's my shot at the problem.  I don't have the time to setup a XFS
> filesystem and tools for testing before the weekend so all I claim is this
> patch builds for R4000-class CPUs but it should be pretty close to the
> real thing.

> Naveen, can you give this patch a spin?  Thanks!

>    Ralf

> Signed-off-by: Ralf Baechle<ralf@linux-mips.org>

[...]

> diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
> index 40bb9fd..69468de 100644
> --- a/arch/mips/include/asm/cacheflush.h
> +++ b/arch/mips/include/asm/cacheflush.h
> @@ -114,4 +114,28 @@ unsigned long run_uncached(void *func);
>   extern void *kmap_coherent(struct page *page, unsigned long addr);
>   extern void kunmap_coherent(void);
>
> +#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
> +static inline void flush_kernel_dcache_page(struct page *page)
> +{
> +	BUG_ON(cpu_has_dc_aliases&&  PageHighMem(page));
> +}
> +
> +/*
> + * For now flush_kernel_vmap_range and invalidate_kernel_vmap_range both do a
> + * cache writeback and invalidate operation.
> + */
> +extern void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
> +
> +static inline void flush_kernel_vmap_range(void *vaddr, int size)
> +{
> +	if (cpu_has_dc_aliases)
> +		__flush_kernel_vmap_range((unsigned long) vaddr, size);
> +}
> +
> +static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
> +{
> +	if (cpu_has_dc_aliases)
> +		__flush_kernel_vmap_range((unsigned long) vaddr, size);

    Not __invalidate_kernel_vmap_range()?

WBR, Sergei

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Ralf Baechle]

On Sat, Jun 18, 2011 at 05:06:37PM +0400, Sergei Shtylyov wrote:

> >+static inline void flush_kernel_vmap_range(void *vaddr, int size)
> >+{
> >+	if (cpu_has_dc_aliases)
> >+		__flush_kernel_vmap_range((unsigned long) vaddr, size);
> >+}
> >+
> >+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
> >+{
> >+	if (cpu_has_dc_aliases)
> >+		__flush_kernel_vmap_range((unsigned long) vaddr, size);
> 
>    Not __invalidate_kernel_vmap_range()?

No, for the moment both just do a writeback + invalidate.  I may change
that for something more efficient later once I understand the consequences
of this.

  Ralf

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[naveen yadav]

Dear Ralf and Sergei,

If we have L2 cache, then we need to invalidate them also ?

our system  have L2 cache(write back).

Regards


On Mon, Jun 20, 2011 at 3:26 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Sat, Jun 18, 2011 at 05:06:37PM +0400, Sergei Shtylyov wrote:
>
>> >+static inline void flush_kernel_vmap_range(void *vaddr, int size)
>> >+{
>> >+    if (cpu_has_dc_aliases)
>> >+            __flush_kernel_vmap_range((unsigned long) vaddr, size);
>> >+}
>> >+
>> >+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
>> >+{
>> >+    if (cpu_has_dc_aliases)
>> >+            __flush_kernel_vmap_range((unsigned long) vaddr, size);
>>
>>    Not __invalidate_kernel_vmap_range()?
>
> No, for the moment both just do a writeback + invalidate.  I may change
> that for something more efficient later once I understand the consequences
> of this.
>
>  Ralf
>

Re: flush_kernel_vmap_range() invalidate_kernel_vmap_range() API not exists for MIPS

[Ralf Baechle]

On Fri, Jun 24, 2011 at 10:36:13AM +0530, naveen yadav wrote:

> Dear Ralf and Sergei,
> 
> If we have L2 cache, then we need to invalidate them also ?

No.  S-cache and T-cache (rare, only the RM7000 has one) are physically
indexed.

  Ralf