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From: Seungwhan Youn <claude.youn@gmail.com>
To: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Cc: linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, jassisinghbrar@gmail.com,
	sbkim73@samsung.com, sw.youn@samsung.com, kgene.kim@samsung.com
Subject: Re: [PATCH v2 3/3] ARM: EXYNOS4: Add EPLL clock operations
Date: Thu, 30 Jun 2011 16:28:47 +0900	[thread overview]
Message-ID: <BANLkTinzY57NCviNmerwpa_GZL8jmXr_rQ@mail.gmail.com> (raw)
In-Reply-To: <BANLkTi=aGo3WPaftzBxR=Jy6oHAzt+Yhbw@mail.gmail.com>

> So far i was not lucky in finding out a generic way of deriving the
> epll_div values.
> And it doesn't seem to
> 1. Save lines of code or
> 2. Consolidate the PLL code.
>
> Any suggestions for a simpler implementation are welcome.

No, I mean that 'epll_div' values are _not_always_correct_ on Samsung
SoC platform. It depends on board setting. That 'epll_div' values only
works fine when FINpll is 24MHz, as you know these're from reference
values on User Manual, and board maker can change FINpll freq. with
OM[0] pin setting, XXTI and XusbXTI.
So. if you want to make consolidate the PLL code, you should make a
general formula to calculate that epll_div values on the fly OR move
'epll_div' values table into somewhere machine specific file, not into
platform file 'arch/arm/plat-s5p/clock.c'.

        claude

WARNING: multiple messages have this Message-ID (diff)
From: claude.youn@gmail.com (Seungwhan Youn)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/3] ARM: EXYNOS4: Add EPLL clock operations
Date: Thu, 30 Jun 2011 16:28:47 +0900	[thread overview]
Message-ID: <BANLkTinzY57NCviNmerwpa_GZL8jmXr_rQ@mail.gmail.com> (raw)
In-Reply-To: <BANLkTi=aGo3WPaftzBxR=Jy6oHAzt+Yhbw@mail.gmail.com>

> So far i was not lucky in finding out a generic way of deriving the
> epll_div values.
> And it doesn't seem to
> 1. Save lines of code or
> 2. Consolidate the PLL code.
>
> Any suggestions for a simpler implementation are welcome.

No, I mean that 'epll_div' values are _not_always_correct_ on Samsung
SoC platform. It depends on board setting. That 'epll_div' values only
works fine when FINpll is 24MHz, as you know these're from reference
values on User Manual, and board maker can change FINpll freq. with
OM[0] pin setting, XXTI and XusbXTI.
So. if you want to make consolidate the PLL code, you should make a
general formula to calculate that epll_div values on the fly OR move
'epll_div' values table into somewhere machine specific file, not into
platform file 'arch/arm/plat-s5p/clock.c'.

        claude

  reply	other threads:[~2011-06-30  7:28 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-06-21 11:24 [PATCH V2 0/3] ARM: Add SPDIF support for EXYNOS4 Naveen Krishna Chatradhi
2011-06-21 11:24 ` Naveen Krishna Chatradhi
2011-06-21 11:24 ` [PATCH v2 1/3] ARM: Samsung: Move duplicate code Naveen Krishna Chatradhi
2011-06-21 11:24   ` Naveen Krishna Chatradhi
2011-07-18  5:35   ` Kukjin Kim
2011-07-18  5:35     ` Kukjin Kim
2011-06-21 11:24 ` [PATCH v2 2/3] ARM: EXYNOS4: Add sclk_spdif clocks Naveen Krishna Chatradhi
2011-06-21 11:24   ` Naveen Krishna Chatradhi
2011-07-18  5:33   ` Kukjin Kim
2011-07-18  5:33     ` Kukjin Kim
2011-07-18 11:25     ` Naveen Krishna Ch
2011-07-18 11:25       ` Naveen Krishna Ch
2011-07-20  9:52       ` Naveen Krishna Ch
2011-07-20  9:52         ` Naveen Krishna Ch
2011-06-21 11:24 ` [PATCH v2 3/3] ARM: EXYNOS4: Add EPLL clock operations Naveen Krishna Chatradhi
2011-06-21 11:24   ` Naveen Krishna Chatradhi
2011-06-22  6:51   ` Naveen Krishna Ch
2011-06-22  6:51     ` Naveen Krishna Ch
2011-06-22  8:01     ` Seungwhan Youn
2011-06-22  8:01       ` Seungwhan Youn
2011-06-30  5:51       ` Naveen Krishna Ch
2011-06-30  5:51         ` Naveen Krishna Ch
2011-06-30  7:28         ` Seungwhan Youn [this message]
2011-06-30  7:28           ` Seungwhan Youn
2011-07-18  5:52   ` Kukjin Kim
2011-07-18  5:52     ` Kukjin Kim
2011-07-18 11:44     ` Naveen Krishna Ch
2011-07-18 11:44       ` Naveen Krishna Ch
2011-06-30  5:54 ` [PATCH V2 0/3] ARM: Add SPDIF support for EXYNOS4 Naveen Krishna Ch
2011-06-30  5:54   ` Naveen Krishna Ch

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