[PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

[PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

[Zeng, Oak]

This allows gfx cache to be probed and invalidated (for none-dirty cache lines)
on a HDP write (from either another GPU or CPU). This should work only for the
memory mapped as RW memory type newly added for arcturus, to achieve some cache
coherence b/t multiple memory clients.

Change-Id: I0a69d0000e48706bb713235bfbc83fcc67774614
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 57d76ee..e01a359 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1272,6 +1272,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 		/* TODO for renoir */
 		mmhub_v1_0_update_power_gating(adev, true);
 		break;
+	case CHIP_ARCTURUS:
+		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
+		break;
 	default:
 		break;
 	}
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

[Zeng, Oak]

Ping...

Regards,
Oak

-----Original Message-----
From: Zeng, Oak <Oak.Zeng@amd.com> 
Sent: Thursday, September 19, 2019 5:17 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Zeng, Oak <Oak.Zeng@amd.com>
Subject: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This should work only for the memory mapped as RW memory type newly added for arcturus, to achieve some cache coherence b/t multiple memory clients.

Change-Id: I0a69d0000e48706bb713235bfbc83fcc67774614
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 57d76ee..e01a359 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1272,6 +1272,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 		/* TODO for renoir */
 		mmhub_v1_0_update_power_gating(adev, true);
 		break;
+	case CHIP_ARCTURUS:
+		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
+		break;
 	default:
 		break;
 	}
--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

[Kuehling, Felix]

I'm pretty sure the gart_enable function is not the right place for 
this. GART is for GPU access to system memory. HDP is for host access to 
GPU memory. Also, I would expect anything done in gart_enable to be 
undone in gart_disable. If that's not the intention, maybe this should 
go in gmc_v9_0_hw_init.

Regards,
   Felix

On 2019-10-04 10:56, Zeng, Oak wrote:
> Ping...
>
> Regards,
> Oak
>
> -----Original Message-----
> From: Zeng, Oak <Oak.Zeng@amd.com>
> Sent: Thursday, September 19, 2019 5:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Zeng, Oak <Oak.Zeng@amd.com>
> Subject: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus
>
> This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This should work only for the memory mapped as RW memory type newly added for arcturus, to achieve some cache coherence b/t multiple memory clients.
>
> Change-Id: I0a69d0000e48706bb713235bfbc83fcc67774614
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 57d76ee..e01a359 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1272,6 +1272,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
>   		/* TODO for renoir */
>   		mmhub_v1_0_update_power_gating(adev, true);
>   		break;
> +	case CHIP_ARCTURUS:
> +		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
> +		break;
>   	default:
>   		break;
>   	}
> --
> 2.7.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

[Zeng, Oak]

Agreed. I will move none gart logic from gmc_v9_0_gart_enable to gmc_v9_0_hw_init

Regards,
Oak

-----Original Message-----
From: Kuehling, Felix <Felix.Kuehling@amd.com> 
Sent: Friday, October 4, 2019 11:03 AM
To: Zeng, Oak <Oak.Zeng@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Koenig, Christian <Christian.Koenig@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for arcturus

I'm pretty sure the gart_enable function is not the right place for this. GART is for GPU access to system memory. HDP is for host access to GPU memory. Also, I would expect anything done in gart_enable to be undone in gart_disable. If that's not the intention, maybe this should go in gmc_v9_0_hw_init.

Regards,
   Felix

On 2019-10-04 10:56, Zeng, Oak wrote:
> Ping...
>
> Regards,
> Oak
>
> -----Original Message-----
> From: Zeng, Oak <Oak.Zeng@amd.com>
> Sent: Thursday, September 19, 2019 5:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Kuehling, Felix <Felix.Kuehling@amd.com>; Koenig, Christian 
> <Christian.Koenig@amd.com>; Zeng, Oak <Oak.Zeng@amd.com>
> Subject: [PATCH] drm/amdgpu: Enable gfx cache probing on HDP write for 
> arcturus
>
> This allows gfx cache to be probed and invalidated (for none-dirty cache lines) on a HDP write (from either another GPU or CPU). This should work only for the memory mapped as RW memory type newly added for arcturus, to achieve some cache coherence b/t multiple memory clients.
>
> Change-Id: I0a69d0000e48706bb713235bfbc83fcc67774614
> Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 57d76ee..e01a359 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1272,6 +1272,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
>   		/* TODO for renoir */
>   		mmhub_v1_0_update_power_gating(adev, true);
>   		break;
> +	case CHIP_ARCTURUS:
> +		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
> +		break;
>   	default:
>   		break;
>   	}
> --
> 2.7.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx