* [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method
@ 2021-03-23 20:44 Rohit Khaire
2021-03-29 15:22 ` Deucher, Alexander
2021-03-29 15:53 ` Luben Tuikov
0 siblings, 2 replies; 4+ messages in thread
From: Rohit Khaire @ 2021-03-23 20:44 UTC (permalink / raw)
To: amd-gfx, HaiJun Chang, Davis Ming, Monk Liu
Cc: Jack Xiao, Feifei Xu, Kevin Wang, Tuikov Luben, Rohit Khaire,
Deucher Alexander, Christian König, Hawking Zhang
Add 3 sub flags to notify guest for indirect access of gc, mmhub and ih
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +++++++++++
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 17 +++++++++++++++--
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 8dd624c20f89..0224f352d060 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -104,6 +104,17 @@ enum AMDGIM_FEATURE_FLAG {
AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
/* PP ONE VF MODE in GIM */
AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
+ /* Indirect Reg Access enabled */
+ AMDGIM_FETURE_INDIRECT_REG_ACCESS = (1 << 5),
+};
+
+enum AMDGIM_REG_ACCESS_FLAG {
+ /* Use PSP to program IH_RB_CNTL */
+ AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
+ /* Use RLC to program MMHUB regs */
+ AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),
+ /* Use RLC to program GC regs */
+ AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),
};
struct amdgim_pf2vf_info_v1 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
index 5355827ed0ae..7fed6377d931 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -90,11 +90,22 @@ union amd_sriov_msg_feature_flags {
uint32_t host_flr_vramlost : 1;
uint32_t mm_bw_management : 1;
uint32_t pp_one_vf_mode : 1;
- uint32_t reserved : 27;
+ uint32_t reg_indirect_acc : 1;
+ uint32_t reserved : 26;
} flags;
uint32_t all;
};
+union amd_sriov_reg_access_flags {
+ struct {
+ uint32_t vf_reg_access_ih : 1;
+ uint32_t vf_reg_access_mmhub : 1;
+ uint32_t vf_reg_access_gc : 1;
+ uint32_t reserved : 29;
+ } flags;
+ uint32_t all;
+};
+
union amd_sriov_msg_os_info {
struct {
uint32_t windows : 1;
@@ -149,8 +160,10 @@ struct amd_sriov_msg_pf2vf_info {
/* identification in ROCm SMI */
uint64_t uuid;
uint32_t fcn_idx;
+ /* flags to indicate which register access method VF should use */
+ union amd_sriov_reg_access_flags reg_access_flags;
/* reserved */
- uint32_t reserved[256-26];
+ uint32_t reserved[256-27];
};
struct amd_sriov_msg_vf2pf_info_header {
--
2.17.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method
2021-03-23 20:44 [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method Rohit Khaire
@ 2021-03-29 15:22 ` Deucher, Alexander
2021-03-29 15:53 ` Luben Tuikov
1 sibling, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2021-03-29 15:22 UTC (permalink / raw)
To: Khaire, Rohit, amd-gfx, Chang, HaiJun, Ming, Davis, Liu, Monk
Cc: Xiao, Jack, Xu, Feifei, Wang, Kevin(Yang),
Tuikov, Luben, Koenig, Christian, Zhang, Hawking
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[AMD Official Use Only - Internal Distribution Only]
Maybe add something like the following in your commit message:
"The host sends this data depending on L1 policy version/asic and other scenarios. These flags ensure that there is compatibility between different guest/host/vbios versions."
With that added, this patch is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
________________________________
From: Khaire, Rohit <Rohit.Khaire@amd.com>
Sent: Tuesday, March 23, 2021 4:44 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Chang, HaiJun <HaiJun.Chang@amd.com>; Ming, Davis <Davis.Ming@amd.com>; Liu, Monk <Monk.Liu@amd.com>
Cc: Tuikov, Luben <Luben.Tuikov@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Khaire, Rohit <Rohit.Khaire@amd.com>
Subject: [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method
Add 3 sub flags to notify guest for indirect access of gc, mmhub and ih
Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +++++++++++
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 17 +++++++++++++++--
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 8dd624c20f89..0224f352d060 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -104,6 +104,17 @@ enum AMDGIM_FEATURE_FLAG {
AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
/* PP ONE VF MODE in GIM */
AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
+ /* Indirect Reg Access enabled */
+ AMDGIM_FETURE_INDIRECT_REG_ACCESS = (1 << 5),
+};
+
+enum AMDGIM_REG_ACCESS_FLAG {
+ /* Use PSP to program IH_RB_CNTL */
+ AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
+ /* Use RLC to program MMHUB regs */
+ AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),
+ /* Use RLC to program GC regs */
+ AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),
};
struct amdgim_pf2vf_info_v1 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
index 5355827ed0ae..7fed6377d931 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
@@ -90,11 +90,22 @@ union amd_sriov_msg_feature_flags {
uint32_t host_flr_vramlost : 1;
uint32_t mm_bw_management : 1;
uint32_t pp_one_vf_mode : 1;
- uint32_t reserved : 27;
+ uint32_t reg_indirect_acc : 1;
+ uint32_t reserved : 26;
} flags;
uint32_t all;
};
+union amd_sriov_reg_access_flags {
+ struct {
+ uint32_t vf_reg_access_ih : 1;
+ uint32_t vf_reg_access_mmhub : 1;
+ uint32_t vf_reg_access_gc : 1;
+ uint32_t reserved : 29;
+ } flags;
+ uint32_t all;
+};
+
union amd_sriov_msg_os_info {
struct {
uint32_t windows : 1;
@@ -149,8 +160,10 @@ struct amd_sriov_msg_pf2vf_info {
/* identification in ROCm SMI */
uint64_t uuid;
uint32_t fcn_idx;
+ /* flags to indicate which register access method VF should use */
+ union amd_sriov_reg_access_flags reg_access_flags;
/* reserved */
- uint32_t reserved[256-26];
+ uint32_t reserved[256-27];
};
struct amd_sriov_msg_vf2pf_info_header {
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method
2021-03-23 20:44 [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method Rohit Khaire
2021-03-29 15:22 ` Deucher, Alexander
@ 2021-03-29 15:53 ` Luben Tuikov
2021-03-29 19:55 ` Khaire, Rohit
1 sibling, 1 reply; 4+ messages in thread
From: Luben Tuikov @ 2021-03-29 15:53 UTC (permalink / raw)
To: Rohit Khaire, amd-gfx, HaiJun Chang, Davis Ming, Monk Liu
Cc: Jack Xiao, Feifei Xu, Kevin Wang, Deucher Alexander,
Christian König, Hawking Zhang
On 2021-03-23 4:44 p.m., Rohit Khaire wrote:
> Add 3 sub flags to notify guest for indirect access of gc, mmhub and ih
>
> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 17 +++++++++++++++--
> 2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 8dd624c20f89..0224f352d060 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -104,6 +104,17 @@ enum AMDGIM_FEATURE_FLAG {
> AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
> /* PP ONE VF MODE in GIM */
> AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
> + /* Indirect Reg Access enabled */
> + AMDGIM_FETURE_INDIRECT_REG_ACCESS = (1 << 5),
Spelling: FETURE --> FEATURE
> +};
> +
> +enum AMDGIM_REG_ACCESS_FLAG {
> + /* Use PSP to program IH_RB_CNTL */
> + AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
> + /* Use RLC to program MMHUB regs */
> + AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),
> + /* Use RLC to program GC regs */
> + AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),
> };
>
> struct amdgim_pf2vf_info_v1 {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> index 5355827ed0ae..7fed6377d931 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> @@ -90,11 +90,22 @@ union amd_sriov_msg_feature_flags {
> uint32_t host_flr_vramlost : 1;
> uint32_t mm_bw_management : 1;
> uint32_t pp_one_vf_mode : 1;
> - uint32_t reserved : 27;
> + uint32_t reg_indirect_acc : 1;
> + uint32_t reserved : 26;
> } flags;
> uint32_t all;
> };
>
> +union amd_sriov_reg_access_flags {
> + struct {
> + uint32_t vf_reg_access_ih : 1;
> + uint32_t vf_reg_access_mmhub : 1;
> + uint32_t vf_reg_access_gc : 1;
> + uint32_t reserved : 29;
> + } flags;
> + uint32_t all;
> +};
> +
> union amd_sriov_msg_os_info {
> struct {
> uint32_t windows : 1;
> @@ -149,8 +160,10 @@ struct amd_sriov_msg_pf2vf_info {
> /* identification in ROCm SMI */
> uint64_t uuid;
> uint32_t fcn_idx;
> + /* flags to indicate which register access method VF should use */
> + union amd_sriov_reg_access_flags reg_access_flags;
"to" --> "which" to become
/* flags which indicate the register access method VF should use */
With these fixed, and Alex's comments addressed, this patch is:
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
> /* reserved */
> - uint32_t reserved[256-26];
> + uint32_t reserved[256-27];
> };
>
> struct amd_sriov_msg_vf2pf_info_header {
>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method
2021-03-29 15:53 ` Luben Tuikov
@ 2021-03-29 19:55 ` Khaire, Rohit
0 siblings, 0 replies; 4+ messages in thread
From: Khaire, Rohit @ 2021-03-29 19:55 UTC (permalink / raw)
To: Tuikov, Luben, amd-gfx, Chang, HaiJun, Ming, Davis, Liu, Monk
Cc: Xiao, Jack, Xu, Feifei, Wang, Kevin(Yang),
Deucher, Alexander, Koenig, Christian, Zhang, Hawking
[AMD Public Use]
Thanks Alex and Luben.
I've addressed the comments and pushed the changes.
Rohit
-----Original Message-----
From: Tuikov, Luben <Luben.Tuikov@amd.com>
Sent: March 29, 2021 11:54 AM
To: Khaire, Rohit <Rohit.Khaire@amd.com>; amd-gfx@lists.freedesktop.org; Chang, HaiJun <HaiJun.Chang@amd.com>; Ming, Davis <Davis.Ming@amd.com>; Liu, Monk <Monk.Liu@amd.com>
Cc: Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Xiao, Jack <Jack.Xiao@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method
On 2021-03-23 4:44 p.m., Rohit Khaire wrote:
> Add 3 sub flags to notify guest for indirect access of gc, mmhub and ih
>
> Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +++++++++++
> drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 17 +++++++++++++++--
> 2 files changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 8dd624c20f89..0224f352d060 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -104,6 +104,17 @@ enum AMDGIM_FEATURE_FLAG {
> AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
> /* PP ONE VF MODE in GIM */
> AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
> + /* Indirect Reg Access enabled */
> + AMDGIM_FETURE_INDIRECT_REG_ACCESS = (1 << 5),
Spelling: FETURE --> FEATURE
> +};
> +
> +enum AMDGIM_REG_ACCESS_FLAG {
> + /* Use PSP to program IH_RB_CNTL */
> + AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
> + /* Use RLC to program MMHUB regs */
> + AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),
> + /* Use RLC to program GC regs */
> + AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),
> };
>
> struct amdgim_pf2vf_info_v1 {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> index 5355827ed0ae..7fed6377d931 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
> @@ -90,11 +90,22 @@ union amd_sriov_msg_feature_flags {
> uint32_t host_flr_vramlost : 1;
> uint32_t mm_bw_management : 1;
> uint32_t pp_one_vf_mode : 1;
> - uint32_t reserved : 27;
> + uint32_t reg_indirect_acc : 1;
> + uint32_t reserved : 26;
> } flags;
> uint32_t all;
> };
>
> +union amd_sriov_reg_access_flags {
> + struct {
> + uint32_t vf_reg_access_ih : 1;
> + uint32_t vf_reg_access_mmhub : 1;
> + uint32_t vf_reg_access_gc : 1;
> + uint32_t reserved : 29;
> + } flags;
> + uint32_t all;
> +};
> +
> union amd_sriov_msg_os_info {
> struct {
> uint32_t windows : 1;
> @@ -149,8 +160,10 @@ struct amd_sriov_msg_pf2vf_info {
> /* identification in ROCm SMI */
> uint64_t uuid;
> uint32_t fcn_idx;
> + /* flags to indicate which register access method VF should use */
> + union amd_sriov_reg_access_flags reg_access_flags;
"to" --> "which" to become
/* flags which indicate the register access method VF should use */
With these fixed, and Alex's comments addressed, this patch is:
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Regards,
Luben
> /* reserved */
> - uint32_t reserved[256-26];
> + uint32_t reserved[256-27];
> };
>
> struct amd_sriov_msg_vf2pf_info_header {
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-03-29 19:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-23 20:44 [PATCH] drm/amdgpu: Add new PF2VF flags for VF register access method Rohit Khaire
2021-03-29 15:22 ` Deucher, Alexander
2021-03-29 15:53 ` Luben Tuikov
2021-03-29 19:55 ` Khaire, Rohit
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