[Intel-gfx] [PATCH v4 0/6] Panel replay phase1 implementation

[Intel-gfx] [PATCH v4 0/6] Panel replay phase1 implementation

[Animesh Manna]

Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.

These patches are basic enablement patches added on top of
existing psr framework to enable full-screen live active frame
update mode of panel replay. Panel replay also can be enabled
in selective update mode which will be enabled in a incremental
approach.

As per current design panel replay priority is higher than psr.
intel_dp->psr.panel_replay_enabled flag indicate panel replay is enabled.
intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled indicates
panel replay is enabled in selective update mode.
intel_dp->psr.panel_replay_enabled + intel_dp->psr.psr2_enabled +
intel_psr.selective_fetch enabled indicates panel replay is
enabled in selective update mode with selective fetch.
PSR replated flags remain same like before.

Note: The patches are under testing by using panel replay emulator and
panel is not avalible.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (5):
  drm/panelreplay: dpcd register definition for panelreplay
  drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
  drm/i915/panelreplay: Initializaton and compute config for panel
    replay
  drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
  drm/i915/panelreplay: enable/disable panel replay

Jouni Högander (1):
  drm/i915/psr: Move psr specific dpcd init into own function

 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_types.h    |  13 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  44 +++-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 197 ++++++++++++------
 include/drm/display/drm_dp.h                  |  11 +
 6 files changed, 199 insertions(+), 70 deletions(-)

-- 
2.29.0

[Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Animesh Manna]

DPCD register definition added to check and enable panel replay
capability of the sink.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e69cece404b3..a38dc5f1731e 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -543,6 +543,10 @@
 /* DFP Capability Extension */
 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
 
+#define DP_PANEL_REPLAY_CAP                 0x0b0
+# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
+# define DP_PANEL_REPLAY_SU_SUPPORT         (1 << 1)
+
 /* Link Configuration */
 #define	DP_LINK_BW_SET		            0x100
 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
@@ -716,6 +720,13 @@
 #define DP_BRANCH_DEVICE_CTRL		    0x1a1
 # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
 
+#define PANEL_REPLAY_CONFIG                             0x1b0
+# define DP_PANEL_REPLAY_ENABLE                         (1 << 0)
+# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR            (1 << 3)
+# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR              (1 << 4)
+# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR         (1 << 5)
+# define DP_PANEL_REPLAY_SU_ENABLE                      (1 << 6)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.29.0

[Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

[Animesh Manna]

Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY()
macro to check for panel replay capability.

v1: Initial version.
v2: DISPLAY_VER() removed as HAS_DP20() is having platform check. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 8198401aa5be..ab615a3199da 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -61,6 +61,7 @@ struct drm_printer;
 #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
 #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
 #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
+#define HAS_PANEL_REPLAY(dev_priv)	(HAS_DP20(dev_priv))
 #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)
 #define HAS_SAGV(i915)			(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
-- 
2.29.0

[Intel-gfx] [PATCH v4 3/6] drm/i915/psr: Move psr specific dpcd init into own function

[Animesh Manna]

From: Jouni Högander <jouni.hogander@intel.com>

This patch is preparing adding panel replay specific dpcd init.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 39 +++++++++++++-----------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 72887c29fb51..b1c0494826f9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -472,27 +472,22 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	intel_dp->psr.su_y_granularity = y;
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
 {
-	struct drm_i915_private *dev_priv =
+	struct drm_i915_private *i915 =
 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 
-	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-			 sizeof(intel_dp->psr_dpcd));
-
-	if (!intel_dp->psr_dpcd[0])
-		return;
-	drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
+	drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
 		    intel_dp->psr_dpcd[0]);
 
 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "PSR support not currently available for this panel\n");
 		return;
 	}
 
 	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "Panel lacks power state control, PSR cannot be enabled\n");
 		return;
 	}
@@ -501,7 +496,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
-	if (DISPLAY_VER(dev_priv) >= 9 &&
+	if (DISPLAY_VER(i915) >= 9 &&
 	    (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 		bool y_req = intel_dp->psr_dpcd[1] &
 			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
@@ -519,14 +514,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 		 * GTC first.
 		 */
 		intel_dp->psr.sink_psr2_support = y_req && alpm;
-		drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
+		drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
 			    intel_dp->psr.sink_psr2_support ? "" : "not ");
+	}
+}
 
-		if (intel_dp->psr.sink_psr2_support) {
-			intel_dp->psr.colorimetry_support =
-				intel_dp_get_colorimetry_status(intel_dp);
-			intel_dp_get_su_granularity(intel_dp);
-		}
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+			 sizeof(intel_dp->psr_dpcd));
+
+	if (intel_dp->psr_dpcd[0])
+		_psr_init_dpcd(intel_dp);
+	/* TODO: Add PR case here */
+
+	if (intel_dp->psr.sink_psr2_support) {
+		intel_dp->psr.colorimetry_support =
+			intel_dp_get_colorimetry_status(intel_dp);
+		intel_dp_get_su_granularity(intel_dp);
 	}
 }
 
-- 
2.29.0

[Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Animesh Manna]

Modify existing PSR implementation to enable panel replay feature of DP 2.0
which is similar to PSR feature of EDP panel. There is different DPCD
address to check panel capability compare to PSR and vsc sdp header
is different.

v1: Initial version.
v2:
- Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni]
- Code restructured around intel_panel_replay_init
and renamed to intel_panel_replay_init_dpcd. [Jouni]
- Remove the initial code modification around has_psr2 flag. [Jouni]
- Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
enable in intel_psr_post_plane_update. [Jouni]
v3:
- Initialize both psr and panel-replay. [Jouni]
- Initialize both panel replay and psr if detected. [Jouni]
- Refactoring psr function by introducing _psr_compute_config(). [Jouni]
- Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
- Enable panel replay dpcd initialization in a separate patch. [Jouni]

v4:
- HAS_PANEL_REPLAY() check not needed during sink capability check.[Jouni]
- Set either panel replay source support or psr.[Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    | 12 ++-
 drivers/gpu/drm/i915/display/intel_dp.c       | 44 ++++++++--
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  3 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 87 +++++++++++++------
 4 files changed, 107 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..97cef458f42b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1202,6 +1202,7 @@ struct intel_crtc_state {
 	bool has_psr2;
 	bool enable_psr2_sel_fetch;
 	bool req_psr2_sdp_prior_scanline;
+	bool has_panel_replay;
 	bool wm_level_disabled;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
@@ -1693,6 +1694,8 @@ struct intel_psr {
 	bool irq_aux_error;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
+	bool source_panel_replay_support;
+	bool sink_panel_replay_support;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
@@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
 			   (intel_dp)->psr.source_support)
 
+#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
+			  (intel_dp)->psr.source_panel_replay_support)
+
 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
 {
-	if (!intel_encoder_is_dp(encoder))
+	if (intel_encoder_is_dp(encoder) || (encoder->type == INTEL_OUTPUT_DP_MST))
+		return CAN_PSR(enc_to_intel_dp(encoder)) || CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
+	else
 		return false;
-
-	return CAN_PSR(enc_to_intel_dp(encoder));
 }
 
 static inline struct intel_digital_port *
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd3..b3301cf0da0a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2337,12 +2337,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	/*
-	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc->revision = 0x5;
+	if (crtc_state->has_panel_replay) {
+		/*
+		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+		 * Encoding/Colorimetry Format indication.
+		 */
+		vsc->revision = 0x7;
+	} else {
+		/*
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+		 * Colorimetry Format indication.
+		 */
+		vsc->revision = 0x5;
+	}
+
 	vsc->length = 0x13;
 
 	/* DP 1.4a spec, Table 2-120 */
@@ -2451,6 +2461,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
 			vsc->revision = 0x4;
 			vsc->length = 0xe;
 		}
+	} else if (crtc_state->has_panel_replay) {
+		if (intel_dp->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [Panel Replay with colorimetry info] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [Panel Replay without colorimetry info]
+			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+			 * VSC SDP supporting 3D stereo + Panel Replay.
+			 */
+			vsc->revision = 0x6;
+			vsc->length = 0x10;
+		}
 	} else {
 		/*
 		 * [PSR1]
@@ -3744,10 +3769,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
 	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
 
 	/*
-	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
-	 * per DP 1.4a spec.
+	 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
+	 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
+	 * Encoding/Colorimetry Format as per DP 2.0 spec.
 	 */
-	if (vsc->revision != 0x5)
+	if (vsc->revision != 0x5 || vsc->revision != 0x7)
 		goto out;
 
 	/* VSC SDP Payload for DB16 through DB18 */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c8..07a3ab473be2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -44,6 +44,7 @@
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
 #include "skl_scaler.h"
+#include "intel_psr.h"
 
 static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
 					  const struct drm_display_mode *adjusted_mode,
@@ -398,6 +399,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 
 	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
 
+	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b1c0494826f9..8dd61c62492d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -472,6 +472,24 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	intel_dp->psr.su_y_granularity = y;
 }
 
+static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u8 pr_dpcd = 0;
+
+	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
+
+	if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Panel replay is not supported by panel\n");
+		return;
+	}
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "Panel replay is supported by panel\n");
+	intel_dp->psr.sink_panel_replay_support = true;
+}
+
 static void _psr_init_dpcd(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *i915 =
@@ -521,12 +539,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
 
 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 {
+	_panel_replay_init_dpcd(intel_dp);
+
 	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 			 sizeof(intel_dp->psr_dpcd));
 
 	if (intel_dp->psr_dpcd[0])
 		_psr_init_dpcd(intel_dp);
-	/* TODO: Add PR case here */
 
 	if (intel_dp->psr.sink_psr2_support) {
 		intel_dp->psr.colorimetry_support =
@@ -1207,13 +1226,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	return false;
 }
 
-void intel_psr_compute_config(struct intel_dp *intel_dp,
-			      struct intel_crtc_state *crtc_state,
-			      struct drm_connector_state *conn_state)
+static bool _psr_compute_config(struct intel_dp *intel_dp,
+				struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	const struct drm_display_mode *adjusted_mode =
-		&crtc_state->hw.adjusted_mode;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int psr_setup_time;
 
 	/*
@@ -1221,10 +1238,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	 * So if VRR is enabled, do not enable PSR.
 	 */
 	if (crtc_state->vrr.enable)
-		return;
+		return false;
 
 	if (!CAN_PSR(intel_dp))
-		return;
+		return false;
+
+	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
+	if (psr_setup_time < 0) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
+			    intel_dp->psr_dpcd[1]);
+		return false;
+	}
+
+	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
+	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "PSR condition failed: PSR setup time (%d us) too long\n",
+			    psr_setup_time);
+		return false;
+	}
+
+	return true;
+}
+
+void intel_psr_compute_config(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      struct drm_connector_state *conn_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	if (!psr_global_enabled(intel_dp)) {
 		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
@@ -1234,7 +1277,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->psr.sink_not_reliable) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR sink implementation is not reliable\n");
-		return;
 	}
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -1243,23 +1285,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 		return;
 	}
 
-	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
-	if (psr_setup_time < 0) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
-			    intel_dp->psr_dpcd[1]);
-		return;
-	}
-
-	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
-	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "PSR condition failed: PSR setup time (%d us) too long\n",
-			    psr_setup_time);
-		return;
-	}
+	if (CAN_PANEL_REPLAY(intel_dp))
+		crtc_state->has_panel_replay = true;
+	else
+		crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
 
-	crtc_state->has_psr = true;
 	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
@@ -2699,7 +2729,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 
-	if (!HAS_PSR(dev_priv))
+	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
 		return;
 
 	/*
@@ -2717,7 +2747,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		return;
 	}
 
-	intel_dp->psr.source_support = true;
+	if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
+		intel_dp->psr.source_panel_replay_support = true;
+	else
+		intel_dp->psr.source_support = true;
 
 	/* Set link_standby x link_off defaults */
 	if (DISPLAY_VER(dev_priv) < 12)
-- 
2.29.0

[Intel-gfx] [PATCH v4 5/6] drm/i915/panelreplay: Enable panel replay dpcd initialization for DP

[Animesh Manna]

Due to similarity panel replay dpcd initialization got added in psr
function which is specific for edp panel. This patch enables panel
replay initialization for dp connector.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 8dd61c62492d..c92acc7be4f1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2732,6 +2732,9 @@ void intel_psr_init(struct intel_dp *intel_dp)
 	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
 		return;
 
+	if (!intel_dp_is_edp(intel_dp))
+		intel_psr_init_dpcd(intel_dp);
+
 	/*
 	 * HSW spec explicitly says PSR is tied to port A.
 	 * BDW+ platforms have a instance of PSR registers per transcoder but
-- 
2.29.0

[Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay

[Animesh Manna]

TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Bspec: 1407940617

v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]

v3: cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]

Note: Initial plan is to enable panel replay in  full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 72 ++++++++++++++-----
 2 files changed, 57 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 97cef458f42b..46f2e8a42d1d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1696,6 +1696,7 @@ struct intel_psr {
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
+	bool panel_replay_enabled;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index c92acc7be4f1..ccb714f2c9e6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -596,8 +596,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 dpcd_val = DP_PSR_ENABLE;
 
-	/* Enable ALPM at sink for psr2 */
+	if (intel_dp->psr.panel_replay_enabled) {
+		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+				   DP_PANEL_REPLAY_ENABLE);
+		return;
+	}
+
 	if (intel_dp->psr.psr2_enabled) {
+		/* Enable ALPM at sink for psr2 */
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 				   DP_ALPM_ENABLE |
 				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -747,6 +753,18 @@ static int psr2_block_count(struct intel_dp *intel_dp)
 	return psr2_block_count_lines(intel_dp) / 4;
 }
 
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (intel_dp->psr.psr2_sel_fetch_enabled)
+		intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+			     0, ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1295,6 +1313,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
 				     &crtc_state->psr_vsc);
+
+	drm_dbg_kms(&dev_priv->drm, "has_pr = %d, has_psr = %d, has_psr2 = %d, infoframes_enable = %d\n",
+		    crtc_state->has_panel_replay, crtc_state->has_psr, crtc_state->has_psr2, crtc_state->infoframes.enable);
 }
 
 void intel_psr_get_config(struct intel_encoder *encoder,
@@ -1310,18 +1331,23 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 		return;
 
 	intel_dp = &dig_port->dp;
-	if (!CAN_PSR(intel_dp))
+	if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
 		return;
 
 	mutex_lock(&intel_dp->psr.lock);
 	if (!intel_dp->psr.enabled)
 		goto unlock;
 
-	/*
-	 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
-	 * enabled/disabled because of frontbuffer tracking and others.
-	 */
-	pipe_config->has_psr = true;
+	if (intel_dp->psr.panel_replay_enabled) {
+		pipe_config->has_panel_replay = true;
+	} else {
+		/*
+		 * Not possible to read EDP_PSR/PSR2_CTL registers as it is
+		 * enabled/disabled because of frontbuffer tracking and others.
+		 */
+		pipe_config->has_psr = true;
+	}
+
 	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
 	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
@@ -1358,8 +1384,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 
 	lockdep_assert_held(&intel_dp->psr.lock);
 
-	/* psr1 and psr2 are mutually exclusive.*/
-	if (intel_dp->psr.psr2_enabled)
+	/* psr1, psr2 and panel-replay are mutually exclusive.*/
+	if (intel_dp->psr.panel_replay_enabled)
+		dg2_activate_panel_replay(intel_dp);
+	else if (intel_dp->psr.psr2_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -1538,6 +1566,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
@@ -1553,8 +1582,12 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	if (!psr_interrupt_error_check(intel_dp))
 		return;
 
-	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
-		    intel_dp->psr.psr2_enabled ? "2" : "1");
+	if (intel_dp->psr.panel_replay_enabled)
+		drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n");
+	else
+		drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
+			    intel_dp->psr.psr2_enabled ? "2" : "1");
+
 	intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
 	intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
 	intel_psr_enable_sink(intel_dp);
@@ -1583,7 +1616,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		return;
 	}
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.panel_replay_enabled) {
+		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+	} else if (intel_dp->psr.psr2_enabled) {
 		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 
 		val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder),
@@ -1632,8 +1668,11 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	if (!intel_dp->psr.enabled)
 		return;
 
-	drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
-		    intel_dp->psr.psr2_enabled ? "2" : "1");
+	if (intel_dp->psr.panel_replay_enabled)
+		drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n");
+	else
+		drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
+			    intel_dp->psr.psr2_enabled ? "2" : "1");
 
 	intel_psr_exit(intel_dp);
 	intel_psr_wait_exit_locked(intel_dp);
@@ -1666,6 +1705,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
 
 	intel_dp->psr.enabled = false;
+	intel_dp->psr.panel_replay_enabled = false;
 	intel_dp->psr.psr2_enabled = false;
 	intel_dp->psr.psr2_sel_fetch_enabled = false;
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
@@ -2235,7 +2275,7 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 	struct intel_encoder *encoder;
 
-	if (!crtc_state->has_psr)
+	if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
 		return;
 
 	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
@@ -2276,7 +2316,7 @@ void intel_psr_post_plane_update(const struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	if (!HAS_PSR(dev_priv))
+	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
 		return;
 
 	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
-- 
2.29.0

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Panel replay phase1 implementation (rev6)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev6)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev6)

[Patchwork]

== Series Details ==

Series: Panel replay phase1 implementation (rev6)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory

[Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10317 bytes --]

== Series Details ==

Series: Panel replay phase1 implementation (rev6)
URL   : https://patchwork.freedesktop.org/series/94470/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13558 -> Patchwork_94470v6
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/index.html

Participating hosts (39 -> 39)
------------------------------

  Additional (1): bat-dg2-9 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_94470v6 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-rplp-1:         NOTRUN -> [SKIP][1] ([i915#7456])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@debugfs_test@basic-hwmon.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-jsl-3:          [PASS][2] -> [ABORT][3] ([i915#5122])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_mmap@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-dg2-9:          NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-rplp-1:         NOTRUN -> [SKIP][7] ([i915#3282])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - bat-dg2-9:          NOTRUN -> [SKIP][8] ([i915#5354] / [i915#7561])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-9:          NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@i915_pm_rps@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-jsl-3:          [PASS][10] -> [FAIL][11] ([fdo#103375])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][12] ([i915#5190])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-9:          NOTRUN -> [SKIP][13] ([i915#4215] / [i915#5190])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - bat-dg2-9:          NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-rplp-1:         NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - bat-dg2-9:          NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-rplp-1:         NOTRUN -> [SKIP][17] ([fdo#109285])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@kms_force_connector_basic@force-load-detect.html
    - bat-dg2-9:          NOTRUN -> [SKIP][18] ([fdo#109285])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-9:          NOTRUN -> [SKIP][19] ([i915#5274])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         NOTRUN -> [SKIP][20] ([i915#1845] / [i915#5354]) +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  * igt@kms_psr@primary_page_flip:
    - bat-rplp-1:         NOTRUN -> [SKIP][21] ([i915#1072]) +1 similar issue
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-dg2-9:          NOTRUN -> [SKIP][22] ([i915#1072]) +3 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html
    - bat-rplp-1:         NOTRUN -> [ABORT][23] ([i915#8442] / [i915#8668] / [i915#8712])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg2-9:          NOTRUN -> [SKIP][24] ([i915#3555])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-9:          NOTRUN -> [SKIP][25] ([i915#3708])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-9:          NOTRUN -> [SKIP][26] ([i915#3708] / [i915#4077]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-9:          NOTRUN -> [SKIP][27] ([i915#3291] / [i915#3708]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-dg2-9/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][28] ([i915#5334]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
    - bat-rpls-2:         [DMESG-FAIL][30] ([i915#4258] / [i915#7913]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712


Build changes
-------------

  * Linux: CI_DRM_13558 -> Patchwork_94470v6

  CI-20190529: 20190529
  CI_DRM_13558: 2d5f57f6436263ecb456228603356d81173b1ceb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_94470v6: 2d5f57f6436263ecb456228603356d81173b1ceb @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

e9155cf8b7ff drm/i915/panelreplay: enable/disable panel replay
560c648832c8 drm/i915/panelreplay: Enable panel replay dpcd initialization for DP
75d8a90c1e23 drm/i915/panelreplay: Initializaton and compute config for panel replay
09dffb648065 drm/i915/psr: Move psr specific dpcd init into own function
9b80640576e3 drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro
93914df5d0ea drm/panelreplay: dpcd register definition for panelreplay

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/index.html

[-- Attachment #2: Type: text/html, Size: 12209 bytes --]

Re: [Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

[Hogander, Jouni]

On Thu, 2023-08-24 at 09:39 +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY()
> macro to check for panel replay capability.
> 
> v1: Initial version.
> v2: DISPLAY_VER() removed as HAS_DP20() is having platform check.
> [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 8198401aa5be..ab615a3199da 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -61,6 +61,7 @@ struct drm_printer;
>  #define HAS_MSO(i915)                  (DISPLAY_VER(i915) >= 12)
>  #define HAS_OVERLAY(i915)              (DISPLAY_INFO(i915)-
> >has_overlay)
>  #define HAS_PSR(i915)                  (DISPLAY_INFO(i915)->has_psr)
> +#define HAS_PANEL_REPLAY(dev_priv)     (HAS_DP20(dev_priv))

I think you can drop this macro and use HAD_DP20 directly.

BR,

Jouni Högander

>  #define HAS_PSR_HW_TRACKING(i915)      (DISPLAY_INFO(i915)-
> >has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(i915)       (DISPLAY_VER(i915) >= 12)
>  #define HAS_SAGV(i915)                 (DISPLAY_VER(i915) >= 9 &&
> !IS_LP(i915))

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay

[Hogander, Jouni]

On Thu, 2023-08-24 at 09:39 +0530, Animesh Manna wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from
> source
> and sink is enabled through panel replay dpcd configuration address.
> 
> Bspec: 1407940617
> 
> v1: Initial version.
> v2:
> - Use pr_* flags instead psr_* flags. [Jouni]
> - Remove intel_dp_is_edp check as edp1.5 also has panel replay.
> [Jouni]
> 
> v3: cover letter updated and selective fetch condition check is added
> before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
> 
> Note: Initial plan is to enable panel replay in  full-screen live
> active
> frame update mode. In a incremental approach panel replay will be
> enabled
> in selctive update mode if there is any gap in curent implementation.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 72 ++++++++++++++---
> --
>  2 files changed, 57 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 97cef458f42b..46f2e8a42d1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1696,6 +1696,7 @@ struct intel_psr {
>         u16 su_y_granularity;
>         bool source_panel_replay_support;
>         bool sink_panel_replay_support;
> +       bool panel_replay_enabled;
>         u32 dc3co_exitline;
>         u32 dc3co_exit_delay;
>         struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index c92acc7be4f1..ccb714f2c9e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -596,8 +596,14 @@ static void intel_psr_enable_sink(struct
> intel_dp *intel_dp)
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>         u8 dpcd_val = DP_PSR_ENABLE;
>  
> -       /* Enable ALPM at sink for psr2 */
> +       if (intel_dp->psr.panel_replay_enabled) {
> +               drm_dp_dpcd_writeb(&intel_dp->aux,
> PANEL_REPLAY_CONFIG,
> +                                  DP_PANEL_REPLAY_ENABLE);
> +               return;
> +       }
> +
>         if (intel_dp->psr.psr2_enabled) {
> +               /* Enable ALPM at sink for psr2 */
>                 drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG,
>                                    DP_ALPM_ENABLE |
>                                   
> DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> @@ -747,6 +753,18 @@ static int psr2_block_count(struct intel_dp
> *intel_dp)
>         return psr2_block_count_lines(intel_dp) / 4;
>  }
>  
> +static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> +{
> +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +       if (intel_dp->psr.psr2_sel_fetch_enabled)
> +               intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp-
> >psr.transcoder),
> +                            0,
> ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> +
> +       intel_de_rmw(dev_priv,

Setting this bit in here is not correct. PSR2_MAN_TRK_CTL is supposed
to be written in intel_psr2_program_trans_man_trk_ctl. Anyways you are
saying in cover letter "enable full-screen live active frame update
mode". This bit is about selective update/selective fetch.

> TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> +                    TRANS_DP2_PANEL_REPLAY_ENABLE);
> +}
> +
>  static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  {
>         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1295,6 +1313,9 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>         crtc_state->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
>         intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> conn_state,
>                                      &crtc_state->psr_vsc);
> +
> +       drm_dbg_kms(&dev_priv->drm, "has_pr = %d, has_psr = %d,
> has_psr2 = %d, infoframes_enable = %d\n",
> +                   crtc_state->has_panel_replay, crtc_state-
> >has_psr, crtc_state->has_psr2, crtc_state->infoframes.enable);
>  }
>  
>  void intel_psr_get_config(struct intel_encoder *encoder,
> @@ -1310,18 +1331,23 @@ void intel_psr_get_config(struct
> intel_encoder *encoder,
>                 return;
>  
>         intel_dp = &dig_port->dp;
> -       if (!CAN_PSR(intel_dp))
> +       if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
>                 return;
>  
>         mutex_lock(&intel_dp->psr.lock);
>         if (!intel_dp->psr.enabled)
>                 goto unlock;
>  
> -       /*
> -        * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> -        * enabled/disabled because of frontbuffer tracking and
> others.
> -        */
> -       pipe_config->has_psr = true;
> +       if (intel_dp->psr.panel_replay_enabled) {
> +               pipe_config->has_panel_replay = true;
> +       } else {
> +               /*
> +                * Not possible to read EDP_PSR/PSR2_CTL registers as
> it is
> +                * enabled/disabled because of frontbuffer tracking
> and others.
> +                */
> +               pipe_config->has_psr = true;
> +       }
> +
>         pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
>         pipe_config->infoframes.enable |=
> intel_hdmi_infoframe_enable(DP_SDP_VSC);
>  
> @@ -1358,8 +1384,10 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
>  
>         lockdep_assert_held(&intel_dp->psr.lock);
>  
> -       /* psr1 and psr2 are mutually exclusive.*/
> -       if (intel_dp->psr.psr2_enabled)
> +       /* psr1, psr2 and panel-replay are mutually exclusive.*/
> +       if (intel_dp->psr.panel_replay_enabled)
> +               dg2_activate_panel_replay(intel_dp);
> +       else if (intel_dp->psr.psr2_enabled)
>                 hsw_activate_psr2(intel_dp);
>         else
>                 hsw_activate_psr1(intel_dp);
> @@ -1538,6 +1566,7 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
>         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
>  
>         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +       intel_dp->psr.panel_replay_enabled = crtc_state-
> >has_panel_replay;
>         intel_dp->psr.busy_frontbuffer_bits = 0;
>         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> >pipe;
>         intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> @@ -1553,8 +1582,12 @@ static void intel_psr_enable_locked(struct
> intel_dp *intel_dp,
>         if (!psr_interrupt_error_check(intel_dp))
>                 return;
>  
> -       drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> -                   intel_dp->psr.psr2_enabled ? "2" : "1");
> +       if (intel_dp->psr.panel_replay_enabled)
> +               drm_dbg_kms(&dev_priv->drm, "Enabling Panel
> Replay\n");
> +       else
> +               drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> +                           intel_dp->psr.psr2_enabled ? "2" : "1");
> +
>         intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state-
> >psr_vsc);
>         intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
>         intel_psr_enable_sink(intel_dp);
> @@ -1583,7 +1616,10 @@ static void intel_psr_exit(struct intel_dp
> *intel_dp)
>                 return;
>         }
>  
> -       if (intel_dp->psr.psr2_enabled) {
> +       if (intel_dp->psr.panel_replay_enabled) {
> +               intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder),
> +                            TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> +       } else if (intel_dp->psr.psr2_enabled) {
>                 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
>  
>                 val = intel_de_rmw(dev_priv,
> EDP_PSR2_CTL(cpu_transcoder),
> @@ -1632,8 +1668,11 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
>         if (!intel_dp->psr.enabled)
>                 return;
>  
> -       drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> -                   intel_dp->psr.psr2_enabled ? "2" : "1");
> +       if (intel_dp->psr.panel_replay_enabled)
> +               drm_dbg_kms(&dev_priv->drm, "Disabling Panel
> Replay\n");
> +       else
> +               drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> +                           intel_dp->psr.psr2_enabled ? "2" : "1");
>  
>         intel_psr_exit(intel_dp);
>         intel_psr_wait_exit_locked(intel_dp);
> @@ -1666,6 +1705,7 @@ static void intel_psr_disable_locked(struct
> intel_dp *intel_dp)
>                 drm_dp_dpcd_writeb(&intel_dp->aux,
> DP_RECEIVER_ALPM_CONFIG, 0);
>  
>         intel_dp->psr.enabled = false;
> +       intel_dp->psr.panel_replay_enabled = false;
>         intel_dp->psr.psr2_enabled = false;
>         intel_dp->psr.psr2_sel_fetch_enabled = false;
>         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
> @@ -2235,7 +2275,7 @@ static void _intel_psr_post_plane_update(const
> struct intel_atomic_state *state,
>         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>         struct intel_encoder *encoder;
>  
> -       if (!crtc_state->has_psr)
> +       if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
>                 return;
>  
>         for_each_intel_encoder_mask_with_psr(state->base.dev,
> encoder,
> @@ -2276,7 +2316,7 @@ void intel_psr_post_plane_update(const struct
> intel_atomic_state *state)
>         struct intel_crtc *crtc;
>         int i;
>  
> -       if (!HAS_PSR(dev_priv))
> +       if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
>                 return;
>  
>         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)

Re: [Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Jani Nikula]

On Thu, 24 Aug 2023, Animesh Manna <animesh.manna@intel.com> wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  include/drm/display/drm_dp.h | 11 +++++++++++

If it touches drm, need to Cc: dri-devel. This is not new.

BR,
Jani.

>  1 file changed, 11 insertions(+)
>
> diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
> index e69cece404b3..a38dc5f1731e 100644
> --- a/include/drm/display/drm_dp.h
> +++ b/include/drm/display/drm_dp.h
> @@ -543,6 +543,10 @@
>  /* DFP Capability Extension */
>  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
>  
> +#define DP_PANEL_REPLAY_CAP                 0x0b0
> +# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
> +# define DP_PANEL_REPLAY_SU_SUPPORT         (1 << 1)
> +
>  /* Link Configuration */
>  #define	DP_LINK_BW_SET		            0x100
>  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> @@ -716,6 +720,13 @@
>  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG                             0x1b0
> +# define DP_PANEL_REPLAY_ENABLE                         (1 << 0)
> +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR            (1 << 3)
> +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR              (1 << 4)
> +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR         (1 << 5)
> +# define DP_PANEL_REPLAY_SU_ENABLE                      (1 << 6)
> +
>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Jani Nikula]

On Thu, 24 Aug 2023, Animesh Manna <animesh.manna@intel.com> wrote:
> Modify existing PSR implementation to enable panel replay feature of DP 2.0
> which is similar to PSR feature of EDP panel. There is different DPCD
> address to check panel capability compare to PSR and vsc sdp header
> is different.
>
> v1: Initial version.
> v2:
> - Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check. [Jouni]
> - Code restructured around intel_panel_replay_init
> and renamed to intel_panel_replay_init_dpcd. [Jouni]
> - Remove the initial code modification around has_psr2 flag. [Jouni]
> - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
> enable in intel_psr_post_plane_update. [Jouni]
> v3:
> - Initialize both psr and panel-replay. [Jouni]
> - Initialize both panel replay and psr if detected. [Jouni]
> - Refactoring psr function by introducing _psr_compute_config(). [Jouni]
> - Add check for !is_edp while deriving source_panel_replay_support. [Jouni]
> - Enable panel replay dpcd initialization in a separate patch. [Jouni]
>
> v4:
> - HAS_PANEL_REPLAY() check not needed during sink capability check.[Jouni]
> - Set either panel replay source support or psr.[Jouni]
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    | 12 ++-
>  drivers/gpu/drm/i915/display/intel_dp.c       | 44 ++++++++--
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  3 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 87 +++++++++++++------
>  4 files changed, 107 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 731f2ec04d5c..97cef458f42b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1202,6 +1202,7 @@ struct intel_crtc_state {
>  	bool has_psr2;
>  	bool enable_psr2_sel_fetch;
>  	bool req_psr2_sdp_prior_scanline;
> +	bool has_panel_replay;
>  	bool wm_level_disabled;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
> @@ -1693,6 +1694,8 @@ struct intel_psr {
>  	bool irq_aux_error;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
> +	bool source_panel_replay_support;
> +	bool sink_panel_replay_support;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
>  	struct delayed_work dc3co_work;
> @@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
>  #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
>  			   (intel_dp)->psr.source_support)
>  
> +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \
> +			  (intel_dp)->psr.source_panel_replay_support)
> +
>  static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
>  {
> -	if (!intel_encoder_is_dp(encoder))
> +	if (intel_encoder_is_dp(encoder) || (encoder->type == INTEL_OUTPUT_DP_MST))
> +		return CAN_PSR(enc_to_intel_dp(encoder)) || CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
> +	else
>  		return false;
> -
> -	return CAN_PSR(enc_to_intel_dp(encoder));
>  }

The whole function and macros should live in intel_psr.c as proper
functions.

>  
>  static inline struct intel_digital_port *
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7067ee3a4bd3..b3301cf0da0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2337,12 +2337,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	/*
> -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -	 * Colorimetry Format indication.
> -	 */
> -	vsc->revision = 0x5;
> +	if (crtc_state->has_panel_replay) {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> +		 * Encoding/Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x7;
> +	} else {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +		 * Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x5;
> +	}
> +
>  	vsc->length = 0x13;
>  
>  	/* DP 1.4a spec, Table 2-120 */
> @@ -2451,6 +2461,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
>  			vsc->revision = 0x4;
>  			vsc->length = 0xe;
>  		}
> +	} else if (crtc_state->has_panel_replay) {
> +		if (intel_dp->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [Panel Replay with colorimetry info] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [Panel Replay without colorimetry info]
> +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +			 * VSC SDP supporting 3D stereo + Panel Replay.
> +			 */
> +			vsc->revision = 0x6;
> +			vsc->length = 0x10;
> +		}
>  	} else {
>  		/*
>  		 * [PSR1]
> @@ -3744,10 +3769,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
>  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>  
>  	/*
> -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> -	 * per DP 1.4a spec.
> +	 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
> +	 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
> +	 * Encoding/Colorimetry Format as per DP 2.0 spec.
>  	 */
> -	if (vsc->revision != 0x5)
> +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
>  		goto out;
>  
>  	/* VSC SDP Payload for DB16 through DB18 */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3eb085fbc7c8..07a3ab473be2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -44,6 +44,7 @@
>  #include "intel_hdcp.h"
>  #include "intel_hotplug.h"
>  #include "skl_scaler.h"
> +#include "intel_psr.h"

Please keep these sorted.

>  
>  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
>  					  const struct drm_display_mode *adjusted_mode,
> @@ -398,6 +399,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>  
>  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
>  
> +	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index b1c0494826f9..8dd61c62492d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -472,6 +472,24 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
>  	intel_dp->psr.su_y_granularity = y;
>  }
>  
> +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u8 pr_dpcd = 0;
> +
> +	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
> +
> +	if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "Panel replay is not supported by panel\n");
> +		return;
> +	}
> +
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "Panel replay is supported by panel\n");
> +	intel_dp->psr.sink_panel_replay_support = true;

This is not eDP so clearing the cached value matters. I don't see this
cleared anywhere.

> +}
> +
>  static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *i915 =
> @@ -521,12 +539,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  
>  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  {
> +	_panel_replay_init_dpcd(intel_dp);
> +
>  	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
>  			 sizeof(intel_dp->psr_dpcd));
>  
>  	if (intel_dp->psr_dpcd[0])
>  		_psr_init_dpcd(intel_dp);
> -	/* TODO: Add PR case here */
>  
>  	if (intel_dp->psr.sink_psr2_support) {
>  		intel_dp->psr.colorimetry_support =
> @@ -1207,13 +1226,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	return false;
>  }
>  
> -void intel_psr_compute_config(struct intel_dp *intel_dp,
> -			      struct intel_crtc_state *crtc_state,
> -			      struct drm_connector_state *conn_state)
> +static bool _psr_compute_config(struct intel_dp *intel_dp,
> +				struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	const struct drm_display_mode *adjusted_mode =
> -		&crtc_state->hw.adjusted_mode;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	int psr_setup_time;
>  
>  	/*
> @@ -1221,10 +1238,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	 * So if VRR is enabled, do not enable PSR.
>  	 */
>  	if (crtc_state->vrr.enable)
> -		return;
> +		return false;
>  
>  	if (!CAN_PSR(intel_dp))
> -		return;
> +		return false;
> +
> +	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> +	if (psr_setup_time < 0) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> +			    intel_dp->psr_dpcd[1]);
> +		return false;
> +	}
> +
> +	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> +	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PSR condition failed: PSR setup time (%d us) too long\n",
> +			    psr_setup_time);
> +		return false;
> +	}
> +
> +	return true;
> +}
> +
> +void intel_psr_compute_config(struct intel_dp *intel_dp,
> +			      struct intel_crtc_state *crtc_state,
> +			      struct drm_connector_state *conn_state)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  
>  	if (!psr_global_enabled(intel_dp)) {
>  		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
> @@ -1234,7 +1277,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	if (intel_dp->psr.sink_not_reliable) {
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR sink implementation is not reliable\n");
> -		return;
>  	}
>  
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1243,23 +1285,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> -	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> -	if (psr_setup_time < 0) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
> -			    intel_dp->psr_dpcd[1]);
> -		return;
> -	}
> -
> -	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> -	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "PSR condition failed: PSR setup time (%d us) too long\n",
> -			    psr_setup_time);
> -		return;
> -	}
> +	if (CAN_PANEL_REPLAY(intel_dp))
> +		crtc_state->has_panel_replay = true;
> +	else
> +		crtc_state->has_psr = _psr_compute_config(intel_dp, crtc_state);
>  
> -	crtc_state->has_psr = true;
>  	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
>  
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> @@ -2699,7 +2729,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	if (!HAS_PSR(dev_priv))
> +	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
>  		return;
>  
>  	/*
> @@ -2717,7 +2747,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  		return;
>  	}
>  
> -	intel_dp->psr.source_support = true;
> +	if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
> +		intel_dp->psr.source_panel_replay_support = true;
> +	else
> +		intel_dp->psr.source_support = true;
>  
>  	/* Set link_standby x link_off defaults */
>  	if (DISPLAY_VER(dev_priv) < 12)

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.IGT: failure for Panel replay phase1 implementation (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 53171 bytes --]

== Series Details ==

Series: Panel replay phase1 implementation (rev6)
URL   : https://patchwork.freedesktop.org/series/94470/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13558_full -> Patchwork_94470v6_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_94470v6_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_94470v6_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_94470v6_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_rc_ccs:
    - shard-mtlp:         [PASS][1] -> [TIMEOUT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-5/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_rc_ccs.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-1/igt@kms_ccs@pipe-d-bad-rotation-90-4_tiled_mtl_rc_ccs.html

  
Known issues
------------

  Here are the changes found in Patchwork_94470v6_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - shard-rkl:          [PASS][3] -> [FAIL][4] ([i915#7742])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-4/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@drm_fdinfo@virtual-busy-idle:
    - shard-dg1:          NOTRUN -> [SKIP][5] ([i915#8414])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@drm_fdinfo@virtual-busy-idle.html

  * igt@drm_fdinfo@virtual-busy-idle-all:
    - shard-dg2:          NOTRUN -> [SKIP][6] ([i915#8414])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@drm_fdinfo@virtual-busy-idle-all.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [PASS][7] -> [FAIL][8] ([i915#6268])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-tglu-4/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg1:          NOTRUN -> [SKIP][9] ([i915#8555])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_ctx_persistence@legacy-engines-hang:
    - shard-snb:          NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#1099])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-snb2/igt@gem_ctx_persistence@legacy-engines-hang.html

  * igt@gem_eio@in-flight-suspend:
    - shard-snb:          NOTRUN -> [DMESG-WARN][11] ([i915#8841]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-snb2/igt@gem_eio@in-flight-suspend.html
    - shard-dg2:          [PASS][12] -> [INCOMPLETE][13] ([i915#7892])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-3/igt@gem_eio@in-flight-suspend.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-11/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          NOTRUN -> [FAIL][14] ([i915#5784])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_eio@reset-stress.html

  * igt@gem_eio@unwedge-stress:
    - shard-dg1:          [PASS][15] -> [FAIL][16] ([i915#5784])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg1-16/igt@gem_eio@unwedge-stress.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-16/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@bonded-true-hang:
    - shard-dg2:          NOTRUN -> [SKIP][17] ([i915#4812]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_exec_balancer@bonded-true-hang.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg1:          NOTRUN -> [SKIP][18] ([i915#4812])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_capture@capture@bcs0-smem:
    - shard-mtlp:         [PASS][19] -> [TIMEOUT][20] ([i915#7941])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-5/igt@gem_exec_capture@capture@bcs0-smem.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-1/igt@gem_exec_capture@capture@bcs0-smem.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [PASS][21] -> [FAIL][22] ([i915#2842])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][23] ([i915#2842])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_flush@basic-wb-rw-before-default:
    - shard-dg1:          NOTRUN -> [SKIP][24] ([i915#3539] / [i915#4852]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_exec_flush@basic-wb-rw-before-default.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-dg1:          NOTRUN -> [SKIP][25] ([i915#3281]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_reloc@basic-write-wc-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#3281]) +3 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_exec_reloc@basic-write-wc-noreloc.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg2:          NOTRUN -> [ABORT][27] ([i915#7975] / [i915#8213])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_fence_thrash@bo-write-verify-x:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4860])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_fence_thrash@bo-write-verify-x.html

  * igt@gem_lmem_swapping@massive:
    - shard-glk:          NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#4613])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@gem_lmem_swapping@massive.html

  * igt@gem_mmap_gtt@basic-read-write-distinct:
    - shard-dg1:          NOTRUN -> [SKIP][30] ([i915#4077]) +3 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_mmap_gtt@basic-read-write-distinct.html

  * igt@gem_mmap_gtt@cpuset-medium-copy-xy:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#4077]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html

  * igt@gem_mmap_offset@clear@smem0:
    - shard-dg1:          [PASS][32] -> [FAIL][33] ([i915#7962])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg1-18/igt@gem_mmap_offset@clear@smem0.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-14/igt@gem_mmap_offset@clear@smem0.html

  * igt@gem_mmap_wc@read-write-distinct:
    - shard-dg1:          NOTRUN -> [SKIP][34] ([i915#4083]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_mmap_wc@read-write-distinct.html

  * igt@gem_mmap_wc@set-cache-level:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4083]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_mmap_wc@set-cache-level.html

  * igt@gem_partial_pwrite_pread@write:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#3282])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_partial_pwrite_pread@write.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#4270])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#4270])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_pxp@reject-modify-context-protection-off-2.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#3297])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#3323])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-dg1:          NOTRUN -> [SKIP][41] ([i915#3297])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([fdo#109289]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gen7_exec_parse@chained-batch.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-dg1:          NOTRUN -> [SKIP][43] ([i915#2527])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gen9_exec_parse@secure-batches.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#2856])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
    - shard-rkl:          [PASS][45] -> [SKIP][46] ([i915#1937])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html

  * igt@i915_pm_rc6_residency@rc6-idle@rcs0:
    - shard-dg1:          [PASS][47] -> [FAIL][48] ([i915#3591]) +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html

  * igt@i915_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#1397])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          [PASS][50] -> [SKIP][51] ([i915#1397])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [PASS][52] -> [SKIP][53] ([i915#1397])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [PASS][54] -> [INCOMPLETE][55] ([i915#7790])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-snb6/igt@i915_pm_rps@reset.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-snb1/igt@i915_pm_rps@reset.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#4387])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@i915_pm_sseu@full-enable.html

  * igt@i915_selftest@live@gt_pm:
    - shard-rkl:          [PASS][57] -> [DMESG-FAIL][58] ([i915#4258])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-1/igt@i915_selftest@live@gt_pm.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-4/igt@i915_selftest@live@gt_pm.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg2:          NOTRUN -> [SKIP][59] ([i915#4212])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_async_flips@crc@pipe-d-dp-4:
    - shard-dg2:          NOTRUN -> [FAIL][60] ([i915#8247]) +3 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#404])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][62] -> [FAIL][63] ([i915#5138])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#4538] / [i915#5286]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([fdo#111614])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][66] ([fdo#111615])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#5190]) +4 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][68] ([fdo#111615])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4538] / [i915#5190]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#3689] / [i915#5354]) +5 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#3689] / [i915#3886] / [i915#5354]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886]) +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl6/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs:
    - shard-dg1:          NOTRUN -> [SKIP][74] ([i915#3689] / [i915#5354] / [i915#6095]) +3 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][76] ([i915#6095]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc:
    - shard-dg1:          NOTRUN -> [SKIP][77] ([i915#5354] / [i915#6095]) +3 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_ccs@pipe-b-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][78] ([i915#3886] / [i915#6095])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium_color@ctm-0-25:
    - shard-dg1:          NOTRUN -> [SKIP][79] ([fdo#111827])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_chamelium_color@ctm-0-25.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([fdo#111827])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#7828]) +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][82] ([i915#7828])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#7828])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][84] ([i915#7173])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#3299])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-glk:          NOTRUN -> [SKIP][86] ([fdo#109271]) +56 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          [PASS][87] -> [FAIL][88] ([i915#2346])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#4103] / [i915#4213])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#3804])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#3555]) +2 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-snb:          NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111767])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-snb6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][93] ([i915#8381])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([fdo#109274])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
    - shard-glk:          [PASS][95] -> [FAIL][96] ([i915#79])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3:
    - shard-dg2:          [PASS][97] -> [FAIL][98] ([fdo#103375]) +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-8/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-5/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#2672])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][100] ([i915#2587] / [i915#2672]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#8708]) +2 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#3458]) +3 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite:
    - shard-apl:          NOTRUN -> [SKIP][103] ([fdo#109271]) +40 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][104] ([i915#5354]) +14 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][105] ([fdo#111825]) +6 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][106] ([i915#3458]) +3 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][107] ([i915#5460])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#8708]) +2 similar issues
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
    - shard-mtlp:         NOTRUN -> [SKIP][109] ([i915#1825])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#3555] / [i915#8228])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-1/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#3555] / [i915#8228])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_plane@pixel-format@pipe-b-planes:
    - shard-mtlp:         [PASS][112] -> [FAIL][113] ([i915#1623])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-3/igt@kms_plane@pixel-format@pipe-b-planes.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-6/igt@kms_plane@pixel-format@pipe-b-planes.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#6953])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-6/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][115] ([i915#8292])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][116] ([i915#8292])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-15/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#5176]) +3 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-8/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][118] ([i915#5176]) +15 similar issues
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-15/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#5235]) +11 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-17/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-4.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#5235]) +5 similar issues
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [SKIP][121] ([i915#5235]) +11 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-11/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-dp-4.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#6524] / [i915#6805])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
    - shard-apl:          NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#658])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#658])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr@primary_page_flip:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#1072])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@psr2_cursor_mmap_gtt:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#1072]) +2 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_psr@psr2_cursor_mmap_gtt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#5461] / [i915#658])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2:          NOTRUN -> [SKIP][128] ([i915#4235])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_selftest@drm_format_helper:
    - shard-glk:          NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#8661])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@kms_selftest@drm_format_helper.html

  * igt@kms_selftest@framebuffer:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#8661])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@kms_selftest@framebuffer.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-snb:          NOTRUN -> [SKIP][131] ([fdo#109271]) +115 similar issues
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-snb2/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_writeback@writeback-check-output:
    - shard-glk:          NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#2437])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@kms_writeback@writeback-check-output.html

  * igt@perf@non-zero-reason@0-rcs0:
    - shard-dg2:          [PASS][133] -> [FAIL][134] ([i915#7484])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-12/igt@perf@non-zero-reason@0-rcs0.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-12/igt@perf@non-zero-reason@0-rcs0.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-dg1:          NOTRUN -> [SKIP][135] ([fdo#109289] / [i915#2433])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@perf@unprivileged-single-ctx-counters.html

  * igt@prime_vgem@basic-fence-read:
    - shard-glk:          [PASS][136] -> [INCOMPLETE][137] ([i915#2295])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-glk5/igt@prime_vgem@basic-fence-read.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk3/igt@prime_vgem@basic-fence-read.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#3291] / [i915#3708])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@fence-read-hang:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#3708])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@prime_vgem@fence-read-hang.html

  * igt@v3d/v3d_submit_cl@bad-pad:
    - shard-dg2:          NOTRUN -> [SKIP][140] ([i915#2575]) +2 similar issues
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@v3d/v3d_submit_cl@bad-pad.html

  * igt@v3d/v3d_submit_csd@valid-multisync-submission:
    - shard-dg1:          NOTRUN -> [SKIP][141] ([i915#2575]) +2 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@v3d/v3d_submit_csd@valid-multisync-submission.html

  * igt@vc4/vc4_lookup_fail@bad-color-write:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#7711])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-3/igt@vc4/vc4_lookup_fail@bad-color-write.html

  * igt@vc4/vc4_perfmon@create-two-perfmon:
    - shard-mtlp:         NOTRUN -> [SKIP][143] ([i915#7711])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@vc4/vc4_perfmon@create-two-perfmon.html

  * igt@vc4/vc4_tiling@set-get:
    - shard-dg1:          NOTRUN -> [SKIP][144] ([i915#7711]) +1 similar issue
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@vc4/vc4_tiling@set-get.html

  
#### Possible fixes ####

  * igt@gem_exec_capture@pi@bcs0:
    - shard-mtlp:         [FAIL][145] ([i915#4475] / [i915#7765]) -> [PASS][146]
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-4/igt@gem_exec_capture@pi@bcs0.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-2/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-rkl:          [FAIL][147] ([i915#2842]) -> [PASS][148]
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_suspend@basic-s4-devices@lmem0:
    - shard-dg1:          [ABORT][149] ([i915#7975] / [i915#8213]) -> [PASS][150]
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg1-14/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@gem_exec_suspend@basic-s4-devices@lmem0.html

  * igt@gem_spin_batch@legacy@render:
    - shard-apl:          [FAIL][151] ([i915#2898]) -> [PASS][152]
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-apl2/igt@gem_spin_batch@legacy@render.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl2/igt@gem_spin_batch@legacy@render.html

  * igt@gem_spin_batch@spin-each:
    - shard-mtlp:         [DMESG-FAIL][153] ([i915#8962] / [i915#9121]) -> [PASS][154]
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-4/igt@gem_spin_batch@spin-each.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-2/igt@gem_spin_batch@spin-each.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [DMESG-WARN][155] ([i915#7061] / [i915#8617]) -> [PASS][156]
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-12/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-dg1:          [FAIL][157] ([i915#3591]) -> [PASS][158]
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [SKIP][159] ([i915#1397]) -> [PASS][160] +1 similar issue
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-6/igt@i915_pm_rpm@dpms-non-lpsp.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-dg2:          [FAIL][161] ([fdo#103375]) -> [PASS][162]
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-11/igt@i915_pm_rpm@system-suspend-execbuf.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-6/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-mtlp:         [FAIL][163] ([i915#2521]) -> [PASS][164]
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-mtlp:         [DMESG-WARN][165] ([i915#1982]) -> [PASS][166]
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-mtlp:         [FAIL][167] ([i915#3743]) -> [PASS][168] +1 similar issue
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [FAIL][169] ([i915#2346]) -> [PASS][170]
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
    - shard-apl:          [FAIL][171] ([i915#2346]) -> [PASS][172]
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@single-bo@all-pipes:
    - shard-mtlp:         [DMESG-WARN][173] ([i915#2017]) -> [PASS][174]
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-4/igt@kms_cursor_legacy@single-bo@all-pipes.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-2/igt@kms_cursor_legacy@single-bo@all-pipes.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][175] ([i915#2122]) -> [PASS][176]
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-glk5/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1:
    - shard-apl:          [ABORT][177] ([i915#180]) -> [PASS][178]
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-dp-1.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
    - shard-mtlp:         [FAIL][179] ([i915#1623]) -> [PASS][180]
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-7/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-7/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html

  
#### Warnings ####

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          [DMESG-WARN][181] ([i915#4936] / [i915#5493]) -> [TIMEOUT][182] ([i915#5493])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-8/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - shard-tglu:         [FAIL][183] ([i915#2681] / [i915#3591]) -> [WARN][184] ([i915#2681])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@kms_content_protection@content_type_change:
    - shard-dg2:          [SKIP][185] ([i915#7118] / [i915#7162]) -> [SKIP][186] ([i915#7118])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg2-11/igt@kms_content_protection@content_type_change.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg2-2/igt@kms_content_protection@content_type_change.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-rkl:          [SKIP][187] ([fdo#109285] / [i915#4098]) -> [SKIP][188] ([fdo#109285])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-1/igt@kms_force_connector_basic@force-load-detect.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][189] ([i915#4070] / [i915#4816]) -> [SKIP][190] ([i915#4816])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@sprite_plane_onoff:
    - shard-dg1:          [SKIP][191] ([i915#1072] / [i915#4078]) -> [SKIP][192] ([i915#1072]) +1 similar issue
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-dg1-13/igt@kms_psr@sprite_plane_onoff.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-dg1-15/igt@kms_psr@sprite_plane_onoff.html

  * igt@syncobj_timeline@invalid-wait-illegal-handle:
    - shard-mtlp:         [DMESG-WARN][193] ([i915#2017] / [i915#9157]) -> [DMESG-WARN][194] ([i915#9157])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13558/shard-mtlp-5/igt@syncobj_timeline@invalid-wait-illegal-handle.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/shard-mtlp-1/igt@syncobj_timeline@invalid-wait-illegal-handle.html

  
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
  [i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
  [i915#7962]: https://gitlab.freedesktop.org/drm/intel/issues/7962
  [i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
  [i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
  [i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
  [i915#9157]: https://gitlab.freedesktop.org/drm/intel/issues/9157


Build changes
-------------

  * Linux: CI_DRM_13558 -> Patchwork_94470v6

  CI-20190529: 20190529
  CI_DRM_13558: 2d5f57f6436263ecb456228603356d81173b1ceb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_94470v6: 2d5f57f6436263ecb456228603356d81173b1ceb @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_94470v6/index.html

[-- Attachment #2: Type: text/html, Size: 62781 bytes --]

Re: [Intel-gfx] [PATCH v4 2/6] drm/i915/panelreplay: Added HAS_PANEL_REPLAY() macro

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, August 24, 2023 4:50 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH v4 2/6] drm/i915/panelreplay: Added
> HAS_PANEL_REPLAY() macro
> 
> On Thu, 2023-08-24 at 09:39 +0530, Animesh Manna wrote:
> > Platforms having Display 13 and above will support panel replay
> > feature of DP 2.0 monitor. Added a HAS_PANEL_REPLAY() macro to check
> > for panel replay capability.
> >
> > v1: Initial version.
> > v2: DISPLAY_VER() removed as HAS_DP20() is having platform check.
> > [Jouni]
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 8198401aa5be..ab615a3199da 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -61,6 +61,7 @@ struct drm_printer;
> >  #define HAS_MSO(i915)                  (DISPLAY_VER(i915) >= 12)
> >  #define HAS_OVERLAY(i915)              (DISPLAY_INFO(i915)-
> > >has_overlay)
> >  #define HAS_PSR(i915)                  (DISPLAY_INFO(i915)->has_psr)
> > +#define HAS_PANEL_REPLAY(dev_priv)     (HAS_DP20(dev_priv))
> 
> I think you can drop this macro and use HAD_DP20 directly.

Ok.

Regards,
Animesh

> 
> BR,
> 
> Jouni Högander
> 
> >  #define HAS_PSR_HW_TRACKING(i915)      (DISPLAY_INFO(i915)-
> > >has_psr_hw_tracking)
> >  #define HAS_PSR2_SEL_FETCH(i915)       (DISPLAY_VER(i915) >= 12)
> >  #define HAS_SAGV(i915)                 (DISPLAY_VER(i915) >= 9 &&
> > !IS_LP(i915))

Re: [Intel-gfx] [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Thursday, August 24, 2023 4:55 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Murthy, Arun R <arun.r.murthy@intel.com>
> Subject: Re: [PATCH v4 6/6] drm/i915/panelreplay: enable/disable panel
> replay
> 
> On Thu, 2023-08-24 at 09:39 +0530, Animesh Manna wrote:
> > TRANS_DP2_CTL register is programmed to enable panel replay from
> > source and sink is enabled through panel replay dpcd configuration
> > address.
> >
> > Bspec: 1407940617
> >
> > v1: Initial version.
> > v2:
> > - Use pr_* flags instead psr_* flags. [Jouni]
> > - Remove intel_dp_is_edp check as edp1.5 also has panel replay.
> > [Jouni]
> >
> > v3: cover letter updated and selective fetch condition check is added
> > before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
> >
> > Note: Initial plan is to enable panel replay in  full-screen live
> > active frame update mode. In a incremental approach panel replay will
> > be enabled in selctive update mode if there is any gap in curent
> > implementation.
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 72 ++++++++++++++---
> > --
> >  2 files changed, 57 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 97cef458f42b..46f2e8a42d1d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1696,6 +1696,7 @@ struct intel_psr {
> >         u16 su_y_granularity;
> >         bool source_panel_replay_support;
> >         bool sink_panel_replay_support;
> > +       bool panel_replay_enabled;
> >         u32 dc3co_exitline;
> >         u32 dc3co_exit_delay;
> >         struct delayed_work dc3co_work; diff --git
> > a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index c92acc7be4f1..ccb714f2c9e6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -596,8 +596,14 @@ static void intel_psr_enable_sink(struct intel_dp
> > *intel_dp)
> >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >         u8 dpcd_val = DP_PSR_ENABLE;
> >
> > -       /* Enable ALPM at sink for psr2 */
> > +       if (intel_dp->psr.panel_replay_enabled) {
> > +               drm_dp_dpcd_writeb(&intel_dp->aux,
> > PANEL_REPLAY_CONFIG,
> > +                                  DP_PANEL_REPLAY_ENABLE);
> > +               return;
> > +       }
> > +
> >         if (intel_dp->psr.psr2_enabled) {
> > +               /* Enable ALPM at sink for psr2 */
> >                 drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG,
> >                                    DP_ALPM_ENABLE |
> >
> > DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> > @@ -747,6 +753,18 @@ static int psr2_block_count(struct intel_dp
> > *intel_dp)
> >         return psr2_block_count_lines(intel_dp) / 4;
> >  }
> >
> > +static void dg2_activate_panel_replay(struct intel_dp *intel_dp) {
> > +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +
> > +       if (intel_dp->psr.psr2_sel_fetch_enabled)
> > +               intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp-
> > >psr.transcoder),
> > +                            0,
> > ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> > +
> > +       intel_de_rmw(dev_priv,
> 
> Setting this bit in here is not correct. PSR2_MAN_TRK_CTL is supposed to be
> written in intel_psr2_program_trans_man_trk_ctl. Anyways you are saying in
> cover letter "enable full-screen live active frame update mode". This bit is
> about selective update/selective fetch.

Agree, it is selective fetch related. We can drop for now.

Regards,
Animesh

> 
> > TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> > +                    TRANS_DP2_PANEL_REPLAY_ENABLE); }
> > +
> >  static void hsw_activate_psr2(struct intel_dp *intel_dp)
> >  {
> >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@
> > -1295,6 +1313,9 @@ void intel_psr_compute_config(struct intel_dp
> > *intel_dp,
> >         crtc_state->infoframes.enable |=
> > intel_hdmi_infoframe_enable(DP_SDP_VSC);
> >         intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> >                                      &crtc_state->psr_vsc);
> > +
> > +       drm_dbg_kms(&dev_priv->drm, "has_pr = %d, has_psr = %d,
> > has_psr2 = %d, infoframes_enable = %d\n",
> > +                   crtc_state->has_panel_replay, crtc_state-
> > >has_psr, crtc_state->has_psr2, crtc_state->infoframes.enable);
> >  }
> >
> >  void intel_psr_get_config(struct intel_encoder *encoder, @@ -1310,18
> > +1331,23 @@ void intel_psr_get_config(struct intel_encoder *encoder,
> >                 return;
> >
> >         intel_dp = &dig_port->dp;
> > -       if (!CAN_PSR(intel_dp))
> > +       if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp)))
> >                 return;
> >
> >         mutex_lock(&intel_dp->psr.lock);
> >         if (!intel_dp->psr.enabled)
> >                 goto unlock;
> >
> > -       /*
> > -        * Not possible to read EDP_PSR/PSR2_CTL registers as it is
> > -        * enabled/disabled because of frontbuffer tracking and
> > others.
> > -        */
> > -       pipe_config->has_psr = true;
> > +       if (intel_dp->psr.panel_replay_enabled) {
> > +               pipe_config->has_panel_replay = true;
> > +       } else {
> > +               /*
> > +                * Not possible to read EDP_PSR/PSR2_CTL registers as
> > it is
> > +                * enabled/disabled because of frontbuffer tracking
> > and others.
> > +                */
> > +               pipe_config->has_psr = true;
> > +       }
> > +
> >         pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> >         pipe_config->infoframes.enable |=
> > intel_hdmi_infoframe_enable(DP_SDP_VSC);
> >
> > @@ -1358,8 +1384,10 @@ static void intel_psr_activate(struct intel_dp
> > *intel_dp)
> >
> >         lockdep_assert_held(&intel_dp->psr.lock);
> >
> > -       /* psr1 and psr2 are mutually exclusive.*/
> > -       if (intel_dp->psr.psr2_enabled)
> > +       /* psr1, psr2 and panel-replay are mutually exclusive.*/
> > +       if (intel_dp->psr.panel_replay_enabled)
> > +               dg2_activate_panel_replay(intel_dp);
> > +       else if (intel_dp->psr.psr2_enabled)
> >                 hsw_activate_psr2(intel_dp);
> >         else
> >                 hsw_activate_psr1(intel_dp); @@ -1538,6 +1566,7 @@
> > static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> >         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> >
> >         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > +       intel_dp->psr.panel_replay_enabled = crtc_state-
> > >has_panel_replay;
> >         intel_dp->psr.busy_frontbuffer_bits = 0;
> >         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> >         intel_dp->psr.transcoder = crtc_state->cpu_transcoder; @@
> > -1553,8 +1582,12 @@ static void intel_psr_enable_locked(struct
> > intel_dp *intel_dp,
> >         if (!psr_interrupt_error_check(intel_dp))
> >                 return;
> >
> > -       drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > -                   intel_dp->psr.psr2_enabled ? "2" : "1");
> > +       if (intel_dp->psr.panel_replay_enabled)
> > +               drm_dbg_kms(&dev_priv->drm, "Enabling Panel
> > Replay\n");
> > +       else
> > +               drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > +                           intel_dp->psr.psr2_enabled ? "2" : "1");
> > +
> >         intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state-
> > >psr_vsc);
> >         intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
> >         intel_psr_enable_sink(intel_dp); @@ -1583,7 +1616,10 @@ static
> > void intel_psr_exit(struct intel_dp
> > *intel_dp)
> >                 return;
> >         }
> >
> > -       if (intel_dp->psr.psr2_enabled) {
> > +       if (intel_dp->psr.panel_replay_enabled) {
> > +               intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp-
> > >psr.transcoder),
> > +                            TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> > +       } else if (intel_dp->psr.psr2_enabled) {
> >                 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> >
> >                 val = intel_de_rmw(dev_priv,
> > EDP_PSR2_CTL(cpu_transcoder), @@ -1632,8 +1668,11 @@ static void
> > intel_psr_disable_locked(struct intel_dp *intel_dp)
> >         if (!intel_dp->psr.enabled)
> >                 return;
> >
> > -       drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> > -                   intel_dp->psr.psr2_enabled ? "2" : "1");
> > +       if (intel_dp->psr.panel_replay_enabled)
> > +               drm_dbg_kms(&dev_priv->drm, "Disabling Panel
> > Replay\n");
> > +       else
> > +               drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
> > +                           intel_dp->psr.psr2_enabled ? "2" : "1");
> >
> >         intel_psr_exit(intel_dp);
> >         intel_psr_wait_exit_locked(intel_dp);
> > @@ -1666,6 +1705,7 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> >                 drm_dp_dpcd_writeb(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CONFIG, 0);
> >
> >         intel_dp->psr.enabled = false;
> > +       intel_dp->psr.panel_replay_enabled = false;
> >         intel_dp->psr.psr2_enabled = false;
> >         intel_dp->psr.psr2_sel_fetch_enabled = false;
> >         intel_dp->psr.psr2_sel_fetch_cff_enabled = false; @@ -2235,7
> > +2275,7 @@ static void _intel_psr_post_plane_update(const
> > struct intel_atomic_state *state,
> >         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >         struct intel_encoder *encoder;
> >
> > -       if (!crtc_state->has_psr)
> > +       if (!(crtc_state->has_psr || crtc_state->has_panel_replay))
> >                 return;
> >
> >         for_each_intel_encoder_mask_with_psr(state->base.dev,
> > encoder,
> > @@ -2276,7 +2316,7 @@ void intel_psr_post_plane_update(const struct
> > intel_atomic_state *state)
> >         struct intel_crtc *crtc;
> >         int i;
> >
> > -       if (!HAS_PSR(dev_priv))
> > +       if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
> >                 return;
> >
> >         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)

Re: [Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register definition for panelreplay

[Manna, Animesh]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, August 24, 2023 4:59 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4 1/6] drm/panelreplay: dpcd register
> definition for panelreplay
> 
> On Thu, 24 Aug 2023, Animesh Manna <animesh.manna@intel.com> wrote:
> > DPCD register definition added to check and enable panel replay
> > capability of the sink.
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  include/drm/display/drm_dp.h | 11 +++++++++++
> 
> If it touches drm, need to Cc: dri-devel. This is not new.

My bad, missed somehow. Will add next time.

Regards,
Animesh
 
> 
> BR,
> Jani.
> 
> >  1 file changed, 11 insertions(+)
> >
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h index e69cece404b3..a38dc5f1731e
> 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -543,6 +543,10 @@
> >  /* DFP Capability Extension */
> >  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_CAP                 0x0b0
> > +# define DP_PANEL_REPLAY_SUPPORT            (1 << 0)
> > +# define DP_PANEL_REPLAY_SU_SUPPORT         (1 << 1)
> > +
> >  /* Link Configuration */
> >  #define	DP_LINK_BW_SET		            0x100
> >  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> > @@ -716,6 +720,13 @@
> >  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
> >  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
> >
> > +#define PANEL_REPLAY_CONFIG                             0x1b0
> > +# define DP_PANEL_REPLAY_ENABLE                         (1 << 0)
> > +# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR            (1 << 3)
> > +# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR              (1 << 4)
> > +# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR         (1 << 5)
> > +# define DP_PANEL_REPLAY_SU_ENABLE                      (1 << 6)
> > +
> >  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
> >  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1  #define
> > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[Manna, Animesh]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, August 24, 2023 5:05 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and
> compute config for panel replay
> 
> On Thu, 24 Aug 2023, Animesh Manna <animesh.manna@intel.com> wrote:
> > Modify existing PSR implementation to enable panel replay feature of
> > DP 2.0 which is similar to PSR feature of EDP panel. There is
> > different DPCD address to check panel capability compare to PSR and
> > vsc sdp header is different.
> >
> > v1: Initial version.
> > v2:
> > - Set source_panel_replay_support flag under HAS_PNEL_REPLAY() check.
> > [Jouni]
> > - Code restructured around intel_panel_replay_init and renamed to
> > intel_panel_replay_init_dpcd. [Jouni]
> > - Remove the initial code modification around has_psr2 flag. [Jouni]
> > - Add CAN_PANEL_REPLAY() in intel_encoder_can_psr which is used to
> > enable in intel_psr_post_plane_update. [Jouni]
> > v3:
> > - Initialize both psr and panel-replay. [Jouni]
> > - Initialize both panel replay and psr if detected. [Jouni]
> > - Refactoring psr function by introducing _psr_compute_config().
> > [Jouni]
> > - Add check for !is_edp while deriving source_panel_replay_support.
> > [Jouni]
> > - Enable panel replay dpcd initialization in a separate patch. [Jouni]
> >
> > v4:
> > - HAS_PANEL_REPLAY() check not needed during sink capability
> > check.[Jouni]
> > - Set either panel replay source support or psr.[Jouni]
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    | 12 ++-
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 44 ++++++++--
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c   |  3 +
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 87 +++++++++++++------
> >  4 files changed, 107 insertions(+), 39 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 731f2ec04d5c..97cef458f42b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1202,6 +1202,7 @@ struct intel_crtc_state {
> >  	bool has_psr2;
> >  	bool enable_psr2_sel_fetch;
> >  	bool req_psr2_sdp_prior_scanline;
> > +	bool has_panel_replay;
> >  	bool wm_level_disabled;
> >  	u32 dc3co_exitline;
> >  	u16 su_y_granularity;
> > @@ -1693,6 +1694,8 @@ struct intel_psr {
> >  	bool irq_aux_error;
> >  	u16 su_w_granularity;
> >  	u16 su_y_granularity;
> > +	bool source_panel_replay_support;
> > +	bool sink_panel_replay_support;
> >  	u32 dc3co_exitline;
> >  	u32 dc3co_exit_delay;
> >  	struct delayed_work dc3co_work;
> > @@ -1983,12 +1986,15 @@ dp_to_lspcon(struct intel_dp *intel_dp)
> > #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
> >  			   (intel_dp)->psr.source_support)
> >
> > +#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)-
> >psr.sink_panel_replay_support && \
> > +			  (intel_dp)->psr.source_panel_replay_support)
> > +
> >  static inline bool intel_encoder_can_psr(struct intel_encoder
> > *encoder)  {
> > -	if (!intel_encoder_is_dp(encoder))
> > +	if (intel_encoder_is_dp(encoder) || (encoder->type ==
> INTEL_OUTPUT_DP_MST))
> > +		return CAN_PSR(enc_to_intel_dp(encoder)) ||
> CAN_PANEL_REPLAY(enc_to_intel_dp(encoder));
> > +	else
> >  		return false;
> > -
> > -	return CAN_PSR(enc_to_intel_dp(encoder));
> >  }
> 
> The whole function and macros should live in intel_psr.c as proper functions.
> 
> >
> >  static inline struct intel_digital_port * diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 7067ee3a4bd3..b3301cf0da0a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2337,12 +2337,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > -	/*
> > -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -	 * Colorimetry Format indication.
> > -	 */
> > -	vsc->revision = 0x5;
> > +	if (crtc_state->has_panel_replay) {
> > +		/*
> > +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > +		 * Encoding/Colorimetry Format indication.
> > +		 */
> > +		vsc->revision = 0x7;
> > +	} else {
> > +		/*
> > +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +		 * Colorimetry Format indication.
> > +		 */
> > +		vsc->revision = 0x5;
> > +	}
> > +
> >  	vsc->length = 0x13;
> >
> >  	/* DP 1.4a spec, Table 2-120 */
> > @@ -2451,6 +2461,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> >  			vsc->revision = 0x4;
> >  			vsc->length = 0xe;
> >  		}
> > +	} else if (crtc_state->has_panel_replay) {
> > +		if (intel_dp->psr.colorimetry_support &&
> > +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > +			/* [Panel Replay with colorimetry info] */
> > +			intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > +							 vsc);
> > +		} else {
> > +			/*
> > +			 * [Panel Replay without colorimetry info]
> > +			 * Prepare VSC Header for SU as per DP 2.0 spec,
> Table 2-223
> > +			 * VSC SDP supporting 3D stereo + Panel Replay.
> > +			 */
> > +			vsc->revision = 0x6;
> > +			vsc->length = 0x10;
> > +		}
> >  	} else {
> >  		/*
> >  		 * [PSR1]
> > @@ -3744,10 +3769,11 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> struct drm_dp_vsc_sdp *vsc,
> >  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> >
> >  	/*
> > -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > -	 * per DP 1.4a spec.
> > +	 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
> > +	 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
> > +	 * Encoding/Colorimetry Format as per DP 2.0 spec.
> >  	 */
> > -	if (vsc->revision != 0x5)
> > +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
> >  		goto out;
> >
> >  	/* VSC SDP Payload for DB16 through DB18 */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 3eb085fbc7c8..07a3ab473be2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -44,6 +44,7 @@
> >  #include "intel_hdcp.h"
> >  #include "intel_hotplug.h"
> >  #include "skl_scaler.h"
> > +#include "intel_psr.h"
> 
> Please keep these sorted.

Sure.

> 
> >
> >  static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int
> bpp,
> >  					  const struct drm_display_mode
> *adjusted_mode, @@ -398,6 +399,8
> > @@ static int intel_dp_mst_compute_config(struct intel_encoder
> > *encoder,
> >
> >  	intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
> >
> > +	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> > +
> >  	return 0;
> >  }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index b1c0494826f9..8dd61c62492d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -472,6 +472,24 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
> >  	intel_dp->psr.su_y_granularity = y;
> >  }
> >
> > +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +	u8 pr_dpcd = 0;
> > +
> > +	drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> > +
> > +	if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) {
> > +		drm_dbg_kms(&dev_priv->drm,
> > +			    "Panel replay is not supported by panel\n");
> > +		return;
> > +	}
> > +
> > +	drm_dbg_kms(&dev_priv->drm,
> > +		    "Panel replay is supported by panel\n");
> > +	intel_dp->psr.sink_panel_replay_support = true;
> 
> This is not eDP so clearing the cached value matters. I don't see this cleared
> anywhere.

Sure, will reset the flag in encoder->detect(). Thanks for catching it.

Regards,
Animesh

> 
> > +}
> > +
> >  static void _psr_init_dpcd(struct intel_dp *intel_dp)  {
> >  	struct drm_i915_private *i915 =
> > @@ -521,12 +539,13 @@ static void _psr_init_dpcd(struct intel_dp
> > *intel_dp)
> >
> >  void intel_psr_init_dpcd(struct intel_dp *intel_dp)  {
> > +	_panel_replay_init_dpcd(intel_dp);
> > +
> >  	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
> >  			 sizeof(intel_dp->psr_dpcd));
> >
> >  	if (intel_dp->psr_dpcd[0])
> >  		_psr_init_dpcd(intel_dp);
> > -	/* TODO: Add PR case here */
> >
> >  	if (intel_dp->psr.sink_psr2_support) {
> >  		intel_dp->psr.colorimetry_support = @@ -1207,13 +1226,11
> @@ static
> > bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> >  	return false;
> >  }
> >
> > -void intel_psr_compute_config(struct intel_dp *intel_dp,
> > -			      struct intel_crtc_state *crtc_state,
> > -			      struct drm_connector_state *conn_state)
> > +static bool _psr_compute_config(struct intel_dp *intel_dp,
> > +				struct intel_crtc_state *crtc_state)
> >  {
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -	const struct drm_display_mode *adjusted_mode =
> > -		&crtc_state->hw.adjusted_mode;
> > +	const struct drm_display_mode *adjusted_mode =
> > +&crtc_state->hw.adjusted_mode;
> >  	int psr_setup_time;
> >
> >  	/*
> > @@ -1221,10 +1238,36 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> >  	 * So if VRR is enabled, do not enable PSR.
> >  	 */
> >  	if (crtc_state->vrr.enable)
> > -		return;
> > +		return false;
> >
> >  	if (!CAN_PSR(intel_dp))
> > -		return;
> > +		return false;
> > +
> > +	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> > +	if (psr_setup_time < 0) {
> > +		drm_dbg_kms(&dev_priv->drm,
> > +			    "PSR condition failed: Invalid PSR setup time
> (0x%02x)\n",
> > +			    intel_dp->psr_dpcd[1]);
> > +		return false;
> > +	}
> > +
> > +	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> > +	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> > +		drm_dbg_kms(&dev_priv->drm,
> > +			    "PSR condition failed: PSR setup time (%d us) too
> long\n",
> > +			    psr_setup_time);
> > +		return false;
> > +	}
> > +
> > +	return true;
> > +}
> > +
> > +void intel_psr_compute_config(struct intel_dp *intel_dp,
> > +			      struct intel_crtc_state *crtc_state,
> > +			      struct drm_connector_state *conn_state) {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +	const struct drm_display_mode *adjusted_mode =
> > +&crtc_state->hw.adjusted_mode;
> >
> >  	if (!psr_global_enabled(intel_dp)) {
> >  		drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
> @@ -1234,7
> > +1277,6 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  	if (intel_dp->psr.sink_not_reliable) {
> >  		drm_dbg_kms(&dev_priv->drm,
> >  			    "PSR sink implementation is not reliable\n");
> > -		return;
> >  	}
> >
> >  	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { @@ -
> 1243,23
> > +1285,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  		return;
> >  	}
> >
> > -	psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
> > -	if (psr_setup_time < 0) {
> > -		drm_dbg_kms(&dev_priv->drm,
> > -			    "PSR condition failed: Invalid PSR setup time
> (0x%02x)\n",
> > -			    intel_dp->psr_dpcd[1]);
> > -		return;
> > -	}
> > -
> > -	if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
> > -	    adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
> > -		drm_dbg_kms(&dev_priv->drm,
> > -			    "PSR condition failed: PSR setup time (%d us) too
> long\n",
> > -			    psr_setup_time);
> > -		return;
> > -	}
> > +	if (CAN_PANEL_REPLAY(intel_dp))
> > +		crtc_state->has_panel_replay = true;
> > +	else
> > +		crtc_state->has_psr = _psr_compute_config(intel_dp,
> crtc_state);
> >
> > -	crtc_state->has_psr = true;
> >  	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp,
> > crtc_state);
> >
> >  	crtc_state->infoframes.enable |=
> > intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > @@ -2699,7 +2729,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
> >  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > -	if (!HAS_PSR(dev_priv))
> > +	if (!(HAS_PSR(dev_priv) || HAS_PANEL_REPLAY(dev_priv)))
> >  		return;
> >
> >  	/*
> > @@ -2717,7 +2747,10 @@ void intel_psr_init(struct intel_dp *intel_dp)
> >  		return;
> >  	}
> >
> > -	intel_dp->psr.source_support = true;
> > +	if (HAS_PANEL_REPLAY(dev_priv) && !intel_dp_is_edp(intel_dp))
> > +		intel_dp->psr.source_panel_replay_support = true;
> > +	else
> > +		intel_dp->psr.source_support = true;
> >
> >  	/* Set link_standby x link_off defaults */
> >  	if (DISPLAY_VER(dev_priv) < 12)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay

[kernel test robot]

Hi Animesh,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-tip/drm-tip]

url:    https://github.com/intel-lab-lkp/linux/commits/Animesh-Manna/drm-panelreplay-dpcd-register-definition-for-panelreplay/20230824-122224
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
patch link:    https://lore.kernel.org/r/20230824040952.186407-5-animesh.manna%40intel.com
patch subject: [Intel-gfx] [PATCH v4 4/6] drm/i915/panelreplay: Initializaton and compute config for panel replay
config: x86_64-rhel-8.3-rust (https://download.01.org/0day-ci/archive/20230826/202308260901.MphIjr2l-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project.git 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce: (https://download.01.org/0day-ci/archive/20230826/202308260901.MphIjr2l-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202308260901.MphIjr2l-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_dp.c:3776:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
           if (vsc->revision != 0x5 || vsc->revision != 0x7)
               ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +3776 drivers/gpu/drm/i915/display/intel_dp.c

  3751	
  3752	static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
  3753					     struct dp_sdp *sdp, size_t size)
  3754	{
  3755		size_t length = sizeof(struct dp_sdp);
  3756	
  3757		if (size < length)
  3758			return -ENOSPC;
  3759	
  3760		memset(sdp, 0, size);
  3761	
  3762		/*
  3763		 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
  3764		 * VSC SDP Header Bytes
  3765		 */
  3766		sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
  3767		sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
  3768		sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
  3769		sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
  3770	
  3771		/*
  3772		 * Other than revision 0x5 which supports Pixel Encoding/Colorimetry
  3773		 * Format as per DP 1.4a spec, revision 0x7 also supports Pixel
  3774		 * Encoding/Colorimetry Format as per DP 2.0 spec.
  3775		 */
> 3776		if (vsc->revision != 0x5 || vsc->revision != 0x7)
  3777			goto out;
  3778	
  3779		/* VSC SDP Payload for DB16 through DB18 */
  3780		/* Pixel Encoding and Colorimetry Formats  */
  3781		sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
  3782		sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
  3783	
  3784		switch (vsc->bpc) {
  3785		case 6:
  3786			/* 6bpc: 0x0 */
  3787			break;
  3788		case 8:
  3789			sdp->db[17] = 0x1; /* DB17[3:0] */
  3790			break;
  3791		case 10:
  3792			sdp->db[17] = 0x2;
  3793			break;
  3794		case 12:
  3795			sdp->db[17] = 0x3;
  3796			break;
  3797		case 16:
  3798			sdp->db[17] = 0x4;
  3799			break;
  3800		default:
  3801			MISSING_CASE(vsc->bpc);
  3802			break;
  3803		}
  3804		/* Dynamic Range and Component Bit Depth */
  3805		if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
  3806			sdp->db[17] |= 0x80;  /* DB17[7] */
  3807	
  3808		/* Content Type */
  3809		sdp->db[18] = vsc->content_type & 0x7;
  3810	
  3811	out:
  3812		return length;
  3813	}
  3814	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki