From: "Mintz, Yuval" <Yuval.Mintz@cavium.com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Cc: "Kalderon, Michal" <Michal.Kalderon@cavium.com>
Subject: RE: [PATCH net-next 2/5] qed: Fix TM block ILT allocation
Date: Mon, 3 Apr 2017 13:58:19 +0000 [thread overview]
Message-ID: <BL2PR07MB23065BDE84DBA9DC5D2B8FBD8D080@BL2PR07MB2306.namprd07.prod.outlook.com> (raw)
In-Reply-To: <7b179126-2a66-8696-98f9-3f3dca7a6d9e@cogentembedded.com>
> > + /* Timers is a special case -> we don't count how many cids require
>
> S/is/are/. CIDs?
What's implicitly meant here is the 'Timer[s] HW block'.
I understand it creates an odd looking English sentence, though.
Assuming there'll be a V2 for this we'd revise the comment;
Otherwise we'd do it in some future cleanup patch.
next prev parent reply other threads:[~2017-04-03 13:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-03 9:21 [PATCH net-next 0/5] qed: QM & ILT changes Yuval Mintz
2017-04-03 9:21 ` [PATCH net-next 1/5] qed: Revise QM cofiguration Yuval Mintz
2017-04-03 9:21 ` [PATCH net-next 2/5] qed: Fix TM block ILT allocation Yuval Mintz
2017-04-03 11:46 ` Sergei Shtylyov
2017-04-03 13:58 ` Mintz, Yuval [this message]
2017-04-03 9:21 ` [PATCH net-next 3/5] qed: Correct TM ILT lines in presence of VFs Yuval Mintz
2017-04-03 9:21 ` [PATCH net-next 4/5] qed: RoCE doesn't need to use SRC Yuval Mintz
2017-04-03 9:21 ` [PATCH net-next 5/5] qed: Manage with less memory regions for RoCE Yuval Mintz
2017-04-04 2:16 ` [PATCH net-next 0/5] qed: QM & ILT changes David Miller
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