[U-Boot] [PATCH v2 2/5] x86: qemu: Add CMD_NET to qemu-x86_defconfig

[U-Boot] [PATCH v2 2/5] x86: qemu: Add CMD_NET to qemu-x86_defconfig

[Bin Meng]

The following error is observed on QEMU x86.

=> print ipaddr
ipaddr=192.168.178.66
=> ping 192.168.178.1
*** ERROR: `ipaddr' not set
ping failed; host 192.168.178.1 is not alive

The issue was introduced in commit fd30563. Adding CMD_NET to
defconfig resolves this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- New patch to fix the networking issue

 configs/qemu-x86_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 198ab97..4509d52 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,6 +1,7 @@
 CONFIG_X86=y
 CONFIG_VENDOR_EMULATION=y
 CONFIG_TARGET_QEMU_X86=y
+CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
 CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86"
-- 
1.8.2.1

[U-Boot] [PATCH v2 3/5] x86: qemu: Create separate i440fx and q35 device trees

[Bin Meng]

Although the two qemu-x86 targets (i440fx and q35) share a lot in
common, they still have something that cannot easily handled in one
single device tree). Split to create two dedicated device tree files
and make the i440fx be the default build target.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- Still use one board configuration file qemu-x86.h

 arch/x86/dts/Makefile                           |  3 ++-
 arch/x86/dts/qemu-x86_i440fx.dts                | 34 +++++++++++++++++++++++++
 arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} |  2 +-
 board/coreboot/coreboot/Kconfig                 |  2 +-
 configs/qemu-x86_defconfig                      |  3 +--
 doc/README.x86                                  | 10 +++++++-
 6 files changed, 48 insertions(+), 6 deletions(-)
 create mode 100644 arch/x86/dts/qemu-x86_i440fx.dts
 rename arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} (95%)

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index ca2eab3..f86514c 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -3,7 +3,8 @@ dtb-y += chromebook_link.dtb \
 	crownbay.dtb \
 	galileo.dtb \
 	minnowmax.dtb \
-	qemu-x86.dtb
+	qemu-x86_i440fx.dtb \
+	qemu-x86_q35.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
new file mode 100644
index 0000000..4cf843b
--- /dev/null
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+	model = "QEMU x86 (I440FX)";
+	compatible = "qemu,x86";
+
+	config {
+		silent_console = <0>;
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	pci {
+		compatible = "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
+			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+	};
+
+};
diff --git a/arch/x86/dts/qemu-x86.dts b/arch/x86/dts/qemu-x86_q35.dts
similarity index 95%
rename from arch/x86/dts/qemu-x86.dts
rename to arch/x86/dts/qemu-x86_q35.dts
index f1291b5..6c89283 100644
--- a/arch/x86/dts/qemu-x86.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -10,7 +10,7 @@
 /include/ "serial.dtsi"
 
 / {
-	model = "QEMU x86";
+	model = "QEMU x86 (Q35)";
 	compatible = "qemu,x86";
 
 	config {
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index 69e3437..3ff64f4 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -23,7 +23,7 @@ config SYS_CONFIG_NAME
 
 config DEFAULT_DEVICE_TREE
 	string "Board Device Tree Source (dts) file"
-	default "qemu-x86"
+	default "qemu-x86_i440fx"
 	help
 	  This option selects the board Device Tree Source (dts) file in
 	  arch/x86/dts/ directory to be used to build U-Boot for coreboot.
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 4509d52..0959a98 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -1,10 +1,9 @@
 CONFIG_X86=y
 CONFIG_VENDOR_EMULATION=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_TARGET_QEMU_X86=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_SEPARATE=y
-CONFIG_DEFAULT_DEVICE_TREE="qemu-x86"
 CONFIG_VIDEO_VESA=y
 CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
 CONFIG_FRAMEBUFFER_VESA_MODE_111=y
diff --git a/doc/README.x86 b/doc/README.x86
index 0726205..c19f4a0 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -40,7 +40,7 @@ configuration during the 'make menuconfig' process.
 x86 architecture  --->
 	...
 	(qemu-x86) Board configuration file
-	(qemu-x86) Board Device Tree Source (dts) file
+	(qemu-x86_i440fx) Board Device Tree Source (dts) file
 	(0x01920000) Board specific Cache-As-RAM (CAR) address
 	(0x4000) Board specific Cache-As-RAM (CAR) size
 
@@ -186,6 +186,14 @@ To build u-boot.rom for QEMU x86 targets, just simply run
 $ make qemu-x86_defconfig
 $ make all
 
+Note this default configuration will build a U-Boot for the QEMU x86 i440FX
+board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
+configuration during the 'make menuconfig' process like below:
+
+Device Tree Control  --->
+	...
+	(qemu-x86_q35) Default Device Tree for DT control
+
 Test with coreboot
 ------------------
 For testing U-Boot as the coreboot payload, there are things that need be paid
-- 
1.8.2.1

[U-Boot] [PATCH v2 4/5] x86: coreboot: Control I/O port 0xb2 writing via device tree

[Bin Meng]

Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v2:
- Use a config option in the device tree instead of deleting the codes

 arch/x86/cpu/coreboot/coreboot.c | 12 +++++++++---
 arch/x86/dts/qemu-x86_q35.dts    |  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c3dfd28..c4cac04 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <netdev.h>
 #include <asm/io.h>
 #include <asm/msr.h>
@@ -74,9 +75,14 @@ void board_final_cleanup(void)
 		mtrr_close(&state);
 	}
 
-	/* Issue SMI to Coreboot to lock down ME and registers */
-	printf("Finalizing Coreboot\n");
-	outb(0xcb, 0xb2);
+	if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
+		/*
+		 * Issue SMI to coreboot to lock down ME and registers
+		 * when allowed via device tree
+		 */
+		printf("Finalizing coreboot\n");
+		outb(0xcb, 0xb2);
+	}
 }
 
 int misc_init_r(void)
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 6c89283..02a483c 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -15,6 +15,7 @@
 
 	config {
 		silent_console = <0>;
+		u-boot,no-apm-finalize;
 	};
 
 	chosen {
-- 
1.8.2.1

[U-Boot] [PATCH v2 5/5] x86: qemu: Implement PIRQ routing

[Bin Meng]

Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/coreboot/coreboot.c |  5 +++++
 arch/x86/cpu/qemu/qemu.c         |  8 ++++++++
 arch/x86/dts/qemu-x86_i440fx.dts | 16 ++++++++++++++++
 arch/x86/dts/qemu-x86_q35.dts    | 32 ++++++++++++++++++++++++++++++++
 configs/qemu-x86_defconfig       |  1 +
 include/configs/qemu-x86.h       |  1 +
 6 files changed, 63 insertions(+)

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c4cac04..0e9f15f 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -89,3 +89,8 @@ int misc_init_r(void)
 {
 	return 0;
 }
+
+int arch_misc_init(void)
+{
+	return 0;
+}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 0f98476..930d2b6 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 
@@ -35,3 +36,10 @@ void reset_cpu(ulong addr)
 	/* cold reset */
 	x86_full_reset();
 }
+
+int arch_misc_init(void)
+{
+	pirq_init();
+
+	return 0;
+}
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 4cf843b..557428a 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -6,6 +6,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 
@@ -29,6 +31,20 @@
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		irq-router at 1,0 {
+			reg = <0x00000800 0 0 0 0>;
+			compatible = "intel,irq-router";
+			intel,pirq-config = "pci";
+			intel,pirq-link = <0x60 4>;
+			intel,pirq-mask = <0x0e40>;
+			intel,pirq-routing = <
+				/* PIIX UHCI */
+				PCI_BDF(0, 1, 2) INTD PIRQD
+				/* e1000 NIC */
+				PCI_BDF(0, 3, 0) INTA PIRQC
+			>;
+		};
 	};
 
 };
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 02a483c..c259f2a 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -6,6 +6,18 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/* ICH9 IRQ router has discrete PIRQ control registers */
+#undef PIRQE
+#undef PIRQF
+#undef PIRQG
+#undef PIRQH
+#define PIRQE	8
+#define PIRQF	9
+#define PIRQG	10
+#define PIRQH	11
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 
@@ -30,6 +42,26 @@
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		irq-router at 1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,irq-router";
+			intel,pirq-config = "pci";
+			intel,pirq-link = <0x60 8>;
+			intel,pirq-mask = <0x0e40>;
+			intel,pirq-routing = <
+				/* e1000 NIC */
+				PCI_BDF(0, 2, 0) INTA PIRQG
+				/* ICH9 UHCI */
+				PCI_BDF(0, 29, 0) INTA PIRQA
+				PCI_BDF(0, 29, 1) INTB PIRQB
+				PCI_BDF(0, 29, 2) INTC PIRQC
+				/* ICH9 EHCI */
+				PCI_BDF(0, 29, 7) INTD PIRQD
+				/* ICH9 SATA */
+				PCI_BDF(0, 31, 2) INTA PIRQA
+			>;
+		};
 	};
 
 };
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 0959a98..901cbd7 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -2,6 +2,7 @@ CONFIG_X86=y
 CONFIG_VENDOR_EMULATION=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_TARGET_QEMU_X86=y
+CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
 CONFIG_VIDEO_VESA=y
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index d01936b..78c296f 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -14,6 +14,7 @@
 #include <configs/x86-common.h>
 
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_X86_SERIAL
 
-- 
1.8.2.1

[U-Boot] [PATCH v2 2/5] x86: qemu: Add CMD_NET to qemu-x86_defconfig

[Simon Glass]

Hi Bin,

On 2 June 2015 at 19:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> The following error is observed on QEMU x86.
>
> => print ipaddr
> ipaddr=192.168.178.66
> => ping 192.168.178.1
> *** ERROR: `ipaddr' not set
> ping failed; host 192.168.178.1 is not alive
>
> The issue was introduced in commit fd30563. Adding CMD_NET to
> defconfig resolves this.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - New patch to fix the networking issue
>
>  configs/qemu-x86_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
> index 198ab97..4509d52 100644
> --- a/configs/qemu-x86_defconfig
> +++ b/configs/qemu-x86_defconfig
> @@ -1,6 +1,7 @@
>  CONFIG_X86=y
>  CONFIG_VENDOR_EMULATION=y
>  CONFIG_TARGET_QEMU_X86=y
> +CONFIG_CMD_NET=y
>  CONFIG_OF_CONTROL=y
>  CONFIG_OF_SEPARATE=y
>  CONFIG_DEFAULT_DEVICE_TREE="qemu-x86"
> --
> 1.8.2.1
>

I'll squash this into your commit that adds qemu support.

Regards,
Simon

[U-Boot] [PATCH v2 3/5] x86: qemu: Create separate i440fx and q35 device trees

[Simon Glass]

On 2 June 2015 at 19:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> Although the two qemu-x86 targets (i440fx and q35) share a lot in
> common, they still have something that cannot easily handled in one
> single device tree). Split to create two dedicated device tree files
> and make the i440fx be the default build target.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - Still use one board configuration file qemu-x86.h
>
>  arch/x86/dts/Makefile                           |  3 ++-
>  arch/x86/dts/qemu-x86_i440fx.dts                | 34 +++++++++++++++++++++++++
>  arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} |  2 +-
>  board/coreboot/coreboot/Kconfig                 |  2 +-
>  configs/qemu-x86_defconfig                      |  3 +--
>  doc/README.x86                                  | 10 +++++++-
>  6 files changed, 48 insertions(+), 6 deletions(-)
>  create mode 100644 arch/x86/dts/qemu-x86_i440fx.dts
>  rename arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} (95%)

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 4/5] x86: coreboot: Control I/O port 0xb2 writing via device tree

[Simon Glass]

On 2 June 2015 at 19:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
> U-Boot to hang on QEMU q35 target. We introduce a config option in the
> device tree "u-boot,no-apm-finalize" under /config node if we don't want
> to do that.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
> Changes in v2:
> - Use a config option in the device tree instead of deleting the codes
>
>  arch/x86/cpu/coreboot/coreboot.c | 12 +++++++++---
>  arch/x86/dts/qemu-x86_q35.dts    |  1 +
>  2 files changed, 10 insertions(+), 3 deletions(-)
>

Acked-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 3/5] x86: qemu: Create separate i440fx and q35 device trees

[Simon Glass]

On 4 June 2015 at 02:47, Simon Glass <sjg@chromium.org> wrote:
> On 2 June 2015 at 19:20, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Although the two qemu-x86 targets (i440fx and q35) share a lot in
>> common, they still have something that cannot easily handled in one
>> single device tree). Split to create two dedicated device tree files
>> and make the i440fx be the default build target.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> Changes in v2:
>> - Still use one board configuration file qemu-x86.h
>>
>>  arch/x86/dts/Makefile                           |  3 ++-
>>  arch/x86/dts/qemu-x86_i440fx.dts                | 34 +++++++++++++++++++++++++
>>  arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} |  2 +-
>>  board/coreboot/coreboot/Kconfig                 |  2 +-
>>  configs/qemu-x86_defconfig                      |  3 +--
>>  doc/README.x86                                  | 10 +++++++-
>>  6 files changed, 48 insertions(+), 6 deletions(-)
>>  create mode 100644 arch/x86/dts/qemu-x86_i440fx.dts
>>  rename arch/x86/dts/{qemu-x86.dts => qemu-x86_q35.dts} (95%)
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 4/5] x86: coreboot: Control I/O port 0xb2 writing via device tree

[Simon Glass]

On 4 June 2015 at 02:47, Simon Glass <sjg@chromium.org> wrote:
> On 2 June 2015 at 19:20, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
>> U-Boot to hang on QEMU q35 target. We introduce a config option in the
>> device tree "u-boot,no-apm-finalize" under /config node if we don't want
>> to do that.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>> Changes in v2:
>> - Use a config option in the device tree instead of deleting the codes
>>
>>  arch/x86/cpu/coreboot/coreboot.c | 12 +++++++++---
>>  arch/x86/dts/qemu-x86_q35.dts    |  1 +
>>  2 files changed, 10 insertions(+), 3 deletions(-)
>>
>
> Acked-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-x86, thanks!

[U-Boot] [PATCH v2 5/5] x86: qemu: Implement PIRQ routing

[Simon Glass]

On 2 June 2015 at 19:20, Bin Meng <bmeng.cn@gmail.com> wrote:
> Support QEMU PIRQ routing via device tree on both i440fx and q35
> platforms. With this commit, Linux booting on QEMU from U-Boot
> has working ATA/SATA, USB and ethernet.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
>  arch/x86/cpu/coreboot/coreboot.c |  5 +++++
>  arch/x86/cpu/qemu/qemu.c         |  8 ++++++++
>  arch/x86/dts/qemu-x86_i440fx.dts | 16 ++++++++++++++++
>  arch/x86/dts/qemu-x86_q35.dts    | 32 ++++++++++++++++++++++++++++++++
>  configs/qemu-x86_defconfig       |  1 +
>  include/configs/qemu-x86.h       |  1 +
>  6 files changed, 63 insertions(+)

Applied to u-boot-x86, thanks!