* [U-Boot] [PATCH v2 2/9] dm: cpu: Test against cpu_ops->get_info in cpu_get_info()
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 19:10 ` Simon Glass
2015-06-12 6:52 ` [U-Boot] [PATCH v2 3/9] x86: dm: Clean up cpu drivers Bin Meng
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2: None
drivers/cpu/cpu-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index aa0267c..d6be9d4 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -26,7 +26,7 @@ int cpu_get_info(struct udevice *dev, struct cpu_info *info)
{
struct cpu_ops *ops = cpu_get_ops(dev);
- if (!ops->get_desc)
+ if (!ops->get_info)
return -ENOSYS;
return ops->get_info(dev, info);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 2/9] dm: cpu: Test against cpu_ops->get_info in cpu_get_info()
2015-06-12 6:52 ` [U-Boot] [PATCH v2 2/9] dm: cpu: Test against cpu_ops->get_info in cpu_get_info() Bin Meng
@ 2015-06-12 19:10 ` Simon Glass
2015-06-12 23:03 ` Simon Glass
0 siblings, 1 reply; 13+ messages in thread
From: Simon Glass @ 2015-06-12 19:10 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 12 June 2015 at 00:52, Bin Meng <bmeng.cn@gmail.com> wrote:
> In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
> if it is NULL. It should test against cpu_ops->get_info.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
> drivers/cpu/cpu-uclass.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
I have the same commit locally - I thought I sent it but obviously not.
Acked-by: Simon Glass <sjg@chromium.org>
Regards,
Simon
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 2/9] dm: cpu: Test against cpu_ops->get_info in cpu_get_info()
2015-06-12 19:10 ` Simon Glass
@ 2015-06-12 23:03 ` Simon Glass
0 siblings, 0 replies; 13+ messages in thread
From: Simon Glass @ 2015-06-12 23:03 UTC (permalink / raw)
To: u-boot
On 12 June 2015 at 13:10, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 12 June 2015 at 00:52, Bin Meng <bmeng.cn@gmail.com> wrote:
>> In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
>> if it is NULL. It should test against cpu_ops->get_info.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>
>> Changes in v2: None
>>
>> drivers/cpu/cpu-uclass.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> I have the same commit locally - I thought I sent it but obviously not.
>
> Acked-by: Simon Glass <sjg@chromium.org>
Applied to u-boot-x86.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/9] x86: dm: Clean up cpu drivers
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
2015-06-12 6:52 ` [U-Boot] [PATCH v2 2/9] dm: cpu: Test against cpu_ops->get_info in cpu_get_info() Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 23:03 ` Simon Glass
2015-06-12 6:52 ` [U-Boot] [PATCH v2 4/9] x86: Move MP initialization codes into a common place Bin Meng
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
cpu_x86_bind()
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
arch/x86/cpu/Makefile | 2 +-
arch/x86/cpu/baytrail/cpu.c | 15 +++----------
arch/x86/cpu/cpu.c | 28 ------------------------
arch/x86/cpu/cpu_x86.c | 48 ++++++++++++++++++++++++++++++++++++++++++
arch/x86/include/asm/cpu.h | 14 ------------
arch/x86/include/asm/cpu_x86.h | 34 ++++++++++++++++++++++++++++++
6 files changed, 86 insertions(+), 55 deletions(-)
create mode 100644 arch/x86/cpu/cpu_x86.c
create mode 100644 arch/x86/include/asm/cpu_x86.h
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7ff05e6..48197fb 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -10,7 +10,7 @@
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o call64.o
+obj-y += interrupts.o cpu.o cpu_x86.o call64.o
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 1d48206..05156a5 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -10,6 +10,7 @@
#include <cpu.h>
#include <dm.h>
#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
#include <asm/lapic.h>
#include <asm/mp.h>
#include <asm/msr.h>
@@ -175,18 +176,8 @@ static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
return 0;
}
-static int cpu_x86_baytrail_bind(struct udevice *dev)
-{
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
-
- plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "intel,apic-id", -1);
-
- return 0;
-}
-
static const struct cpu_ops cpu_x86_baytrail_ops = {
- .get_desc = x86_cpu_get_desc,
+ .get_desc = cpu_x86_get_desc,
.get_info = baytrail_get_info,
};
@@ -199,7 +190,7 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
.name = "cpu_x86_baytrail",
.id = UCLASS_CPU,
.of_match = cpu_x86_baytrail_ids,
- .bind = cpu_x86_baytrail_bind,
+ .bind = cpu_x86_bind,
.probe = cpu_x86_baytrail_probe,
.ops = &cpu_x86_baytrail_ops,
};
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index bb4a110..ffb6e43 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -21,8 +21,6 @@
#include <common.h>
#include <command.h>
-#include <cpu.h>
-#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
@@ -520,16 +518,6 @@ char *cpu_get_name(char *name)
return ptr;
}
-int x86_cpu_get_desc(struct udevice *dev, char *buf, int size)
-{
- if (size < CPU_MAX_NAME_LEN)
- return -ENOSPC;
-
- cpu_get_name(buf);
-
- return 0;
-}
-
int default_print_cpuinfo(void)
{
printf("CPU: %s, vendor %s, device %xh\n",
@@ -622,19 +610,3 @@ int cpu_init_r(void)
{
return x86_init_cpus();
}
-
-static const struct cpu_ops cpu_x86_ops = {
- .get_desc = x86_cpu_get_desc,
-};
-
-static const struct udevice_id cpu_x86_ids[] = {
- { .compatible = "cpu-x86" },
- { }
-};
-
-U_BOOT_DRIVER(cpu_x86_drv) = {
- .name = "cpu_x86",
- .id = UCLASS_CPU,
- .of_match = cpu_x86_ids,
- .ops = &cpu_x86_ops,
-};
diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c
new file mode 100644
index 0000000..d32ba66
--- /dev/null
+++ b/arch/x86/cpu/cpu_x86.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu.h>
+
+int cpu_x86_bind(struct udevice *dev)
+{
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+ plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "intel,apic-id", -1);
+
+ return 0;
+}
+
+int cpu_x86_get_desc(struct udevice *dev, char *buf, int size)
+{
+ if (size < CPU_MAX_NAME_LEN)
+ return -ENOSPC;
+
+ cpu_get_name(buf);
+
+ return 0;
+}
+
+static const struct cpu_ops cpu_x86_ops = {
+ .get_desc = cpu_x86_get_desc,
+};
+
+static const struct udevice_id cpu_x86_ids[] = {
+ { .compatible = "cpu-x86" },
+ { }
+};
+
+U_BOOT_DRIVER(cpu_x86_drv) = {
+ .name = "cpu_x86",
+ .id = UCLASS_CPU,
+ .of_match = cpu_x86_ids,
+ .bind = cpu_x86_bind,
+ .ops = &cpu_x86_ops,
+};
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index ebc74ad..08284ee 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -197,20 +197,6 @@ const char *cpu_vendor_name(int vendor);
char *cpu_get_name(char *name);
/**
- *
-* x86_cpu_get_desc() - Get a description string for an x86 CPU
-*
-* This uses cpu_get_name() and is suitable to use as the get_desc() method for
-* the CPU uclass.
-*
-* @dev: Device to check (UCLASS_CPU)
-* @buf: Buffer to place string
-* @size: Size of string space
-* @return 0 if OK, -ENOSPC if buffer is too small, other -ve on error
-*/
-int x86_cpu_get_desc(struct udevice *dev, char *buf, int size);
-
-/**
* cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
*
* The kernel is uncompressed and the 64-bit entry point is expected to be
diff --git a/arch/x86/include/asm/cpu_x86.h b/arch/x86/include/asm/cpu_x86.h
new file mode 100644
index 0000000..1940480
--- /dev/null
+++ b/arch/x86/include/asm/cpu_x86.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_CPU_X86_H
+#define _ASM_CPU_X86_H
+
+/**
+ * cpu_x86_bind() - Bind an x86 CPU with the driver
+ *
+ * This updates cpu device's platform data with information from device tree,
+ * like the processor local apic id.
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @return 0 always
+ */
+int cpu_x86_bind(struct udevice *dev);
+
+/**
+ * cpu_x86_get_desc() - Get a description string for an x86 CPU
+ *
+ * This uses cpu_get_name() and is suitable to use as the get_desc() method for
+ * the CPU uclass.
+ *
+ * @dev: Device to check (UCLASS_CPU)
+ * @buf: Buffer to place string
+ * @size: Size of string space
+ * @return: 0 if OK, -ENOSPC if buffer is too small, other -ve on error
+ */
+int cpu_x86_get_desc(struct udevice *dev, char *buf, int size);
+
+#endif /* _ASM_CPU_X86_H */
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/9] x86: dm: Clean up cpu drivers
2015-06-12 6:52 ` [U-Boot] [PATCH v2 3/9] x86: dm: Clean up cpu drivers Bin Meng
@ 2015-06-12 23:03 ` Simon Glass
0 siblings, 0 replies; 13+ messages in thread
From: Simon Glass @ 2015-06-12 23:03 UTC (permalink / raw)
To: u-boot
On 12 June 2015 at 00:52, Bin Meng <bmeng.cn@gmail.com> wrote:
> This commit does the following to clean up x86 cpu dm drivers:
> - Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
> file arch/x86/cpu/cpu_x86.c
> - Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
> naming with other dm drivers
> - Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
> the same as the one in the intel baytrail cpu driver
> - Update intel baytrail cpu driver to use cpu_x86_get_desc() and
> cpu_x86_bind()
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2: None
>
> arch/x86/cpu/Makefile | 2 +-
> arch/x86/cpu/baytrail/cpu.c | 15 +++----------
> arch/x86/cpu/cpu.c | 28 ------------------------
> arch/x86/cpu/cpu_x86.c | 48 ++++++++++++++++++++++++++++++++++++++++++
> arch/x86/include/asm/cpu.h | 14 ------------
> arch/x86/include/asm/cpu_x86.h | 34 ++++++++++++++++++++++++++++++
> 6 files changed, 86 insertions(+), 55 deletions(-)
> create mode 100644 arch/x86/cpu/cpu_x86.c
> create mode 100644 arch/x86/include/asm/cpu_x86.h
Applied to u-boot-x86.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 4/9] x86: Move MP initialization codes into a common place
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
2015-06-12 6:52 ` [U-Boot] [PATCH v2 2/9] dm: cpu: Test against cpu_ops->get_info in cpu_get_info() Bin Meng
2015-06-12 6:52 ` [U-Boot] [PATCH v2 3/9] x86: dm: Clean up cpu drivers Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 6:52 ` [U-Boot] [PATCH v2 5/9] x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP Bin Meng
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and declare a weak
detect_num_cpus() which just returns 2 which is minimally required.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2: None
arch/x86/cpu/baytrail/cpu.c | 44 +-----------------------------------------
arch/x86/cpu/cpu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+), 43 deletions(-)
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 05156a5..7805056 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -12,23 +12,11 @@
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/lapic.h>
-#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/turbo.h>
#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
- return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
- MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
- /* Wait for APs to finish initialization before proceeding. */
- MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int detect_num_cpus(void)
+int detect_num_cpus(void)
{
int ecx = 0;
@@ -52,38 +40,8 @@ static int detect_num_cpus(void)
ecx++;
}
}
-
-static int baytrail_init_cpus(void)
-{
- struct mp_params mp_params;
-
- lapic_setup();
-
- mp_params.num_cpus = detect_num_cpus();
- mp_params.parallel_microcode_load = 0,
- mp_params.flight_plan = &mp_steps[0];
- mp_params.num_records = ARRAY_SIZE(mp_steps);
- mp_params.microcode_pointer = 0;
-
- if (mp_init(&mp_params)) {
- printf("Warning: MP init failure\n");
- return -EIO;
- }
-
- return 0;
-}
#endif
-int x86_init_cpus(void)
-{
-#ifdef CONFIG_SMP
- debug("Init additional CPUs\n");
- baytrail_init_cpus();
-#endif
-
- return 0;
-}
-
static void set_max_freq(void)
{
msr_t perf_ctl;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index ffb6e43..ddc7dc3 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -21,10 +21,13 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
#include <asm/cpu.h>
+#include <asm/lapic.h>
+#include <asm/mp.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
@@ -601,8 +604,52 @@ int last_stage_init(void)
}
#endif
+#ifdef CONFIG_SMP
+static int enable_smis(struct udevice *cpu, void *unused)
+{
+ return 0;
+}
+
+static struct mp_flight_record mp_steps[] = {
+ MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
+ /* Wait for APs to finish initialization before proceeding */
+ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
+};
+
+__weak int detect_num_cpus(void)
+{
+ /* We need at least 2 cores to perform mp_init() */
+ return 2;
+}
+
+static int x86_mp_init(void)
+{
+ struct mp_params mp_params;
+
+ lapic_setup();
+
+ mp_params.num_cpus = detect_num_cpus();
+ mp_params.parallel_microcode_load = 0,
+ mp_params.flight_plan = &mp_steps[0];
+ mp_params.num_records = ARRAY_SIZE(mp_steps);
+ mp_params.microcode_pointer = 0;
+
+ if (mp_init(&mp_params)) {
+ printf("Warning: MP init failure\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
+
__weak int x86_init_cpus(void)
{
+#ifdef CONFIG_SMP
+ debug("Init additional CPUs\n");
+ x86_mp_init();
+#endif
+
return 0;
}
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 5/9] x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
` (2 preceding siblings ...)
2015-06-12 6:52 ` [U-Boot] [PATCH v2 4/9] x86: Move MP initialization codes into a common place Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 23:03 ` Simon Glass
2015-06-12 6:52 ` [U-Boot] [PATCH v2 6/9] x86: kconfig: Fix minor nits in MAX_CPUS Bin Meng
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
arch/x86/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3506ba2..d4cd9ed 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -228,6 +228,7 @@ config FSP_TEMP_RAM_ADDR
config MAX_CPUS
int "Maximum number of CPUs permitted"
+ depends on SMP
default 4
help
When using multi-CPU chips it is possible for U-Boot to start up
@@ -249,6 +250,7 @@ config SMP
config AP_STACK_SIZE
hex
+ depends on SMP
default 0x1000
help
Each additional CPU started by U-Boot requires its own stack. This
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 6/9] x86: kconfig: Fix minor nits in MAX_CPUS
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
` (3 preceding siblings ...)
2015-06-12 6:52 ` [U-Boot] [PATCH v2 5/9] x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 23:03 ` Simon Glass
2015-06-12 6:52 ` [U-Boot] [PATCH v2 7/9] x86: Move lapic_setup() call into init_bsp() Bin Meng
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
arch/x86/Kconfig | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d4cd9ed..4757011 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -226,18 +226,6 @@ config FSP_TEMP_RAM_ADDR
Stack top address which is used in FspInit after DRAM is ready and
CAR is disabled.
-config MAX_CPUS
- int "Maximum number of CPUs permitted"
- depends on SMP
- default 4
- help
- When using multi-CPU chips it is possible for U-Boot to start up
- more than one CPU. The stack memory used by all of these CPUs is
- pre-allocated so at present U-Boot wants to know the maximum
- number of CPUs that may be present. Set this to at least as high
- as the number of CPUs in your system (it uses about 4KB of RAM for
- each CPU).
-
config SMP
bool "Enable Symmetric Multiprocessing"
default n
@@ -248,6 +236,18 @@ config SMP
only one CPU will be enabled regardless of the number of CPUs
available.
+config MAX_CPUS
+ int "Maximum number of CPUs permitted"
+ depends on SMP
+ default 4
+ help
+ When using multi-CPU chips it is possible for U-Boot to start up
+ more than one CPU. The stack memory used by all of these CPUs is
+ pre-allocated so at present U-Boot wants to know the maximum
+ number of CPUs that may be present. Set this to at least as high
+ as the number of CPUs in your system (it uses about 4KB of RAM for
+ each CPU).
+
config AP_STACK_SIZE
hex
depends on SMP
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 7/9] x86: Move lapic_setup() call into init_bsp()
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
` (4 preceding siblings ...)
2015-06-12 6:52 ` [U-Boot] [PATCH v2 6/9] x86: kconfig: Fix minor nits in MAX_CPUS Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 6:52 ` [U-Boot] [PATCH v2 8/9] x86: Clean up lapic codes Bin Meng
2015-06-12 6:52 ` [U-Boot] [PATCH v2 9/9] x86: crownbay: Add MP initialization Bin Meng
7 siblings, 0 replies; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
arch/x86/cpu/cpu.c | 2 --
arch/x86/cpu/mp_init.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index ddc7dc3..dd1b18b 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -626,8 +626,6 @@ static int x86_mp_init(void)
{
struct mp_params mp_params;
- lapic_setup();
-
mp_params.num_cpus = detect_num_cpus();
mp_params.parallel_microcode_load = 0,
mp_params.flight_plan = &mp_steps[0];
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index ac5753a..864eb63 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -415,7 +415,7 @@ static int init_bsp(struct udevice **devp)
cpu_get_name(processor_name);
debug("CPU: %s.\n", processor_name);
- enable_lapic();
+ lapic_setup();
apic_id = lapicid();
ret = find_cpu_by_apid_id(apic_id, devp);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 8/9] x86: Clean up lapic codes
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
` (5 preceding siblings ...)
2015-06-12 6:52 ` [U-Boot] [PATCH v2 7/9] x86: Move lapic_setup() call into init_bsp() Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
2015-06-12 6:52 ` [U-Boot] [PATCH v2 9/9] x86: crownbay: Add MP initialization Bin Meng
7 siblings, 0 replies; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 2 +-
arch/x86/cpu/lapic.c | 38 ++++----
arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++-
arch/x86/include/asm/lapic.h | 131 ++++++++++++++------------
arch/x86/include/asm/lapic_def.h | 101 --------------------
5 files changed, 103 insertions(+), 183 deletions(-)
delete mode 100644 arch/x86/include/asm/lapic_def.h
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 8b08c40..fd7db97 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -13,12 +13,12 @@
#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
-#include <asm/lapic_def.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
+#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
static void enable_vmx(void)
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 4690603..6769ae5 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -8,50 +8,46 @@
*/
#include <common.h>
-#include <asm/msr.h>
-#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/post.h>
void lapic_setup(void)
{
-#if NEED_LAPIC == 1
+#ifdef CONFIG_SMP
/* Only Pentium Pro and later have those MSR stuff */
debug("Setting up local apic: ");
/* Enable the local apic */
enable_lapic();
- /*
- * Set Task Priority to 'accept all'.
- */
+ /* Set Task Priority to 'accept all' */
lapic_write_around(LAPIC_TASKPRI,
lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
/* Put the local apic in virtual wire mode */
lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
- ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+ ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
- LAPIC_DELIVERY_MODE_EXTINT));
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_EXTINT));
lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
- LAPIC_DELIVERY_MODE_NMI));
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_NMI));
debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !NEED_LLAPIC */
+#else /* !CONFIG_SMP */
/* Only Pentium Pro and later have those MSR stuff */
debug("Disabling local apic: ");
disable_lapic();
-#endif /* !NEED_LAPIC */
+#endif /* CONFIG_SMP */
debug("done.\n");
post_code(POST_LAPIC);
}
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 5ae32f7..7786493 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -16,7 +16,19 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
const void *blob, int node);
int bd82x6x_init(void);
-struct x86_cpu_priv;
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+ int apic_id;
+ int start_err;
+};
+
int model_206ax_init(struct x86_cpu_priv *cpu);
#endif
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
index 0a7f443..f60974a 100644
--- a/arch/x86/include/asm/lapic.h
+++ b/arch/x86/include/asm/lapic.h
@@ -1,5 +1,5 @@
/*
- * From Coreboot file of same name
+ * From coreboot file of same name
*
* Copyright (C) 2014 Google, Inc
*
@@ -10,16 +10,61 @@
#define _ARCH_ASM_LAPIC_H
#include <asm/io.h>
-#include <asm/lapic_def.h>
#include <asm/msr.h>
+#include <asm/msr-index.h>
#include <asm/processor.h>
-/* See if I need to initialize the local apic */
-#if CONFIG_SMP || CONFIG_IOAPIC
-# define NEED_LAPIC 1
-#else
-# define NEED_LAPIC 0
-#endif
+#define LAPIC_DEFAULT_BASE 0xfee00000
+
+#define LAPIC_ID 0x020
+#define LAPIC_LVR 0x030
+
+#define LAPIC_TASKPRI 0x080
+#define LAPIC_TPRI_MASK 0xff
+
+#define LAPIC_RRR 0x0c0
+
+#define LAPIC_SPIV 0x0f0
+#define LAPIC_SPIV_ENABLE 0x100
+
+#define LAPIC_ICR 0x300
+#define LAPIC_DEST_SELF 0x40000
+#define LAPIC_DEST_ALLINC 0x80000
+#define LAPIC_DEST_ALLBUT 0xc0000
+#define LAPIC_ICR_RR_MASK 0x30000
+#define LAPIC_ICR_RR_INVALID 0x00000
+#define LAPIC_ICR_RR_INPROG 0x10000
+#define LAPIC_ICR_RR_VALID 0x20000
+#define LAPIC_INT_LEVELTRIG 0x08000
+#define LAPIC_INT_ASSERT 0x04000
+#define LAPIC_ICR_BUSY 0x01000
+#define LAPIC_DEST_LOGICAL 0x00800
+#define LAPIC_DM_FIXED 0x00000
+#define LAPIC_DM_LOWEST 0x00100
+#define LAPIC_DM_SMI 0x00200
+#define LAPIC_DM_REMRD 0x00300
+#define LAPIC_DM_NMI 0x00400
+#define LAPIC_DM_INIT 0x00500
+#define LAPIC_DM_STARTUP 0x00600
+#define LAPIC_DM_EXTINT 0x00700
+#define LAPIC_VECTOR_MASK 0x000ff
+
+#define LAPIC_ICR2 0x310
+#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xff)
+#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
+
+#define LAPIC_LVT0 0x350
+#define LAPIC_LVT1 0x360
+#define LAPIC_LVT_MASKED (1 << 16)
+#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
+#define LAPIC_LVT_REMOTE_IRR (1 << 14)
+#define LAPIC_INPUT_POLARITY (1 << 13)
+#define LAPIC_SEND_PENDING (1 << 12)
+#define LAPIC_LVT_RESERVED_1 (1 << 11)
+#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
+#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
+#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
+#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
static inline __attribute__((always_inline))
unsigned long lapic_read(unsigned long reg)
@@ -42,21 +87,21 @@ static inline void enable_lapic(void)
{
msr_t msr;
- msr = msr_read(LAPIC_BASE_MSR);
+ msr = msr_read(MSR_IA32_APICBASE);
msr.hi &= 0xffffff00;
- msr.lo |= LAPIC_BASE_MSR_ENABLE;
- msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+ msr.lo |= MSR_IA32_APICBASE_ENABLE;
+ msr.lo &= ~MSR_IA32_APICBASE_BASE;
msr.lo |= LAPIC_DEFAULT_BASE;
- msr_write(LAPIC_BASE_MSR, msr);
+ msr_write(MSR_IA32_APICBASE, msr);
}
static inline void disable_lapic(void)
{
msr_t msr;
- msr = msr_read(LAPIC_BASE_MSR);
- msr.lo &= ~(1 << 11);
- msr_write(LAPIC_BASE_MSR, msr);
+ msr = msr_read(MSR_IA32_APICBASE);
+ msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+ msr_write(MSR_IA32_APICBASE, msr);
}
static inline __attribute__((always_inline)) unsigned long lapicid(void)
@@ -64,30 +109,24 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
return lapic_read(LAPIC_ID) >> 24;
}
-#if !CONFIG_AP_IN_SIPI_WAIT
-/* If we need to go back to sipi wait, we use the long non-inlined version of
- * this function in lapic_cpu_init.c
- */
static inline __attribute__((always_inline)) void stop_this_cpu(void)
{
/* Called by an AP when it is ready to halt and wait for a new task */
for (;;)
cpu_hlt();
}
-#else
-void stop_this_cpu(void);
-#endif
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
- sizeof(*(ptr))))
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr))))
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
+ *
* Note 2: xchg has side effect, so that attribute volatile is necessary,
- * but generally the primitive is invalid, *ptr is output argument. --ANK
+ * but generally the primitive is invalid, *ptr is output argument.
*/
static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
int size)
@@ -121,25 +160,19 @@ static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
}
-
-#ifdef X86_GOOD_APIC
-# define FORCE_READ_AROUND_WRITE 0
-# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x, y) lapic_write((x), (y))
-#else
-# define FORCE_READ_AROUND_WRITE 1
-# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
-#endif
+#define lapic_read_around(x) lapic_read(x)
+#define lapic_write_around(x, y) lapic_write_atomic((x), (y))
static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
{
int timeout;
unsigned long status;
int result;
+
lapic_wait_icr_idle();
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+
timeout = 0;
do {
status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
@@ -150,30 +183,10 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
*pvalue = lapic_read(LAPIC_RRR);
result = 0;
}
+
return result;
}
-
void lapic_setup(void);
-#if CONFIG_SMP
-struct device;
-int start_cpu(struct device *cpu);
-#endif /* CONFIG_SMP */
-
-int boot_cpu(void);
-
-/**
- * struct x86_cpu_priv - Information about a single CPU
- *
- * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
- * just a number representing the CPU core
- *
- * TODO: Move this to driver model once lifecycle is understood
- */
-struct x86_cpu_priv {
- int apic_id;
- int start_err;
-};
-
#endif
diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h
deleted file mode 100644
index 722cead..0000000
--- a/arch/x86/include/asm/lapic_def.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Taken from the Coreboot file of the same name
- *
- * (C) Copyright 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _ASM_LAPIC_DEF_H
-#define _ASM_LAPIC_DEF_H
-
-#define LAPIC_BASE_MSR 0x1B
-#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
-#define LAPIC_BASE_MSR_ENABLE (1 << 11)
-#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
-
-#define LOCAL_APIC_ADDR 0xfee00000
-#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
-
-#define LAPIC_ID 0x020
-#define LAPIC_LVR 0x030
-#define LAPIC_TASKPRI 0x80
-#define LAPIC_TPRI_MASK 0xFF
-#define LAPIC_ARBID 0x090
-#define LAPIC_RRR 0x0C0
-#define LAPIC_SVR 0x0f0
-#define LAPIC_SPIV 0x0f0
-#define LAPIC_SPIV_ENABLE 0x100
-#define LAPIC_ESR 0x280
-#define LAPIC_ESR_SEND_CS 0x00001
-#define LAPIC_ESR_RECV_CS 0x00002
-#define LAPIC_ESR_SEND_ACC 0x00004
-#define LAPIC_ESR_RECV_ACC 0x00008
-#define LAPIC_ESR_SENDILL 0x00020
-#define LAPIC_ESR_RECVILL 0x00040
-#define LAPIC_ESR_ILLREGA 0x00080
-#define LAPIC_ICR 0x300
-#define LAPIC_DEST_SELF 0x40000
-#define LAPIC_DEST_ALLINC 0x80000
-#define LAPIC_DEST_ALLBUT 0xC0000
-#define LAPIC_ICR_RR_MASK 0x30000
-#define LAPIC_ICR_RR_INVALID 0x00000
-#define LAPIC_ICR_RR_INPROG 0x10000
-#define LAPIC_ICR_RR_VALID 0x20000
-#define LAPIC_INT_LEVELTRIG 0x08000
-#define LAPIC_INT_ASSERT 0x04000
-#define LAPIC_ICR_BUSY 0x01000
-#define LAPIC_DEST_LOGICAL 0x00800
-#define LAPIC_DM_FIXED 0x00000
-#define LAPIC_DM_LOWEST 0x00100
-#define LAPIC_DM_SMI 0x00200
-#define LAPIC_DM_REMRD 0x00300
-#define LAPIC_DM_NMI 0x00400
-#define LAPIC_DM_INIT 0x00500
-#define LAPIC_DM_STARTUP 0x00600
-#define LAPIC_DM_EXTINT 0x00700
-#define LAPIC_VECTOR_MASK 0x000FF
-#define LAPIC_ICR2 0x310
-#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
-#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
-#define LAPIC_LVTT 0x320
-#define LAPIC_LVTPC 0x340
-#define LAPIC_LVT0 0x350
-#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18)
-#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
-#define SET_LAPIC_TIMER_BASE(x) (((x) << 18))
-#define LAPIC_TIMER_BASE_CLKIN 0x0
-#define LAPIC_TIMER_BASE_TMBASE 0x1
-#define LAPIC_TIMER_BASE_DIV 0x2
-#define LAPIC_LVT_TIMER_PERIODIC (1 << 17)
-#define LAPIC_LVT_MASKED (1 << 16)
-#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
-#define LAPIC_LVT_REMOTE_IRR (1 << 14)
-#define LAPIC_INPUT_POLARITY (1 << 13)
-#define LAPIC_SEND_PENDING (1 << 12)
-#define LAPIC_LVT_RESERVED_1 (1 << 11)
-#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
-#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
-#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
-#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
-#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
-#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8))
-#define LAPIC_MODE_FIXED 0x0
-#define LAPIC_MODE_NMI 0x4
-#define LAPIC_MODE_EXINT 0x7
-#define LAPIC_LVT1 0x360
-#define LAPIC_LVTERR 0x370
-#define LAPIC_TMICT 0x380
-#define LAPIC_TMCCT 0x390
-#define LAPIC_TDCR 0x3E0
-#define LAPIC_TDR_DIV_TMBASE (1 << 2)
-#define LAPIC_TDR_DIV_1 0xB
-#define LAPIC_TDR_DIV_2 0x0
-#define LAPIC_TDR_DIV_4 0x1
-#define LAPIC_TDR_DIV_8 0x2
-#define LAPIC_TDR_DIV_16 0x3
-#define LAPIC_TDR_DIV_32 0x8
-#define LAPIC_TDR_DIV_64 0x9
-#define LAPIC_TDR_DIV_128 0xA
-
-#endif
--
1.8.2.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 9/9] x86: crownbay: Add MP initialization
[not found] <1434091946-19913-1-git-send-email-bmeng.cn@gmail.com>
` (6 preceding siblings ...)
2015-06-12 6:52 ` [U-Boot] [PATCH v2 8/9] x86: Clean up lapic codes Bin Meng
@ 2015-06-12 6:52 ` Bin Meng
7 siblings, 0 replies; 13+ messages in thread
From: Bin Meng @ 2015-06-12 6:52 UTC (permalink / raw)
To: u-boot
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to
match the order in Kconfig
arch/x86/dts/crownbay.dts | 20 ++++++++++++++++++++
configs/crownbay_defconfig | 4 ++++
2 files changed, 24 insertions(+)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index d68efda..1ec90cd 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -23,6 +23,26 @@
silent_console = <0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d3a370d..d21177d 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -2,6 +2,10 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_TARGET_CROWNBAY=y
+CONFIG_SMP=y
+CONFIG_MAX_CPUS=2
CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_CMD_CPU=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
+CONFIG_CPU=y
--
1.8.2.1
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