* [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
[not found] <1434510939-25285-1-git-send-email-bmeng.cn@gmail.com>
@ 2015-06-17 3:15 ` Bin Meng
2015-06-24 2:44 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place Bin Meng
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2015-06-17 3:15 UTC (permalink / raw)
To: u-boot
Ivybridge is not ready for U-Boot MP initialization yet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v4: None
Changes in v3:
- New patch to remove SMP from CPU_SPECIFIC_OPTIONS for ivybridge
Changes in v2: None
arch/x86/cpu/ivybridge/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index e4595be..0e249a4 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -95,7 +95,6 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
- select SMP
select SSE2
select UDELAY_LAPIC
select CPU_MICROCODE_IN_CBFS
--
1.8.2.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place
[not found] <1434510939-25285-1-git-send-email-bmeng.cn@gmail.com>
2015-06-17 3:15 ` [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Bin Meng
@ 2015-06-17 3:15 ` Bin Meng
2015-06-24 2:45 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp() Bin Meng
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2015-06-17 3:15 UTC (permalink / raw)
To: u-boot
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v4:
- Update to match cpu_get_count()
Changes in v3:
- Remove num_cpus from struct mp_params
- Call cpu_get_count() in mp_init() to get the number of CPUs
- Add missing DECLARE_GLOBAL_DATA_PTR in cpu-uclass.c and cpu_x86.c
Changes in v2: None
arch/x86/cpu/baytrail/cpu.c | 98 ++++++++++++++-------------------------------
arch/x86/cpu/cpu.c | 40 ++++++++++++++++++
arch/x86/cpu/cpu_x86.c | 28 +++++++++++++
arch/x86/cpu/mp_init.c | 18 +++++++--
arch/x86/include/asm/mp.h | 1 -
drivers/cpu/cpu-uclass.c | 2 +
6 files changed, 114 insertions(+), 73 deletions(-)
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 05156a5..a011730 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -12,78 +12,9 @@
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
#include <asm/lapic.h>
-#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/turbo.h>
-#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
- return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
- MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
- /* Wait for APs to finish initialization before proceeding. */
- MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int detect_num_cpus(void)
-{
- int ecx = 0;
-
- /*
- * Use the algorithm described in Intel 64 and IA-32 Architectures
- * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
- * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
- * of CPUID Extended Topology Leaf.
- */
- while (1) {
- struct cpuid_result leaf_b;
-
- leaf_b = cpuid_ext(0xb, ecx);
-
- /*
- * Bay Trail doesn't have hyperthreading so just determine the
- * number of cores by from level type (ecx[15:8] == * 2)
- */
- if ((leaf_b.ecx & 0xff00) == 0x0200)
- return leaf_b.ebx & 0xffff;
- ecx++;
- }
-}
-
-static int baytrail_init_cpus(void)
-{
- struct mp_params mp_params;
-
- lapic_setup();
-
- mp_params.num_cpus = detect_num_cpus();
- mp_params.parallel_microcode_load = 0,
- mp_params.flight_plan = &mp_steps[0];
- mp_params.num_records = ARRAY_SIZE(mp_steps);
- mp_params.microcode_pointer = 0;
-
- if (mp_init(&mp_params)) {
- printf("Warning: MP init failure\n");
- return -EIO;
- }
-
- return 0;
-}
-#endif
-
-int x86_init_cpus(void)
-{
-#ifdef CONFIG_SMP
- debug("Init additional CPUs\n");
- baytrail_init_cpus();
-#endif
-
- return 0;
-}
-
static void set_max_freq(void)
{
msr_t perf_ctl;
@@ -176,9 +107,38 @@ static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
return 0;
}
+static int baytrail_get_count(struct udevice *dev)
+{
+ int ecx = 0;
+
+ /*
+ * Use the algorithm described in Intel 64 and IA-32 Architectures
+ * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+ * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+ * of CPUID Extended Topology Leaf.
+ */
+ while (1) {
+ struct cpuid_result leaf_b;
+
+ leaf_b = cpuid_ext(0xb, ecx);
+
+ /*
+ * Bay Trail doesn't have hyperthreading so just determine the
+ * number of cores by from level type (ecx[15:8] == * 2)
+ */
+ if ((leaf_b.ecx & 0xff00) == 0x0200)
+ return leaf_b.ebx & 0xffff;
+
+ ecx++;
+ }
+
+ return 0;
+}
+
static const struct cpu_ops cpu_x86_baytrail_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = baytrail_get_info,
+ .get_count = baytrail_get_count,
};
static const struct udevice_id cpu_x86_baytrail_ids[] = {
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 1dfd9e6..a6e88cf 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -21,10 +21,13 @@
#include <common.h>
#include <command.h>
+#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <asm/control_regs.h>
#include <asm/cpu.h>
+#include <asm/lapic.h>
+#include <asm/mp.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
@@ -621,8 +624,45 @@ int last_stage_init(void)
}
#endif
+#ifdef CONFIG_SMP
+static int enable_smis(struct udevice *cpu, void *unused)
+{
+ return 0;
+}
+
+static struct mp_flight_record mp_steps[] = {
+ MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
+ /* Wait for APs to finish initialization before proceeding */
+ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
+};
+
+static int x86_mp_init(void)
+{
+ struct mp_params mp_params;
+
+ lapic_setup();
+
+ mp_params.parallel_microcode_load = 0,
+ mp_params.flight_plan = &mp_steps[0];
+ mp_params.num_records = ARRAY_SIZE(mp_steps);
+ mp_params.microcode_pointer = 0;
+
+ if (mp_init(&mp_params)) {
+ printf("Warning: MP init failure\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif
+
__weak int x86_init_cpus(void)
{
+#ifdef CONFIG_SMP
+ debug("Init additional CPUs\n");
+ x86_mp_init();
+#endif
+
return 0;
}
diff --git a/arch/x86/cpu/cpu_x86.c b/arch/x86/cpu/cpu_x86.c
index d32ba66..0941041 100644
--- a/arch/x86/cpu/cpu_x86.c
+++ b/arch/x86/cpu/cpu_x86.c
@@ -10,6 +10,8 @@
#include <errno.h>
#include <asm/cpu.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int cpu_x86_bind(struct udevice *dev)
{
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
@@ -30,8 +32,34 @@ int cpu_x86_get_desc(struct udevice *dev, char *buf, int size)
return 0;
}
+static int cpu_x86_get_count(struct udevice *dev)
+{
+ int node, cpu;
+ int num = 0;
+
+ node = fdt_path_offset(gd->fdt_blob, "/cpus");
+ if (node < 0)
+ return -ENOENT;
+
+ for (cpu = fdt_first_subnode(gd->fdt_blob, node);
+ cpu >= 0;
+ cpu = fdt_next_subnode(gd->fdt_blob, cpu)) {
+ const char *device_type;
+
+ device_type = fdt_getprop(gd->fdt_blob, cpu,
+ "device_type", NULL);
+ if (!device_type)
+ continue;
+ if (strcmp(device_type, "cpu") == 0)
+ num++;
+ }
+
+ return num;
+}
+
static const struct cpu_ops cpu_x86_ops = {
.get_desc = cpu_x86_get_desc,
+ .get_count = cpu_x86_get_count,
};
static const struct udevice_id cpu_x86_ids[] = {
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index ac5753a..5564d84 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -22,6 +22,9 @@
#include <dm/uclass-internal.h>
#include <linux/linkage.h>
+/* Total CPUs include BSP */
+static int num_cpus;
+
/* This also needs to match the sipi.S assembly code for saved MSR encoding */
struct saved_msr {
uint32_t index;
@@ -383,7 +386,7 @@ static int bsp_do_flight_plan(struct udevice *cpu, struct mp_params *mp_params)
int ret = 0;
const int timeout_us = 100000;
const int step_us = 100;
- int num_aps = mp_params->num_cpus - 1;
+ int num_aps = num_cpus - 1;
for (i = 0; i < mp_params->num_records; i++) {
struct mp_flight_record *rec = &mp_params->flight_plan[i];
@@ -451,7 +454,16 @@ int mp_init(struct mp_params *p)
return -1;
}
- ret = check_cpu_devices(p->num_cpus);
+ num_cpus = cpu_get_count(cpu);
+ if (num_cpus < 0) {
+ debug("Cannot get number of CPUs: err=%d\n", num_cpus);
+ return num_cpus;
+ }
+
+ if (num_cpus < 2)
+ debug("Warning: Only 1 CPU is detected\n");
+
+ ret = check_cpu_devices(num_cpus);
if (ret)
debug("Warning: Device tree does not describe all CPUs. Extra ones will not be started correctly\n");
@@ -471,7 +483,7 @@ int mp_init(struct mp_params *p)
wbinvd();
/* Start the APs providing number of APs and the cpus_entered field */
- num_aps = p->num_cpus - 1;
+ num_aps = num_cpus - 1;
ret = start_aps(num_aps, ap_count);
if (ret) {
mdelay(1000);
diff --git a/arch/x86/include/asm/mp.h b/arch/x86/include/asm/mp.h
index c0930fd..2e6c312 100644
--- a/arch/x86/include/asm/mp.h
+++ b/arch/x86/include/asm/mp.h
@@ -59,7 +59,6 @@ struct mp_flight_record {
* SMM support.
*/
struct mp_params {
- int num_cpus; /* Total cpus include BSP */
int parallel_microcode_load;
const void *microcode_pointer;
/* Flight plan for APs and BSP */
diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c
index a2814a8..7660f99 100644
--- a/drivers/cpu/cpu-uclass.c
+++ b/drivers/cpu/cpu-uclass.c
@@ -12,6 +12,8 @@
#include <dm/lists.h>
#include <dm/root.h>
+DECLARE_GLOBAL_DATA_PTR;
+
int cpu_get_desc(struct udevice *dev, char *buf, int size)
{
struct cpu_ops *ops = cpu_get_ops(dev);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp()
[not found] <1434510939-25285-1-git-send-email-bmeng.cn@gmail.com>
2015-06-17 3:15 ` [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Bin Meng
2015-06-17 3:15 ` [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place Bin Meng
@ 2015-06-17 3:15 ` Bin Meng
2015-06-24 2:45 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes Bin Meng
2015-06-17 3:15 ` [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization Bin Meng
4 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2015-06-17 3:15 UTC (permalink / raw)
To: u-boot
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/cpu/cpu.c | 2 --
arch/x86/cpu/mp_init.c | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index a6e88cf..d108ee5 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -640,8 +640,6 @@ static int x86_mp_init(void)
{
struct mp_params mp_params;
- lapic_setup();
-
mp_params.parallel_microcode_load = 0,
mp_params.flight_plan = &mp_steps[0];
mp_params.num_records = ARRAY_SIZE(mp_steps);
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 5564d84..e8bc9b6 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -418,7 +418,7 @@ static int init_bsp(struct udevice **devp)
cpu_get_name(processor_name);
debug("CPU: %s.\n", processor_name);
- enable_lapic();
+ lapic_setup();
apic_id = lapicid();
ret = find_cpu_by_apid_id(apic_id, devp);
--
1.8.2.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes
[not found] <1434510939-25285-1-git-send-email-bmeng.cn@gmail.com>
` (2 preceding siblings ...)
2015-06-17 3:15 ` [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp() Bin Meng
@ 2015-06-17 3:15 ` Bin Meng
2015-06-24 2:45 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization Bin Meng
4 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2015-06-17 3:15 UTC (permalink / raw)
To: u-boot
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/x86/cpu/ivybridge/model_206ax.c | 2 +-
arch/x86/cpu/lapic.c | 38 ++++----
arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++-
arch/x86/include/asm/lapic.h | 131 ++++++++++++++------------
arch/x86/include/asm/lapic_def.h | 101 --------------------
5 files changed, 103 insertions(+), 183 deletions(-)
delete mode 100644 arch/x86/include/asm/lapic_def.h
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 8b08c40..fd7db97 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -13,12 +13,12 @@
#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/lapic.h>
-#include <asm/lapic_def.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
+#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
static void enable_vmx(void)
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 4690603..6769ae5 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -8,50 +8,46 @@
*/
#include <common.h>
-#include <asm/msr.h>
-#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/post.h>
void lapic_setup(void)
{
-#if NEED_LAPIC == 1
+#ifdef CONFIG_SMP
/* Only Pentium Pro and later have those MSR stuff */
debug("Setting up local apic: ");
/* Enable the local apic */
enable_lapic();
- /*
- * Set Task Priority to 'accept all'.
- */
+ /* Set Task Priority to 'accept all' */
lapic_write_around(LAPIC_TASKPRI,
lapic_read_around(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
/* Put the local apic in virtual wire mode */
lapic_write_around(LAPIC_SPIV, (lapic_read_around(LAPIC_SPIV) &
- ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
+ ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) &
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
- LAPIC_DELIVERY_MODE_EXTINT));
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_EXTINT));
lapic_write_around(LAPIC_LVT1, (lapic_read_around(LAPIC_LVT1) &
- ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
- LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
- LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
- LAPIC_DELIVERY_MODE_MASK)) |
- (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
- LAPIC_DELIVERY_MODE_NMI));
+ ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
+ LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
+ LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+ LAPIC_DELIVERY_MODE_MASK)) |
+ (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
+ LAPIC_DELIVERY_MODE_NMI));
debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !NEED_LLAPIC */
+#else /* !CONFIG_SMP */
/* Only Pentium Pro and later have those MSR stuff */
debug("Disabling local apic: ");
disable_lapic();
-#endif /* !NEED_LAPIC */
+#endif /* CONFIG_SMP */
debug("done.\n");
post_code(POST_LAPIC);
}
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index 5ae32f7..7786493 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -16,7 +16,19 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
const void *blob, int node);
int bd82x6x_init(void);
-struct x86_cpu_priv;
+/**
+ * struct x86_cpu_priv - Information about a single CPU
+ *
+ * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
+ * just a number representing the CPU core
+ *
+ * TODO: Move this to driver model once lifecycle is understood
+ */
+struct x86_cpu_priv {
+ int apic_id;
+ int start_err;
+};
+
int model_206ax_init(struct x86_cpu_priv *cpu);
#endif
diff --git a/arch/x86/include/asm/lapic.h b/arch/x86/include/asm/lapic.h
index 0a7f443..f60974a 100644
--- a/arch/x86/include/asm/lapic.h
+++ b/arch/x86/include/asm/lapic.h
@@ -1,5 +1,5 @@
/*
- * From Coreboot file of same name
+ * From coreboot file of same name
*
* Copyright (C) 2014 Google, Inc
*
@@ -10,16 +10,61 @@
#define _ARCH_ASM_LAPIC_H
#include <asm/io.h>
-#include <asm/lapic_def.h>
#include <asm/msr.h>
+#include <asm/msr-index.h>
#include <asm/processor.h>
-/* See if I need to initialize the local apic */
-#if CONFIG_SMP || CONFIG_IOAPIC
-# define NEED_LAPIC 1
-#else
-# define NEED_LAPIC 0
-#endif
+#define LAPIC_DEFAULT_BASE 0xfee00000
+
+#define LAPIC_ID 0x020
+#define LAPIC_LVR 0x030
+
+#define LAPIC_TASKPRI 0x080
+#define LAPIC_TPRI_MASK 0xff
+
+#define LAPIC_RRR 0x0c0
+
+#define LAPIC_SPIV 0x0f0
+#define LAPIC_SPIV_ENABLE 0x100
+
+#define LAPIC_ICR 0x300
+#define LAPIC_DEST_SELF 0x40000
+#define LAPIC_DEST_ALLINC 0x80000
+#define LAPIC_DEST_ALLBUT 0xc0000
+#define LAPIC_ICR_RR_MASK 0x30000
+#define LAPIC_ICR_RR_INVALID 0x00000
+#define LAPIC_ICR_RR_INPROG 0x10000
+#define LAPIC_ICR_RR_VALID 0x20000
+#define LAPIC_INT_LEVELTRIG 0x08000
+#define LAPIC_INT_ASSERT 0x04000
+#define LAPIC_ICR_BUSY 0x01000
+#define LAPIC_DEST_LOGICAL 0x00800
+#define LAPIC_DM_FIXED 0x00000
+#define LAPIC_DM_LOWEST 0x00100
+#define LAPIC_DM_SMI 0x00200
+#define LAPIC_DM_REMRD 0x00300
+#define LAPIC_DM_NMI 0x00400
+#define LAPIC_DM_INIT 0x00500
+#define LAPIC_DM_STARTUP 0x00600
+#define LAPIC_DM_EXTINT 0x00700
+#define LAPIC_VECTOR_MASK 0x000ff
+
+#define LAPIC_ICR2 0x310
+#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xff)
+#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
+
+#define LAPIC_LVT0 0x350
+#define LAPIC_LVT1 0x360
+#define LAPIC_LVT_MASKED (1 << 16)
+#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
+#define LAPIC_LVT_REMOTE_IRR (1 << 14)
+#define LAPIC_INPUT_POLARITY (1 << 13)
+#define LAPIC_SEND_PENDING (1 << 12)
+#define LAPIC_LVT_RESERVED_1 (1 << 11)
+#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
+#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
+#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
+#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
static inline __attribute__((always_inline))
unsigned long lapic_read(unsigned long reg)
@@ -42,21 +87,21 @@ static inline void enable_lapic(void)
{
msr_t msr;
- msr = msr_read(LAPIC_BASE_MSR);
+ msr = msr_read(MSR_IA32_APICBASE);
msr.hi &= 0xffffff00;
- msr.lo |= LAPIC_BASE_MSR_ENABLE;
- msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+ msr.lo |= MSR_IA32_APICBASE_ENABLE;
+ msr.lo &= ~MSR_IA32_APICBASE_BASE;
msr.lo |= LAPIC_DEFAULT_BASE;
- msr_write(LAPIC_BASE_MSR, msr);
+ msr_write(MSR_IA32_APICBASE, msr);
}
static inline void disable_lapic(void)
{
msr_t msr;
- msr = msr_read(LAPIC_BASE_MSR);
- msr.lo &= ~(1 << 11);
- msr_write(LAPIC_BASE_MSR, msr);
+ msr = msr_read(MSR_IA32_APICBASE);
+ msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+ msr_write(MSR_IA32_APICBASE, msr);
}
static inline __attribute__((always_inline)) unsigned long lapicid(void)
@@ -64,30 +109,24 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
return lapic_read(LAPIC_ID) >> 24;
}
-#if !CONFIG_AP_IN_SIPI_WAIT
-/* If we need to go back to sipi wait, we use the long non-inlined version of
- * this function in lapic_cpu_init.c
- */
static inline __attribute__((always_inline)) void stop_this_cpu(void)
{
/* Called by an AP when it is ready to halt and wait for a new task */
for (;;)
cpu_hlt();
}
-#else
-void stop_this_cpu(void);
-#endif
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
- sizeof(*(ptr))))
+#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
+ sizeof(*(ptr))))
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
+ *
* Note 2: xchg has side effect, so that attribute volatile is necessary,
- * but generally the primitive is invalid, *ptr is output argument. --ANK
+ * but generally the primitive is invalid, *ptr is output argument.
*/
static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
int size)
@@ -121,25 +160,19 @@ static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
}
-
-#ifdef X86_GOOD_APIC
-# define FORCE_READ_AROUND_WRITE 0
-# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x, y) lapic_write((x), (y))
-#else
-# define FORCE_READ_AROUND_WRITE 1
-# define lapic_read_around(x) lapic_read(x)
-# define lapic_write_around(x, y) lapic_write_atomic((x), (y))
-#endif
+#define lapic_read_around(x) lapic_read(x)
+#define lapic_write_around(x, y) lapic_write_atomic((x), (y))
static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
{
int timeout;
unsigned long status;
int result;
+
lapic_wait_icr_idle();
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
+
timeout = 0;
do {
status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
@@ -150,30 +183,10 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
*pvalue = lapic_read(LAPIC_RRR);
result = 0;
}
+
return result;
}
-
void lapic_setup(void);
-#if CONFIG_SMP
-struct device;
-int start_cpu(struct device *cpu);
-#endif /* CONFIG_SMP */
-
-int boot_cpu(void);
-
-/**
- * struct x86_cpu_priv - Information about a single CPU
- *
- * @apic_id: Advanced Programmable Interrupt Controller Identifier, which is
- * just a number representing the CPU core
- *
- * TODO: Move this to driver model once lifecycle is understood
- */
-struct x86_cpu_priv {
- int apic_id;
- int start_err;
-};
-
#endif
diff --git a/arch/x86/include/asm/lapic_def.h b/arch/x86/include/asm/lapic_def.h
deleted file mode 100644
index 722cead..0000000
--- a/arch/x86/include/asm/lapic_def.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Taken from the Coreboot file of the same name
- *
- * (C) Copyright 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#ifndef _ASM_LAPIC_DEF_H
-#define _ASM_LAPIC_DEF_H
-
-#define LAPIC_BASE_MSR 0x1B
-#define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
-#define LAPIC_BASE_MSR_ENABLE (1 << 11)
-#define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
-
-#define LOCAL_APIC_ADDR 0xfee00000
-#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
-
-#define LAPIC_ID 0x020
-#define LAPIC_LVR 0x030
-#define LAPIC_TASKPRI 0x80
-#define LAPIC_TPRI_MASK 0xFF
-#define LAPIC_ARBID 0x090
-#define LAPIC_RRR 0x0C0
-#define LAPIC_SVR 0x0f0
-#define LAPIC_SPIV 0x0f0
-#define LAPIC_SPIV_ENABLE 0x100
-#define LAPIC_ESR 0x280
-#define LAPIC_ESR_SEND_CS 0x00001
-#define LAPIC_ESR_RECV_CS 0x00002
-#define LAPIC_ESR_SEND_ACC 0x00004
-#define LAPIC_ESR_RECV_ACC 0x00008
-#define LAPIC_ESR_SENDILL 0x00020
-#define LAPIC_ESR_RECVILL 0x00040
-#define LAPIC_ESR_ILLREGA 0x00080
-#define LAPIC_ICR 0x300
-#define LAPIC_DEST_SELF 0x40000
-#define LAPIC_DEST_ALLINC 0x80000
-#define LAPIC_DEST_ALLBUT 0xC0000
-#define LAPIC_ICR_RR_MASK 0x30000
-#define LAPIC_ICR_RR_INVALID 0x00000
-#define LAPIC_ICR_RR_INPROG 0x10000
-#define LAPIC_ICR_RR_VALID 0x20000
-#define LAPIC_INT_LEVELTRIG 0x08000
-#define LAPIC_INT_ASSERT 0x04000
-#define LAPIC_ICR_BUSY 0x01000
-#define LAPIC_DEST_LOGICAL 0x00800
-#define LAPIC_DM_FIXED 0x00000
-#define LAPIC_DM_LOWEST 0x00100
-#define LAPIC_DM_SMI 0x00200
-#define LAPIC_DM_REMRD 0x00300
-#define LAPIC_DM_NMI 0x00400
-#define LAPIC_DM_INIT 0x00500
-#define LAPIC_DM_STARTUP 0x00600
-#define LAPIC_DM_EXTINT 0x00700
-#define LAPIC_VECTOR_MASK 0x000FF
-#define LAPIC_ICR2 0x310
-#define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
-#define SET_LAPIC_DEST_FIELD(x) ((x) << 24)
-#define LAPIC_LVTT 0x320
-#define LAPIC_LVTPC 0x340
-#define LAPIC_LVT0 0x350
-#define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18)
-#define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
-#define SET_LAPIC_TIMER_BASE(x) (((x) << 18))
-#define LAPIC_TIMER_BASE_CLKIN 0x0
-#define LAPIC_TIMER_BASE_TMBASE 0x1
-#define LAPIC_TIMER_BASE_DIV 0x2
-#define LAPIC_LVT_TIMER_PERIODIC (1 << 17)
-#define LAPIC_LVT_MASKED (1 << 16)
-#define LAPIC_LVT_LEVEL_TRIGGER (1 << 15)
-#define LAPIC_LVT_REMOTE_IRR (1 << 14)
-#define LAPIC_INPUT_POLARITY (1 << 13)
-#define LAPIC_SEND_PENDING (1 << 12)
-#define LAPIC_LVT_RESERVED_1 (1 << 11)
-#define LAPIC_DELIVERY_MODE_MASK (7 << 8)
-#define LAPIC_DELIVERY_MODE_FIXED (0 << 8)
-#define LAPIC_DELIVERY_MODE_NMI (4 << 8)
-#define LAPIC_DELIVERY_MODE_EXTINT (7 << 8)
-#define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7)
-#define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8))
-#define LAPIC_MODE_FIXED 0x0
-#define LAPIC_MODE_NMI 0x4
-#define LAPIC_MODE_EXINT 0x7
-#define LAPIC_LVT1 0x360
-#define LAPIC_LVTERR 0x370
-#define LAPIC_TMICT 0x380
-#define LAPIC_TMCCT 0x390
-#define LAPIC_TDCR 0x3E0
-#define LAPIC_TDR_DIV_TMBASE (1 << 2)
-#define LAPIC_TDR_DIV_1 0xB
-#define LAPIC_TDR_DIV_2 0x0
-#define LAPIC_TDR_DIV_4 0x1
-#define LAPIC_TDR_DIV_8 0x2
-#define LAPIC_TDR_DIV_16 0x3
-#define LAPIC_TDR_DIV_32 0x8
-#define LAPIC_TDR_DIV_64 0x9
-#define LAPIC_TDR_DIV_128 0xA
-
-#endif
--
1.8.2.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization
[not found] <1434510939-25285-1-git-send-email-bmeng.cn@gmail.com>
` (3 preceding siblings ...)
2015-06-17 3:15 ` [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes Bin Meng
@ 2015-06-17 3:15 ` Bin Meng
2015-06-24 2:45 ` Simon Glass
4 siblings, 1 reply; 10+ messages in thread
From: Bin Meng @ 2015-06-17 3:15 UTC (permalink / raw)
To: u-boot
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to
match the order in Kconfig
arch/x86/dts/crownbay.dts | 20 ++++++++++++++++++++
configs/crownbay_defconfig | 4 ++++
2 files changed, 24 insertions(+)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index d68efda..1ec90cd 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -23,6 +23,26 @@
silent_console = <0>;
};
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <0>;
+ intel,apic-id = <0>;
+ };
+
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "cpu-x86";
+ reg = <1>;
+ intel,apic-id = <1>;
+ };
+
+ };
+
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d3a370d..d21177d 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -2,6 +2,10 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="crownbay"
CONFIG_TARGET_CROWNBAY=y
+CONFIG_SMP=y
+CONFIG_MAX_CPUS=2
CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_CMD_CPU=y
CONFIG_CMD_NET=y
CONFIG_OF_CONTROL=y
+CONFIG_CPU=y
--
1.8.2.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
2015-06-17 3:15 ` [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Bin Meng
@ 2015-06-24 2:44 ` Simon Glass
0 siblings, 0 replies; 10+ messages in thread
From: Simon Glass @ 2015-06-24 2:44 UTC (permalink / raw)
To: u-boot
Hi Bin,
On 16 June 2015 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Ivybridge is not ready for U-Boot MP initialization yet.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - New patch to remove SMP from CPU_SPECIFIC_OPTIONS for ivybridge
>
> Changes in v2: None
>
> arch/x86/cpu/ivybridge/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
I'm going to apply this series now since it seems that the SFI-only
mutiprocessor support is not good enough.
Applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place
2015-06-17 3:15 ` [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place Bin Meng
@ 2015-06-24 2:45 ` Simon Glass
0 siblings, 0 replies; 10+ messages in thread
From: Simon Glass @ 2015-06-24 2:45 UTC (permalink / raw)
To: u-boot
On 16 June 2015 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote:
> Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
> common to all x86 processors, except detect_num_cpus() which varies
> from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
> new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
> cpu_get_count() in mp_init() to get the number of CPUs.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4:
> - Update to match cpu_get_count()
>
> Changes in v3:
> - Remove num_cpus from struct mp_params
> - Call cpu_get_count() in mp_init() to get the number of CPUs
> - Add missing DECLARE_GLOBAL_DATA_PTR in cpu-uclass.c and cpu_x86.c
>
> Changes in v2: None
>
> arch/x86/cpu/baytrail/cpu.c | 98 ++++++++++++++-------------------------------
> arch/x86/cpu/cpu.c | 40 ++++++++++++++++++
> arch/x86/cpu/cpu_x86.c | 28 +++++++++++++
> arch/x86/cpu/mp_init.c | 18 +++++++--
> arch/x86/include/asm/mp.h | 1 -
> drivers/cpu/cpu-uclass.c | 2 +
> 6 files changed, 114 insertions(+), 73 deletions(-)
Applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp()
2015-06-17 3:15 ` [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp() Bin Meng
@ 2015-06-24 2:45 ` Simon Glass
0 siblings, 0 replies; 10+ messages in thread
From: Simon Glass @ 2015-06-24 2:45 UTC (permalink / raw)
To: u-boot
On 16 June 2015 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote:
> Currently lapic_setup() is called before calling mp_init(), which
> then calls init_bsp() where it calls enable_lapic(), which was
> already enabled in lapic_setup(). Hence move lapic_setup() call
> into init_bsp() to avoid the duplication.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> arch/x86/cpu/cpu.c | 2 --
> arch/x86/cpu/mp_init.c | 2 +-
> 2 files changed, 1 insertion(+), 3 deletions(-)
Applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes
2015-06-17 3:15 ` [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes Bin Meng
@ 2015-06-24 2:45 ` Simon Glass
0 siblings, 0 replies; 10+ messages in thread
From: Simon Glass @ 2015-06-24 2:45 UTC (permalink / raw)
To: u-boot
On 16 June 2015 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote:
> This commit cleans up the lapic codes:
> - Delete arch/x86/include/asm/lapic_def.h, and move register and bit
> defines into arch/x86/include/asm/lapic.h
> - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
> - Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
> CONFIG_AP_IN_SIPI_WAIT
> - Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
> it is not apic related and only used by ivybridge
> - Fix coding convention issues
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> arch/x86/cpu/ivybridge/model_206ax.c | 2 +-
> arch/x86/cpu/lapic.c | 38 ++++----
> arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++-
> arch/x86/include/asm/lapic.h | 131 ++++++++++++++------------
> arch/x86/include/asm/lapic_def.h | 101 --------------------
> 5 files changed, 103 insertions(+), 183 deletions(-)
> delete mode 100644 arch/x86/include/asm/lapic_def.h
Applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization
2015-06-17 3:15 ` [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization Bin Meng
@ 2015-06-24 2:45 ` Simon Glass
0 siblings, 0 replies; 10+ messages in thread
From: Simon Glass @ 2015-06-24 2:45 UTC (permalink / raw)
To: u-boot
On 16 June 2015 at 21:15, Bin Meng <bmeng.cn@gmail.com> wrote:
> Intel Crown Bay board has a TunnelCreek processor which supports
> hyper-threading. Add /cpus node in the crownbay.dts and enable
> the MP initialization.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Acked-by: Simon Glass <sjg@chromium.org>
>
> ---
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to
> match the order in Kconfig
>
> arch/x86/dts/crownbay.dts | 20 ++++++++++++++++++++
> configs/crownbay_defconfig | 4 ++++
> 2 files changed, 24 insertions(+)
Applied to u-boot-x86, thanks!
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-06-24 2:45 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <1434510939-25285-1-git-send-email-bmeng.cn@gmail.com>
2015-06-17 3:15 ` [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS Bin Meng
2015-06-24 2:44 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place Bin Meng
2015-06-24 2:45 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp() Bin Meng
2015-06-24 2:45 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes Bin Meng
2015-06-24 2:45 ` Simon Glass
2015-06-17 3:15 ` [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization Bin Meng
2015-06-24 2:45 ` Simon Glass
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.