* [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
@ 2017-09-25 6:15 Pixel Ding
[not found] ` <1506320151-7386-1-git-send-email-Pixel.Ding-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Pixel Ding @ 2017-09-25 6:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Pixel.Ding-5C7GfCeVMHo,
Frank.Min-5C7GfCeVMHo, Monk.Liu-5C7GfCeVMHo,
Alexander.Deucher-5C7GfCeVMHo
Both Tonga and Vega register SPECs indicate that this registers only
use 31:2 bits in DW. SRIOV test case immediately fails withtout this
shift.
Signed-off-by: Pixel Ding <Pixel.Ding@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 72f31cc..947f019 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -714,7 +714,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
- lower_32_bits(wptr_gpu_addr));
+ lower_32_bits(wptr_gpu_addr) >> 2);
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index c26d205..26d7f03 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -665,7 +665,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
- lower_32_bits(wptr_gpu_addr));
+ lower_32_bits(wptr_gpu_addr) >> 2);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
[not found] ` <1506320151-7386-1-git-send-email-Pixel.Ding-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-25 6:37 ` Liu, Monk
[not found] ` <BLUPR12MB0449E6B2520C186E65DBE477847A0-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Liu, Monk @ 2017-09-25 6:37 UTC (permalink / raw)
To: Ding, Pixel, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hold on,
We didn't hit test fail without your patch, actually at least VEGA10 doesn't have the issue you mentioned,
Can you elaborate what issue or test case you can fix with this patch ?
Besides, please don't change anything on vega10 before you verified it
BR Monk
-----Original Message-----
From: Pixel Ding [mailto:Pixel.Ding@amd.com]
Sent: Monday, September 25, 2017 2:16 PM
To: amd-gfx@lists.freedesktop.org; Ding, Pixel <Pixel.Ding@amd.com>; Min, Frank <Frank.Min@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
Both Tonga and Vega register SPECs indicate that this registers only use 31:2 bits in DW. SRIOV test case immediately fails withtout this shift.
Signed-off-by: Pixel Ding <Pixel.Ding@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 72f31cc..947f019 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -714,7 +714,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
- lower_32_bits(wptr_gpu_addr));
+ lower_32_bits(wptr_gpu_addr) >> 2);
WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index c26d205..26d7f03 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -665,7 +665,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
- lower_32_bits(wptr_gpu_addr));
+ lower_32_bits(wptr_gpu_addr) >> 2);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
[not found] ` <BLUPR12MB0449E6B2520C186E65DBE477847A0-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-09-25 6:41 ` Ding, Pixel
[not found] ` <D1BCE7C1-EC7F-4DF3-98EF-AEEB376C5A29-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Ding, Pixel @ 2017-09-25 6:41 UTC (permalink / raw)
To: Liu, Monk, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Min, Frank,
Deucher, Alexander, Yu, Xiangliang
Hi Monk,
The world switch gets immediately fail. According to Xiangliang’s comment, I think 17.50 also has this issue. Other G branch uses original patch from Frank, that doesn’t have this issue. Please confirm this.
Also refer to http://adcweb02.amd.com/orlvalid/regspec/web_regspec/vega11/regspec/vega11_chip/public/index.html
SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
ADDR 31:2
I update a v2 patch for this. I think it must fail if you really overwrite the address to 31:0.
—
Sincerely Yours,
Pixel
On 25/09/2017, 2:37 PM, "Liu, Monk" <Monk.Liu@amd.com> wrote:
>Hold on,
>
>We didn't hit test fail without your patch, actually at least VEGA10 doesn't have the issue you mentioned,
>Can you elaborate what issue or test case you can fix with this patch ?
>Besides, please don't change anything on vega10 before you verified it
>
>BR Monk
>
>-----Original Message-----
>From: Pixel Ding [mailto:Pixel.Ding@amd.com]
>Sent: Monday, September 25, 2017 2:16 PM
>To: amd-gfx@lists.freedesktop.org; Ding, Pixel <Pixel.Ding@amd.com>; Min, Frank <Frank.Min@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
>Subject: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
>
>Both Tonga and Vega register SPECs indicate that this registers only use 31:2 bits in DW. SRIOV test case immediately fails withtout this shift.
>
>Signed-off-by: Pixel Ding <Pixel.Ding@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>index 72f31cc..947f019 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>@@ -714,7 +714,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
>
> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
>- lower_32_bits(wptr_gpu_addr));
>+ lower_32_bits(wptr_gpu_addr) >> 2);
> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
> upper_32_bits(wptr_gpu_addr));
> wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>index c26d205..26d7f03 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>@@ -665,7 +665,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
> /* setup the wptr shadow polling */
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
> WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
>- lower_32_bits(wptr_gpu_addr));
>+ lower_32_bits(wptr_gpu_addr) >> 2);
> WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
> upper_32_bits(wptr_gpu_addr));
> wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
>--
>2.7.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
[not found] ` <D1BCE7C1-EC7F-4DF3-98EF-AEEB376C5A29-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-25 6:45 ` Yu, Xiangliang
2017-09-25 7:12 ` Liu, Monk
1 sibling, 0 replies; 5+ messages in thread
From: Yu, Xiangliang @ 2017-09-25 6:45 UTC (permalink / raw)
To: Ding, Pixel, Liu, Monk, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
Min, Frank, Deucher, Alexander
RB: Xiangliang Yu <Xiangliang.Yu@amd.com>
-----Original Message-----
From: Ding, Pixel
Sent: Monday, September 25, 2017 2:42 PM
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org; Min, Frank <Frank.Min@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Yu, Xiangliang <Xiangliang.Yu@amd.com>
Subject: Re: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
Hi Monk,
The world switch gets immediately fail. According to Xiangliang’s comment, I think 17.50 also has this issue. Other G branch uses original patch from Frank, that doesn’t have this issue. Please confirm this.
Also refer to http://adcweb02.amd.com/orlvalid/regspec/web_regspec/vega11/regspec/vega11_chip/public/index.html
SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
ADDR 31:2
I update a v2 patch for this. I think it must fail if you really overwrite the address to 31:0.
—
Sincerely Yours,
Pixel
On 25/09/2017, 2:37 PM, "Liu, Monk" <Monk.Liu@amd.com> wrote:
>Hold on,
>
>We didn't hit test fail without your patch, actually at least VEGA10 doesn't have the issue you mentioned,
>Can you elaborate what issue or test case you can fix with this patch ?
>Besides, please don't change anything on vega10 before you verified it
>
>BR Monk
>
>-----Original Message-----
>From: Pixel Ding [mailto:Pixel.Ding@amd.com]
>Sent: Monday, September 25, 2017 2:16 PM
>To: amd-gfx@lists.freedesktop.org; Ding, Pixel <Pixel.Ding@amd.com>; Min, Frank <Frank.Min@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
>Subject: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
>
>Both Tonga and Vega register SPECs indicate that this registers only use 31:2 bits in DW. SRIOV test case immediately fails withtout this shift.
>
>Signed-off-by: Pixel Ding <Pixel.Ding@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>index 72f31cc..947f019 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>@@ -714,7 +714,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
>
> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
>- lower_32_bits(wptr_gpu_addr));
>+ lower_32_bits(wptr_gpu_addr) >> 2);
> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
> upper_32_bits(wptr_gpu_addr));
> wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>index c26d205..26d7f03 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>@@ -665,7 +665,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
> /* setup the wptr shadow polling */
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
> WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
>- lower_32_bits(wptr_gpu_addr));
>+ lower_32_bits(wptr_gpu_addr) >> 2);
> WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
> upper_32_bits(wptr_gpu_addr));
> wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
>--
>2.7.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
[not found] ` <D1BCE7C1-EC7F-4DF3-98EF-AEEB376C5A29-5C7GfCeVMHo@public.gmane.org>
2017-09-25 6:45 ` Yu, Xiangliang
@ 2017-09-25 7:12 ` Liu, Monk
1 sibling, 0 replies; 5+ messages in thread
From: Liu, Monk @ 2017-09-25 7:12 UTC (permalink / raw)
To: Ding, Pixel, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Min,
Frank, Deucher, Alexander, Yu, Xiangliang
See the code in drm-next:
/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
lower_32_bits(wptr_gpu_addr));
WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
the wptr_gpu_addr is gpu_addr + wptr_offs * 4, so it is a value with low two bits all zero, e.g. 0xffff000C
this is your new change (v2):
> /* setup the wptr shadow polling */
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
>-
>- WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
>- lower_32_bits(wptr_gpu_addr));
>+ wptr_poll_addr_lo = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i]);
>+ wptr_poll_addr_lo = REG_SET_FIELD(wptr_poll_addr_lo, SDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
>+ ADDR, lower_32_bits(wptr_gpu_addr) >> 2);
>+ WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], wptr_poll_addr_lo;
You right shift " wptr_gpu_addr" two bits and later write it into 31:2 bits of SDMA0_GFX_RB_WPTR_POLL_ADDR_LO registers, that way
The value finally written to the register will be totally the same with or without you patch
BR Monk
-----Original Message-----
From: Ding, Pixel
Sent: Monday, September 25, 2017 2:42 PM
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org; Min, Frank <Frank.Min@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Yu, Xiangliang <Xiangliang.Yu@amd.com>
Subject: Re: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
Hi Monk,
The world switch gets immediately fail. According to Xiangliang’s comment, I think 17.50 also has this issue. Other G branch uses original patch from Frank, that doesn’t have this issue. Please confirm this.
Also refer to http://adcweb02.amd.com/orlvalid/regspec/web_regspec/vega11/regspec/vega11_chip/public/index.html
SDMA0_GFX_RB_WPTR_POLL_ADDR_LO
ADDR 31:2
I update a v2 patch for this. I think it must fail if you really overwrite the address to 31:0.
—
Sincerely Yours,
Pixel
On 25/09/2017, 2:37 PM, "Liu, Monk" <Monk.Liu@amd.com> wrote:
>Hold on,
>
>We didn't hit test fail without your patch, actually at least VEGA10 doesn't have the issue you mentioned,
>Can you elaborate what issue or test case you can fix with this patch ?
>Besides, please don't change anything on vega10 before you verified it
>
>BR Monk
>
>-----Original Message-----
>From: Pixel Ding [mailto:Pixel.Ding@amd.com]
>Sent: Monday, September 25, 2017 2:16 PM
>To: amd-gfx@lists.freedesktop.org; Ding, Pixel <Pixel.Ding@amd.com>; Min, Frank <Frank.Min@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
>Subject: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO
>
>Both Tonga and Vega register SPECs indicate that this registers only use 31:2 bits in DW. SRIOV test case immediately fails withtout this shift.
>
>Signed-off-by: Pixel Ding <Pixel.Ding@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>index 72f31cc..947f019 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>@@ -714,7 +714,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
>
> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
>- lower_32_bits(wptr_gpu_addr));
>+ lower_32_bits(wptr_gpu_addr) >> 2);
> WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
> upper_32_bits(wptr_gpu_addr));
> wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>index c26d205..26d7f03 100644
>--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>@@ -665,7 +665,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
> /* setup the wptr shadow polling */
> wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
> WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
>- lower_32_bits(wptr_gpu_addr));
>+ lower_32_bits(wptr_gpu_addr) >> 2);
> WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
> upper_32_bits(wptr_gpu_addr));
> wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
>--
>2.7.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-09-25 7:12 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-25 6:15 [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO Pixel Ding
[not found] ` <1506320151-7386-1-git-send-email-Pixel.Ding-5C7GfCeVMHo@public.gmane.org>
2017-09-25 6:37 ` Liu, Monk
[not found] ` <BLUPR12MB0449E6B2520C186E65DBE477847A0-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-09-25 6:41 ` Ding, Pixel
[not found] ` <D1BCE7C1-EC7F-4DF3-98EF-AEEB376C5A29-5C7GfCeVMHo@public.gmane.org>
2017-09-25 6:45 ` Yu, Xiangliang
2017-09-25 7:12 ` Liu, Monk
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.