[PATCH 1/4] drm/amdgpu/sriov:unmap KCQ in gfx hw_fini

[PATCH 1/4] drm/amdgpu/sriov:unmap KCQ in gfx hw_fini

[Monk Liu]

Change-Id: Ieee45a0127701ba946b5f8014ff0ac0a8a94a200
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 57 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 58 +++++++++++++++++++++++++++++++++++
 2 files changed, 115 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 0c4a3b8..a027bda 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5034,6 +5034,57 @@ static int gfx_v8_0_hw_init(void *handle)
 	return r;
 }
 
+static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = kiq_ring->adev;
+	uint32_t scratch, tmp = 0;
+	int r, i;
+
+	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	if (r) {
+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+
+	r = amdgpu_ring_alloc(kiq_ring, 10);
+	if (r) {
+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+		amdgpu_gfx_scratch_free(adev, scratch);
+		return r;
+	}
+
+	/* unmap queues */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
+						PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
+						PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
+						PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
+						PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
+	amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	/* write to scratch for completion */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+	amdgpu_ring_commit(kiq_ring);
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i >= adev->usec_timeout) {
+		DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
+		r = -EINVAL;
+	}
+	amdgpu_gfx_scratch_free(adev, scratch);
+	return r;
+}
+
 static int gfx_v8_0_hw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -5041,6 +5092,12 @@ static int gfx_v8_0_hw_fini(void *handle)
 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 	if (amdgpu_sriov_vf(adev)) {
+		int i;
+
+		/* disable KCQ to avoid CPC touch memory not valid anymore */
+		for (i = 0; i < adev->gfx.num_compute_rings; i++)
+			gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
+
 		pr_debug("For SRIOV client, shouldn't do anything.\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e2ae00d..bbae00a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2895,6 +2895,58 @@ static int gfx_v9_0_hw_init(void *handle)
 	return r;
 }
 
+static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = kiq_ring->adev;
+	uint32_t scratch, tmp = 0;
+	int r, i;
+
+	r = amdgpu_gfx_scratch_get(adev, &scratch);
+	if (r) {
+		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
+		return r;
+	}
+	WREG32(scratch, 0xCAFEDEAD);
+
+	r = amdgpu_ring_alloc(kiq_ring, 10);
+	if (r) {
+		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
+		amdgpu_gfx_scratch_free(adev, scratch);
+		return r;
+	}
+
+	/* unmap queues */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
+	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
+						PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
+						PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
+						PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
+						PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
+	amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	amdgpu_ring_write(kiq_ring, 0);
+	/* write to scratch for completion */
+	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+	amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
+	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
+	amdgpu_ring_commit(kiq_ring);
+
+	for (i = 0; i < adev->usec_timeout; i++) {
+		tmp = RREG32(scratch);
+		if (tmp == 0xDEADBEEF)
+			break;
+		DRM_UDELAY(1);
+	}
+	if (i >= adev->usec_timeout) {
+		DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
+		r = -EINVAL;
+	}
+	amdgpu_gfx_scratch_free(adev, scratch);
+	return r;
+}
+
+
 static int gfx_v9_0_hw_fini(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -2902,6 +2954,12 @@ static int gfx_v9_0_hw_fini(void *handle)
 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
 	if (amdgpu_sriov_vf(adev)) {
+		int i;
+
+		/* disable KCQ to avoid CPC touch memory not valid anymore */
+		for (i = 0; i < adev->gfx.num_compute_rings; i++)
+			gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
+
 		pr_debug("For SRIOV client, shouldn't do anything.\n");
 		return 0;
 	}
-- 
2.7.4

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[PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Monk Liu]

this way after KIQ MQD released in drv unloading, CPC
can still let KIQ access this MQD thus RLCV SAVE_VF
will not fail

Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 4f6c68f..d85962b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
 	ring = &adev->gfx.kiq.ring;
 	if (!ring->mqd_obj) {
 		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
-					    AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
+					    (amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring->mqd_obj,
 					    &ring->mqd_gpu_addr, &ring->mqd_ptr);
 		if (r) {
 			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
-- 
2.7.4

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[PATCH 3/4] drm/amdgpu:fix uvd ring fini routine(v2)

[Monk Liu]

fix missing finish uvd enc_ring.
v2:
since the adev pointer check in already in ring_fini
so drop the check outsider

Change-Id: Ib74237ca5adcb3b128c9b751fced0b7db7b09e86
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 331e34a..e8bd50c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
 
 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 {
+	int i;
 	kfree(adev->uvd.saved_bo);
 
 	amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
@@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
 
 	amdgpu_ring_fini(&adev->uvd.ring);
 
+	for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
+		amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
+
 	release_firmware(adev->uvd.fw);
 
 	return 0;
-- 
2.7.4

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[PATCH 4/4] drm/amdgpu:fix firmware memoryleak

[Monk Liu]

this fix memory leak due to request_firmware after driver
unloaded

Change-Id: I7b4724deea0a095189c344eea3801e456e9cced0
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  6 ++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 20 ++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  5 +++++
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index e028286..447d446 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -92,6 +92,12 @@ static int psp_sw_init(void *handle)
 
 static int psp_sw_fini(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	release_firmware(adev->psp.sos_fw);
+	adev->psp.sos_fw = NULL;
+	release_firmware(adev->psp.asd_fw);
+	adev->psp.asd_fw = NULL;
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index bbae00a..f768f1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -384,6 +384,25 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
         return r;
 }
 
+
+static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
+{
+	release_firmware(adev->gfx.pfp_fw);
+	adev->gfx.pfp_fw = NULL;
+	release_firmware(adev->gfx.me_fw);
+	adev->gfx.me_fw = NULL;
+	release_firmware(adev->gfx.ce_fw);
+	adev->gfx.ce_fw = NULL;
+	release_firmware(adev->gfx.rlc_fw);
+	adev->gfx.rlc_fw = NULL;
+	release_firmware(adev->gfx.mec_fw);
+	adev->gfx.mec_fw = NULL;
+	release_firmware(adev->gfx.mec2_fw);
+	adev->gfx.mec2_fw = NULL;
+
+	kfree(adev->gfx.rlc.register_list_format);
+}
+
 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 {
 	const char *chip_name;
@@ -1429,6 +1448,7 @@ static int gfx_v9_0_sw_fini(void *handle)
 
 	gfx_v9_0_mec_fini(adev);
 	gfx_v9_0_ngg_fini(adev);
+	gfx_v9_0_free_microcode(adev);
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index d5f3848..d052922 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1264,6 +1264,11 @@ static int sdma_v4_0_sw_fini(void *handle)
 	for (i = 0; i < adev->sdma.num_instances; i++)
 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
+	for (i = 0; i < adev->sdma.num_instances; i++) {
+		release_firmware(adev->sdma.instance[i].fw);
+		adev->sdma.instance[i].fw = NULL;
+	}
+
 	return 0;
 }
 
-- 
2.7.4

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Re: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Christian König]

Am 21.09.2017 um 09:12 schrieb Monk Liu:
> this way after KIQ MQD released in drv unloading, CPC
> can still let KIQ access this MQD thus RLCV SAVE_VF
> will not fail
>
> Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 4f6c68f..d85962b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
>   	ring = &adev->gfx.kiq.ring;
>   	if (!ring->mqd_obj) {
>   		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
> -					    AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
> +					    (amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring->mqd_obj,

Looks like that line is getting to long, please wrap it a bit.

Apart from that the series looks good to me, but I don't have the 
slightest idea if that is really correct what you do with the KCQ.

Patch #3 is Reviewed-by: Christian König <christian.koenig@amd.com>, the 
rest is Acked-by: Christian König <christian.koenig@amd.com>

Maybe wait for Alex/Felix to have another look as well.

Regards,
Christian.

>   					    &ring->mqd_gpu_addr, &ring->mqd_ptr);
>   		if (r) {
>   			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);


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RE: [PATCH 1/4] drm/amdgpu/sriov:unmap KCQ in gfx hw_fini

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 1/4] drm/amdgpu/sriov:unmap KCQ in gfx hw_fini
> 
> Change-Id: Ieee45a0127701ba946b5f8014ff0ac0a8a94a200
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 57
> ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 58
> +++++++++++++++++++++++++++++++++++
>  2 files changed, 115 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 0c4a3b8..a027bda 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -5034,6 +5034,57 @@ static int gfx_v8_0_hw_init(void *handle)
>  	return r;
>  }
> 
> +static int gfx_v8_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct
> amdgpu_ring *ring)
> +{
> +	struct amdgpu_device *adev = kiq_ring->adev;
> +	uint32_t scratch, tmp = 0;
> +	int r, i;
> +
> +	r = amdgpu_gfx_scratch_get(adev, &scratch);
> +	if (r) {
> +		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
> +		return r;
> +	}
> +	WREG32(scratch, 0xCAFEDEAD);
> +
> +	r = amdgpu_ring_alloc(kiq_ring, 10);
> +	if (r) {
> +		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
> +		amdgpu_gfx_scratch_free(adev, scratch);
> +		return r;
> +	}
> +
> +	/* unmap queues */
> +	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES,
> 4));
> +	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q:
> 1 */
> +
> 	PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
> +
> 	PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
> +
> 	PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
> +
> 	PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
> +	amdgpu_ring_write(kiq_ring,
> PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	/* write to scratch for completion */
> +	amdgpu_ring_write(kiq_ring,
> PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> +	amdgpu_ring_write(kiq_ring, (scratch -
> PACKET3_SET_UCONFIG_REG_START));
> +	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
> +	amdgpu_ring_commit(kiq_ring);
> +
> +	for (i = 0; i < adev->usec_timeout; i++) {
> +		tmp = RREG32(scratch);
> +		if (tmp == 0xDEADBEEF)
> +			break;
> +		DRM_UDELAY(1);
> +	}
> +	if (i >= adev->usec_timeout) {
> +		DRM_ERROR("KCQ disabled failed
> (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
> +		r = -EINVAL;
> +	}
> +	amdgpu_gfx_scratch_free(adev, scratch);
> +	return r;
> +}
> +
>  static int gfx_v8_0_hw_fini(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -5041,6 +5092,12 @@ static int gfx_v8_0_hw_fini(void *handle)
>  	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
>  	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
>  	if (amdgpu_sriov_vf(adev)) {

Might as well do this for bare metal as well to keep things consistent.

Alex



> +		int i;
> +
> +		/* disable KCQ to avoid CPC touch memory not valid anymore
> */
> +		for (i = 0; i < adev->gfx.num_compute_rings; i++)
> +			gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev-
> >gfx.compute_ring[i]);
> +
>  		pr_debug("For SRIOV client, shouldn't do anything.\n");
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e2ae00d..bbae00a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2895,6 +2895,58 @@ static int gfx_v9_0_hw_init(void *handle)
>  	return r;
>  }
> 
> +static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct
> amdgpu_ring *ring)
> +{
> +	struct amdgpu_device *adev = kiq_ring->adev;
> +	uint32_t scratch, tmp = 0;
> +	int r, i;
> +
> +	r = amdgpu_gfx_scratch_get(adev, &scratch);
> +	if (r) {
> +		DRM_ERROR("Failed to get scratch reg (%d).\n", r);
> +		return r;
> +	}
> +	WREG32(scratch, 0xCAFEDEAD);
> +
> +	r = amdgpu_ring_alloc(kiq_ring, 10);
> +	if (r) {
> +		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
> +		amdgpu_gfx_scratch_free(adev, scratch);
> +		return r;
> +	}
> +
> +	/* unmap queues */
> +	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES,
> 4));
> +	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q:
> 1 */
> +
> 	PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
> +
> 	PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
> +
> 	PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
> +
> 	PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
> +	amdgpu_ring_write(kiq_ring,
> PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	amdgpu_ring_write(kiq_ring, 0);
> +	/* write to scratch for completion */
> +	amdgpu_ring_write(kiq_ring,
> PACKET3(PACKET3_SET_UCONFIG_REG, 1));
> +	amdgpu_ring_write(kiq_ring, (scratch -
> PACKET3_SET_UCONFIG_REG_START));
> +	amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
> +	amdgpu_ring_commit(kiq_ring);
> +
> +	for (i = 0; i < adev->usec_timeout; i++) {
> +		tmp = RREG32(scratch);
> +		if (tmp == 0xDEADBEEF)
> +			break;
> +		DRM_UDELAY(1);
> +	}
> +	if (i >= adev->usec_timeout) {
> +		DRM_ERROR("KCQ disabled failed
> (scratch(0x%04X)=0x%08X)\n", scratch, tmp);
> +		r = -EINVAL;
> +	}
> +	amdgpu_gfx_scratch_free(adev, scratch);
> +	return r;
> +}
> +
> +
>  static int gfx_v9_0_hw_fini(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -2902,6 +2954,12 @@ static int gfx_v9_0_hw_fini(void *handle)
>  	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
>  	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
>  	if (amdgpu_sriov_vf(adev)) {
> +		int i;
> +
> +		/* disable KCQ to avoid CPC touch memory not valid anymore
> */
> +		for (i = 0; i < adev->gfx.num_compute_rings; i++)
> +			gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev-
> >gfx.compute_ring[i]);
> +
>  		pr_debug("For SRIOV client, shouldn't do anything.\n");
>  		return 0;
>  	}
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
> 
> this way after KIQ MQD released in drv unloading, CPC
> can still let KIQ access this MQD thus RLCV SAVE_VF
> will not fail
> 
> Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 4f6c68f..d85962b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct
> amdgpu_device *adev,
>  	ring = &adev->gfx.kiq.ring;
>  	if (!ring->mqd_obj) {
>  		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
> -					    AMDGPU_GEM_DOMAIN_GTT,
> &ring->mqd_obj,
> +					    (amdgpu_sriov_vf(adev) ?
> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring-

Here as well.  Might as well vram for both VF and bare metal for consistency.

Alex

> >mqd_obj,
>  					    &ring->mqd_gpu_addr, &ring-
> >mqd_ptr);
>  		if (r) {
>  			dev_warn(adev->dev, "failed to create ring mqd ob
> (%d)", r);
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 3/4] drm/amdgpu:fix uvd ring fini routine(v2)

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 3/4] drm/amdgpu:fix uvd ring fini routine(v2)
> 
> fix missing finish uvd enc_ring.
> v2:
> since the adev pointer check in already in ring_fini
> so drop the check outsider
> 
> Change-Id: Ib74237ca5adcb3b128c9b751fced0b7db7b09e86
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index 331e34a..e8bd50c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -269,6 +269,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device
> *adev)
> 
>  int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
>  {
> +	int i;
>  	kfree(adev->uvd.saved_bo);
> 
>  	amd_sched_entity_fini(&adev->uvd.ring.sched, &adev->uvd.entity);
> @@ -279,6 +280,9 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device
> *adev)
> 
>  	amdgpu_ring_fini(&adev->uvd.ring);
> 
> +	for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
> +		amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
> +
>  	release_firmware(adev->uvd.fw);
> 
>  	return 0;
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 4/4] drm/amdgpu:fix firmware memoryleak

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 4/4] drm/amdgpu:fix firmware memoryleak
> 
> this fix memory leak due to request_firmware after driver
> unloaded
> 
> Change-Id: I7b4724deea0a095189c344eea3801e456e9cced0
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Bonus points if you send out a patch to fix gmc  for mc firmware as well.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  6 ++++++
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 20 ++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  5 +++++
>  3 files changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index e028286..447d446 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -92,6 +92,12 @@ static int psp_sw_init(void *handle)
> 
>  static int psp_sw_fini(void *handle)
>  {
> +	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +
> +	release_firmware(adev->psp.sos_fw);
> +	adev->psp.sos_fw = NULL;
> +	release_firmware(adev->psp.asd_fw);
> +	adev->psp.asd_fw = NULL;
>  	return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index bbae00a..f768f1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -384,6 +384,25 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring
> *ring, long timeout)
>          return r;
>  }
> 
> +
> +static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
> +{
> +	release_firmware(adev->gfx.pfp_fw);
> +	adev->gfx.pfp_fw = NULL;
> +	release_firmware(adev->gfx.me_fw);
> +	adev->gfx.me_fw = NULL;
> +	release_firmware(adev->gfx.ce_fw);
> +	adev->gfx.ce_fw = NULL;
> +	release_firmware(adev->gfx.rlc_fw);
> +	adev->gfx.rlc_fw = NULL;
> +	release_firmware(adev->gfx.mec_fw);
> +	adev->gfx.mec_fw = NULL;
> +	release_firmware(adev->gfx.mec2_fw);
> +	adev->gfx.mec2_fw = NULL;
> +
> +	kfree(adev->gfx.rlc.register_list_format);
> +}
> +
>  static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>  {
>  	const char *chip_name;
> @@ -1429,6 +1448,7 @@ static int gfx_v9_0_sw_fini(void *handle)
> 
>  	gfx_v9_0_mec_fini(adev);
>  	gfx_v9_0_ngg_fini(adev);
> +	gfx_v9_0_free_microcode(adev);
> 
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index d5f3848..d052922 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -1264,6 +1264,11 @@ static int sdma_v4_0_sw_fini(void *handle)
>  	for (i = 0; i < adev->sdma.num_instances; i++)
>  		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
> 
> +	for (i = 0; i < adev->sdma.num_instances; i++) {
> +		release_firmware(adev->sdma.instance[i].fw);
> +		adev->sdma.instance[i].fw = NULL;
> +	}
> +
>  	return 0;
>  }
> 
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Liu, Monk]

Alex

Since CPU visible VRAM resource is very limited, I'm not sure BM like it or not, 
Besides, after we unify the code we'll forget why we do this on SRIOV and in future someone will change it back to GTT domain (some guy care bare-metal only) and lead to SRIOV issues and that time it's hard to recall what's going on 

I prefer keep things different that's good to maintain the stability 

BR Monk

-----Original Message-----
From: Deucher, Alexander 
Sent: 2017年9月21日 23:00
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf 
> Of Monk Liu
> Sent: Thursday, September 21, 2017 3:12 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
> 
> this way after KIQ MQD released in drv unloading, CPC can still let 
> KIQ access this MQD thus RLCV SAVE_VF will not fail
> 
> Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 4f6c68f..d85962b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct
> amdgpu_device *adev,
>  	ring = &adev->gfx.kiq.ring;
>  	if (!ring->mqd_obj) {
>  		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
> -					    AMDGPU_GEM_DOMAIN_GTT,
> &ring->mqd_obj,
> +					    (amdgpu_sriov_vf(adev) ?
> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring-

Here as well.  Might as well vram for both VF and bare metal for consistency.

Alex

> >mqd_obj,
>  					    &ring->mqd_gpu_addr, &ring-
> >mqd_ptr);
>  		if (r) {
>  			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Deucher, Alexander]

> -----Original Message-----
> From: Liu, Monk
> Sent: Thursday, September 21, 2017 11:37 PM
> To: Deucher, Alexander; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
> 
> Alex
> 
> Since CPU visible VRAM resource is very limited, I'm not sure BM like it or
> not,
> Besides, after we unify the code we'll forget why we do this on SRIOV and in
> future someone will change it back to GTT domain (some guy care bare-
> metal only) and lead to SRIOV issues and that time it's hard to recall what's
> going on

You could add a comment.  I'm ok either way for this one.
Acked-by: Alex Deucher <alexander.deucher@amd.com>

Alex

> 
> I prefer keep things different that's good to maintain the stability
> 
> BR Monk
> 
> -----Original Message-----
> From: Deucher, Alexander
> Sent: 2017年9月21日 23:00
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
> 
> > -----Original Message-----
> > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> > Of Monk Liu
> > Sent: Thursday, September 21, 2017 3:12 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Liu, Monk
> > Subject: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
> >
> > this way after KIQ MQD released in drv unloading, CPC can still let
> > KIQ access this MQD thus RLCV SAVE_VF will not fail
> >
> > Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
> > Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index 4f6c68f..d85962b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct
> > amdgpu_device *adev,
> >  	ring = &adev->gfx.kiq.ring;
> >  	if (!ring->mqd_obj) {
> >  		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
> > -					    AMDGPU_GEM_DOMAIN_GTT,
> > &ring->mqd_obj,
> > +					    (amdgpu_sriov_vf(adev) ?
> > AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring-
> 
> Here as well.  Might as well vram for both VF and bare metal for consistency.
> 
> Alex
> 
> > >mqd_obj,
> >  					    &ring->mqd_gpu_addr, &ring-
> > >mqd_ptr);
> >  		if (r) {
> >  			dev_warn(adev->dev, "failed to create ring mqd ob
> (%d)", r);
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Christian König]

Hi Monk,

I agree with Alex here. We should keep the SRIOV specialized handling to 
a minimum.

Please add a code comment if you think somebody could accidentally 
change the code back.

Regards,
Christian.

Am 22.09.2017 um 05:37 schrieb Liu, Monk:
> Alex
>
> Since CPU visible VRAM resource is very limited, I'm not sure BM like it or not,
> Besides, after we unify the code we'll forget why we do this on SRIOV and in future someone will change it back to GTT domain (some guy care bare-metal only) and lead to SRIOV issues and that time it's hard to recall what's going on
>
> I prefer keep things different that's good to maintain the stability
>
> BR Monk
>
> -----Original Message-----
> From: Deucher, Alexander
> Sent: 2017年9月21日 23:00
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
>
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Monk Liu
>> Sent: Thursday, September 21, 2017 3:12 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Liu, Monk
>> Subject: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
>>
>> this way after KIQ MQD released in drv unloading, CPC can still let
>> KIQ access this MQD thus RLCV SAVE_VF will not fail
>>
>> Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
>> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 4f6c68f..d85962b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct
>> amdgpu_device *adev,
>>   	ring = &adev->gfx.kiq.ring;
>>   	if (!ring->mqd_obj) {
>>   		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
>> -					    AMDGPU_GEM_DOMAIN_GTT,
>> &ring->mqd_obj,
>> +					    (amdgpu_sriov_vf(adev) ?
>> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring-
> Here as well.  Might as well vram for both VF and bare metal for consistency.
>
> Alex
>
>>> mqd_obj,
>>   					    &ring->mqd_gpu_addr, &ring-
>>> mqd_ptr);
>>   		if (r) {
>>   			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

[Liu, Monk]

alright

-----Original Message-----
From: Christian König [mailto:ckoenig.leichtzumerken@gmail.com] 
Sent: 2017年9月22日 15:15
To: Liu, Monk <Monk.Liu@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM

Hi Monk,

I agree with Alex here. We should keep the SRIOV specialized handling to a minimum.

Please add a code comment if you think somebody could accidentally change the code back.

Regards,
Christian.

Am 22.09.2017 um 05:37 schrieb Liu, Monk:
> Alex
>
> Since CPU visible VRAM resource is very limited, I'm not sure BM like 
> it or not, Besides, after we unify the code we'll forget why we do 
> this on SRIOV and in future someone will change it back to GTT domain 
> (some guy care bare-metal only) and lead to SRIOV issues and that time 
> it's hard to recall what's going on
>
> I prefer keep things different that's good to maintain the stability
>
> BR Monk
>
> -----Original Message-----
> From: Deucher, Alexander
> Sent: 2017年9月21日 23:00
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
>
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On 
>> Behalf Of Monk Liu
>> Sent: Thursday, September 21, 2017 3:12 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Liu, Monk
>> Subject: [PATCH 2/4] drm/amdgpu/sriov:alloc KIQ MQD in VRAM
>>
>> this way after KIQ MQD released in drv unloading, CPC can still let 
>> KIQ access this MQD thus RLCV SAVE_VF will not fail
>>
>> Change-Id: Iccef37a70c193c83af80961dae2c67ed859f1a13
>> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> index 4f6c68f..d85962b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
>> @@ -261,7 +261,7 @@ int amdgpu_gfx_compute_mqd_sw_init(struct
>> amdgpu_device *adev,
>>   	ring = &adev->gfx.kiq.ring;
>>   	if (!ring->mqd_obj) {
>>   		r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
>> -					    AMDGPU_GEM_DOMAIN_GTT,
>> &ring->mqd_obj,
>> +					    (amdgpu_sriov_vf(adev) ?
>> AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT), &ring-
> Here as well.  Might as well vram for both VF and bare metal for consistency.
>
> Alex
>
>>> mqd_obj,
>>   					    &ring->mqd_gpu_addr, &ring-
>>> mqd_ptr);
>>   		if (r) {
>>   			dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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