[U-Boot] [PATCH] Xilinx Zynq PS GPIO driver

[U-Boot] [PATCH] Xilinx Zynq PS GPIO driver

[rnd4 at dave-tech.it]

From: Andrea Scian <andrea.scian@dave.eu>

Dear all,

I've written a simple driver for Zynq PS GPIO (currently we have in U-Boot
only the Xilinx PL GPIO driver).
Most of the code is taken from Linux kernel Zynq PS GPIO driver.

It has been tested (not intensively) on our Zynq7000 SOM running U-Boot 2014.07,
however the patch refers to the latest master pulled a few minutes ago: 2015.04-rc4.
It compiles correctly on with zynq_zc770_xm010_defconfig target (of course after
manually adding the right CONFIG_ to include the driver!).

Feel free to comment the patch and, if useful, insert in next U-Boot release.

Best Regards,

Andrea Scian
DAVE Embedded Systems

Andrea Scian (1):
  gpio: add Xilinx Zynq PS GPIO driver

 arch/arm/include/asm/arch-zynq/gpio.h |   66 ++++++++++
 drivers/gpio/Makefile                 |    1 +
 drivers/gpio/zynq_gpio.c              |  220 +++++++++++++++++++++++++++++++++
 3 files changed, 287 insertions(+)
 create mode 100644 drivers/gpio/zynq_gpio.c

-- 
1.7.9.5

[U-Boot] [PATCH] gpio: add Xilinx Zynq PS GPIO driver

[rnd4 at dave-tech.it]

From: Andrea Scian <andrea.scian@dave.eu>

Most of the code is taken (and adapted) from Linux kernel driver.

Just add CONFIG_ZYNQ_GPIO to you config to enable it

Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
---
 arch/arm/include/asm/arch-zynq/gpio.h |   66 ++++++++++
 drivers/gpio/Makefile                 |    1 +
 drivers/gpio/zynq_gpio.c              |  220 +++++++++++++++++++++++++++++++++
 3 files changed, 287 insertions(+)
 create mode 100644 drivers/gpio/zynq_gpio.c

diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
index a26ae87..9e1e7da 100644
--- a/arch/arm/include/asm/arch-zynq/gpio.h
+++ b/arch/arm/include/asm/arch-zynq/gpio.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2013 Xilinx, Inc.
+ * Copyright (c) 2015 DAVE Embedded Systems
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -7,4 +8,69 @@
 #ifndef _ZYNQ_GPIO_H
 #define _ZYNQ_GPIO_H
 
+#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
+
+/* Maximum banks */
+#define ZYNQ_GPIO_MAX_BANK	4
+
+#define ZYNQ_GPIO_BANK0_NGPIO	32
+#define ZYNQ_GPIO_BANK1_NGPIO	22
+#define ZYNQ_GPIO_BANK2_NGPIO	32
+#define ZYNQ_GPIO_BANK3_NGPIO	32
+
+#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
+				 ZYNQ_GPIO_BANK1_NGPIO + \
+				 ZYNQ_GPIO_BANK2_NGPIO + \
+				 ZYNQ_GPIO_BANK3_NGPIO)
+
+#define ZYNQ_GPIO_BANK0_PIN_MIN	0
+#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
+					ZYNQ_GPIO_BANK0_NGPIO - 1)
+#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
+					ZYNQ_GPIO_BANK1_NGPIO - 1)
+#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
+					ZYNQ_GPIO_BANK2_NGPIO - 1)
+#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
+					ZYNQ_GPIO_BANK3_NGPIO - 1)
+
+/* Register offsets for the GPIO device */
+/* LSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
+/* MSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
+/* Data Register-RW */
+#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
+/* Direction mode reg-RW */
+#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
+/* Output enable reg-RW */
+#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
+/* Interrupt mask reg-RO */
+#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
+/* Interrupt enable reg-WO */
+#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
+/* Interrupt disable reg-WO */
+#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
+/* Interrupt status reg-RO */
+#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
+/* Interrupt type reg-RW */
+#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
+/* Interrupt polarity reg-RW */
+#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
+/* Interrupt on any, reg-RW */
+#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
+
+/* Disable all interrupts mask */
+#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
+
+/* Mid pin number of a bank */
+#define ZYNQ_GPIO_MID_PIN_NUM 16
+
+/* GPIO upper 16 bit mask */
+#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
+
+#define BIT(x) (1<<x)
+
 #endif /* _ZYNQ_GPIO_H */
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fe9a3b2..916ecb5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
 obj-$(CONFIG_TCA642X)		+= tca642x.o
 oby-$(CONFIG_SX151X)		+= sx151x.o
 obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
+obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
new file mode 100644
index 0000000..83a2c46
--- /dev/null
+++ b/drivers/gpio/zynq_gpio.c
@@ -0,0 +1,220 @@
+/*
+ * Xilinx Zynq GPIO device driver
+ *
+ * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
+ *
+ * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
+ * Copyright (C) 2009 - 2014 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+/**
+ * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
+ * for a given pin in the GPIO device
+ * @pin_num:	gpio pin number within the device
+ * @bank_num:	an output parameter used to return the bank number of the gpio
+ *		pin
+ * @bank_pin_num: an output parameter used to return pin number within a bank
+ *		  for the given gpio pin
+ *
+ * Returns the bank number and pin offset within the bank.
+ */
+static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
+					  unsigned int *bank_num,
+					  unsigned int *bank_pin_num)
+{
+	switch (pin_num) {
+	case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
+		*bank_num = 0;
+		*bank_pin_num = pin_num;
+		break;
+	case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
+		*bank_num = 1;
+		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
+		break;
+	case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
+		*bank_num = 2;
+		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
+		break;
+	case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
+		*bank_num = 3;
+		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
+		break;
+	default:
+		printf("invalid GPIO pin number: %u\n", pin_num);
+		*bank_num = 0;
+		*bank_pin_num = 0;
+		break;
+	}
+}
+
+int gpio_is_valid(unsigned gpio)
+{
+	return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
+}
+
+static int check_gpio(unsigned gpio)
+{
+	if (!gpio_is_valid(gpio)) {
+		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
+		return -1;
+	}
+	return 0;
+}
+
+/**
+ * gpio_get_value - Get the state of the specified pin of GPIO device
+ * @gpio:	gpio pin number within the device
+ *
+ * This function reads the state of the specified pin of the GPIO device.
+ *
+ * Return: 0 if the pin is low, 1 if pin is high.
+ */
+int gpio_get_value(unsigned gpio)
+{
+	u32 data;
+	unsigned int bank_num, bank_pin_num;
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	data = readl(ZYNQ_GPIO_BASE_ADDRESS +
+			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
+
+	return (data >> bank_pin_num) & 1;
+}
+
+/**
+ * gpio_set_value - Modify the value of the pin with specified value
+ * @gpio:	gpio pin number within the device
+ * @value:	value used to modify the value of the specified pin
+ *
+ * This function calculates the register offset (i.e to lower 16 bits or
+ * upper 16 bits) based on the given pin number and sets the value of a
+ * gpio pin to the specified value. The value is either 0 or non-zero.
+ */
+int gpio_set_value(unsigned gpio, int value)
+{
+	unsigned int reg_offset, bank_num, bank_pin_num;
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
+		/* only 16 data bits in bit maskable reg */
+		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
+		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
+	} else {
+		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
+	}
+
+	/*
+	 * get the 32 bit value to be written to the mask/data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data
+	 */
+	value = !!value;
+	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
+		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
+
+	writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset);
+
+	return 0;
+}
+
+/**
+ * gpio_direction_input - Set the direction of the specified GPIO pin as input
+ * @gpio:	gpio pin number within the device
+ *
+ * This function uses the read-modify-write sequence to set the direction of
+ * the gpio pin as input.
+ *
+ * Return: -1 if invalid gpio specified, 0 if successul
+ */
+int gpio_direction_input(unsigned gpio)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
+	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
+		return -1;
+
+	/* clear the bit in direction mode reg to set the pin as input */
+	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg &= ~BIT(bank_pin_num);
+	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+
+	return 0;
+}
+
+/**
+ * gpio_direction_output - Set the direction of the specified GPIO pin as output
+ * @gpio:	gpio pin number within the device
+ * @value:	value to be written to specified pin
+ *
+ * This function sets the direction of specified GPIO pin as output, configures
+ * the Output Enable register for the pin and uses zynq_gpio_set to set
+ * the value of the pin to the value specified.
+ *
+ * Return: 0 always
+ */
+int gpio_direction_output(unsigned gpio, int value)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
+
+	/* set the GPIO pin as output */
+	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg |= BIT(bank_pin_num);
+	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+
+	/* configure the output enable reg for the pin */
+	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+	reg |= BIT(bank_pin_num);
+	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
+
+	/* set the state of the pin */
+	gpio_set_value(gpio, value);
+	return 0;
+}
+
+/**
+ * Request a gpio before using it.
+ *
+ * NOTE: Argument 'label' is unused.
+ */
+int gpio_request(unsigned gpio, const char *label)
+{
+	if (check_gpio(gpio) < 0)
+		return -1;
+
+	return 0;
+}
+
+/**
+ * Reset and free the gpio after using it.
+ */
+int gpio_free(unsigned gpio)
+{
+	return 0;
+}
-- 
1.7.9.5

[U-Boot] [PATCH] gpio: add Xilinx Zynq PS GPIO driver

[Michal Simek]

On 03/20/2015 04:00 PM, rnd4 at dave-tech.it wrote:
> From: Andrea Scian <andrea.scian@dave.eu>
> 
> Most of the code is taken (and adapted) from Linux kernel driver.
> 
> Just add CONFIG_ZYNQ_GPIO to you config to enable it
> 
> Signed-off-by: Andrea Scian <andrea.scian@dave.eu>
> ---
>  arch/arm/include/asm/arch-zynq/gpio.h |   66 ++++++++++
>  drivers/gpio/Makefile                 |    1 +
>  drivers/gpio/zynq_gpio.c              |  220 +++++++++++++++++++++++++++++++++
>  3 files changed, 287 insertions(+)
>  create mode 100644 drivers/gpio/zynq_gpio.c
> 
> diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
> index a26ae87..9e1e7da 100644
> --- a/arch/arm/include/asm/arch-zynq/gpio.h
> +++ b/arch/arm/include/asm/arch-zynq/gpio.h
> @@ -1,5 +1,6 @@
>  /*
>   * Copyright (c) 2013 Xilinx, Inc.
> + * Copyright (c) 2015 DAVE Embedded Systems
>   *
>   * SPDX-License-Identifier:	GPL-2.0+
>   */
> @@ -7,4 +8,69 @@
>  #ifndef _ZYNQ_GPIO_H
>  #define _ZYNQ_GPIO_H
>  
> +#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
> +
> +/* Maximum banks */
> +#define ZYNQ_GPIO_MAX_BANK	4
> +
> +#define ZYNQ_GPIO_BANK0_NGPIO	32
> +#define ZYNQ_GPIO_BANK1_NGPIO	22
> +#define ZYNQ_GPIO_BANK2_NGPIO	32
> +#define ZYNQ_GPIO_BANK3_NGPIO	32
> +
> +#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
> +				 ZYNQ_GPIO_BANK1_NGPIO + \
> +				 ZYNQ_GPIO_BANK2_NGPIO + \
> +				 ZYNQ_GPIO_BANK3_NGPIO)
> +
> +#define ZYNQ_GPIO_BANK0_PIN_MIN	0
> +#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
> +					ZYNQ_GPIO_BANK0_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
> +#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
> +					ZYNQ_GPIO_BANK1_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
> +#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
> +					ZYNQ_GPIO_BANK2_NGPIO - 1)
> +#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
> +#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
> +					ZYNQ_GPIO_BANK3_NGPIO - 1)
> +
> +/* Register offsets for the GPIO device */
> +/* LSW Mask & Data -WO */
> +#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
> +/* MSW Mask & Data -WO */
> +#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
> +/* Data Register-RW */
> +#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
> +/* Direction mode reg-RW */
> +#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
> +/* Output enable reg-RW */
> +#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
> +/* Interrupt mask reg-RO */
> +#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
> +/* Interrupt enable reg-WO */
> +#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
> +/* Interrupt disable reg-WO */
> +#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
> +/* Interrupt status reg-RO */
> +#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
> +/* Interrupt type reg-RW */
> +#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
> +/* Interrupt polarity reg-RW */
> +#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
> +/* Interrupt on any, reg-RW */
> +#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
> +
> +/* Disable all interrupts mask */
> +#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
> +
> +/* Mid pin number of a bank */
> +#define ZYNQ_GPIO_MID_PIN_NUM 16
> +
> +/* GPIO upper 16 bit mask */
> +#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
> +
> +#define BIT(x) (1<<x)
> +
>  #endif /* _ZYNQ_GPIO_H */
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index fe9a3b2..916ecb5 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -41,3 +41,4 @@ obj-$(CONFIG_ADI_GPIO2)	+= adi_gpio2.o
>  obj-$(CONFIG_TCA642X)		+= tca642x.o
>  oby-$(CONFIG_SX151X)		+= sx151x.o
>  obj-$(CONFIG_SUNXI_GPIO)	+= sunxi_gpio.o
> +obj-$(CONFIG_ZYNQ_GPIO)		+= zynq_gpio.o
> diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
> new file mode 100644
> index 0000000..83a2c46
> --- /dev/null
> +++ b/drivers/gpio/zynq_gpio.c
> @@ -0,0 +1,220 @@
> +/*
> + * Xilinx Zynq GPIO device driver
> + *
> + * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
> + *
> + * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
> + * Copyright (C) 2009 - 2014 Xilinx, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>
> +
> +/**
> + * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
> + * for a given pin in the GPIO device
> + * @pin_num:	gpio pin number within the device
> + * @bank_num:	an output parameter used to return the bank number of the gpio
> + *		pin
> + * @bank_pin_num: an output parameter used to return pin number within a bank
> + *		  for the given gpio pin
> + *
> + * Returns the bank number and pin offset within the bank.
> + */
> +static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
> +					  unsigned int *bank_num,
> +					  unsigned int *bank_pin_num)
> +{
> +	switch (pin_num) {
> +	case ZYNQ_GPIO_BANK0_PIN_MIN ... ZYNQ_GPIO_BANK0_PIN_MAX:
> +		*bank_num = 0;
> +		*bank_pin_num = pin_num;
> +		break;
> +	case ZYNQ_GPIO_BANK1_PIN_MIN ... ZYNQ_GPIO_BANK1_PIN_MAX:
> +		*bank_num = 1;
> +		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK1_PIN_MIN;
> +		break;
> +	case ZYNQ_GPIO_BANK2_PIN_MIN ... ZYNQ_GPIO_BANK2_PIN_MAX:
> +		*bank_num = 2;
> +		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK2_PIN_MIN;
> +		break;
> +	case ZYNQ_GPIO_BANK3_PIN_MIN ... ZYNQ_GPIO_BANK3_PIN_MAX:
> +		*bank_num = 3;
> +		*bank_pin_num = pin_num - ZYNQ_GPIO_BANK3_PIN_MIN;
> +		break;
> +	default:
> +		printf("invalid GPIO pin number: %u\n", pin_num);
> +		*bank_num = 0;
> +		*bank_pin_num = 0;
> +		break;
> +	}
> +}
> +
> +int gpio_is_valid(unsigned gpio)
> +{
> +	return (gpio >= 0) && (gpio < ZYNQ_GPIO_NR_GPIOS);
> +}
> +
> +static int check_gpio(unsigned gpio)
> +{
> +	if (!gpio_is_valid(gpio)) {
> +		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
> +		return -1;
> +	}
> +	return 0;
> +}
> +
> +/**
> + * gpio_get_value - Get the state of the specified pin of GPIO device
> + * @gpio:	gpio pin number within the device
> + *
> + * This function reads the state of the specified pin of the GPIO device.
> + *
> + * Return: 0 if the pin is low, 1 if pin is high.
> + */
> +int gpio_get_value(unsigned gpio)
> +{
> +	u32 data;
> +	unsigned int bank_num, bank_pin_num;
> +
> +	if (check_gpio(gpio) < 0)
> +		return -1;
> +
> +	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
> +
> +	data = readl(ZYNQ_GPIO_BASE_ADDRESS +
> +			     ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
> +
> +	return (data >> bank_pin_num) & 1;
> +}
> +
> +/**
> + * gpio_set_value - Modify the value of the pin with specified value
> + * @gpio:	gpio pin number within the device
> + * @value:	value used to modify the value of the specified pin
> + *
> + * This function calculates the register offset (i.e to lower 16 bits or
> + * upper 16 bits) based on the given pin number and sets the value of a
> + * gpio pin to the specified value. The value is either 0 or non-zero.
> + */
> +int gpio_set_value(unsigned gpio, int value)
> +{
> +	unsigned int reg_offset, bank_num, bank_pin_num;
> +
> +	if (check_gpio(gpio) < 0)
> +		return -1;
> +
> +	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
> +
> +	if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
> +		/* only 16 data bits in bit maskable reg */
> +		bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
> +		reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
> +	} else {
> +		reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
> +	}
> +
> +	/*
> +	 * get the 32 bit value to be written to the mask/data register where
> +	 * the upper 16 bits is the mask and lower 16 bits is the data
> +	 */
> +	value = !!value;
> +	value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
> +		((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
> +
> +	writel(value, ZYNQ_GPIO_BASE_ADDRESS + reg_offset);
> +
> +	return 0;
> +}
> +
> +/**
> + * gpio_direction_input - Set the direction of the specified GPIO pin as input
> + * @gpio:	gpio pin number within the device
> + *
> + * This function uses the read-modify-write sequence to set the direction of
> + * the gpio pin as input.
> + *
> + * Return: -1 if invalid gpio specified, 0 if successul
> + */
> +int gpio_direction_input(unsigned gpio)
> +{
> +	u32 reg;
> +	unsigned int bank_num, bank_pin_num;
> +
> +	if (check_gpio(gpio) < 0)
> +		return -1;
> +
> +	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
> +
> +	/* bank 0 pins 7 and 8 are special and cannot be used as inputs */
> +	if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
> +		return -1;
> +
> +	/* clear the bit in direction mode reg to set the pin as input */
> +	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +	reg &= ~BIT(bank_pin_num);
> +	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +
> +	return 0;
> +}
> +
> +/**
> + * gpio_direction_output - Set the direction of the specified GPIO pin as output
> + * @gpio:	gpio pin number within the device
> + * @value:	value to be written to specified pin
> + *
> + * This function sets the direction of specified GPIO pin as output, configures
> + * the Output Enable register for the pin and uses zynq_gpio_set to set
> + * the value of the pin to the value specified.
> + *
> + * Return: 0 always
> + */
> +int gpio_direction_output(unsigned gpio, int value)
> +{
> +	u32 reg;
> +	unsigned int bank_num, bank_pin_num;
> +
> +	if (check_gpio(gpio) < 0)
> +		return -1;
> +
> +	zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num);
> +
> +	/* set the GPIO pin as output */
> +	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +	reg |= BIT(bank_pin_num);
> +	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
> +
> +	/* configure the output enable reg for the pin */
> +	reg = readl(ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
> +	reg |= BIT(bank_pin_num);
> +	writel(reg, ZYNQ_GPIO_BASE_ADDRESS + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
> +
> +	/* set the state of the pin */
> +	gpio_set_value(gpio, value);
> +	return 0;
> +}
> +
> +/**
> + * Request a gpio before using it.
> + *
> + * NOTE: Argument 'label' is unused.
> + */
> +int gpio_request(unsigned gpio, const char *label)
> +{
> +	if (check_gpio(gpio) < 0)
> +		return -1;
> +
> +	return 0;
> +}
> +
> +/**
> + * Reset and free the gpio after using it.
> + */
> +int gpio_free(unsigned gpio)
> +{
> +	return 0;
> +}
> 

Looks good to me.
Tested-by: Michal Simek <michal.simek@xilinx.com>

I will add this to zynq custodian tree.

Thanks,
Michal