* [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
@ 2021-05-26 6:55 Jingwen Chen
2021-05-26 7:14 ` Deng, Emily
2021-05-26 7:24 ` Liu, Monk
0 siblings, 2 replies; 4+ messages in thread
From: Jingwen Chen @ 2021-05-26 6:55 UTC (permalink / raw)
To: amd-gfx; +Cc: Jingwen Chen, Victor Zhao, monk.liu
From: Victor Zhao <Victor.Zhao@amd.com>
save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
MP0_SMN_C2PMSG_102 reg
Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 ++-
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..20e06b3ec686 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2701,6 +2701,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
/* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
psp_ring_set_wptr(psp, psp_write_ptr_reg);
+ ring->ring_wptr = psp_write_ptr_reg;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 46a5328e00e0..60aa99a39a74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -76,6 +76,7 @@ struct psp_ring
uint64_t ring_mem_mc_addr;
void *ring_mem_handle;
uint32_t ring_size;
+ uint32_t ring_wptr;
};
/* More registers may will be supported */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1f2e7e35c91e..4a32b0c84ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -474,6 +474,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
return ret;
}
+ ring->ring_wptr = 0;
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
@@ -733,7 +734,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f2e725f72d2f..160f78eb6403 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -237,6 +237,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
return ret;
}
+ ring->ring_wptr = 0;
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
@@ -379,7 +380,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
return data;
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
2021-05-26 6:55 [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack Jingwen Chen
@ 2021-05-26 7:14 ` Deng, Emily
2021-05-26 7:24 ` Liu, Monk
1 sibling, 0 replies; 4+ messages in thread
From: Deng, Emily @ 2021-05-26 7:14 UTC (permalink / raw)
To: Chen, JingWen, amd-gfx; +Cc: Chen, JingWen, Zhao, Victor, Liu, Monk
[AMD Official Use Only]
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Jingwen
>Chen
>Sent: Wednesday, May 26, 2021 2:55 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Chen, JingWen <JingWen.Chen2@amd.com>; Zhao, Victor
><Victor.Zhao@amd.com>; Liu, Monk <Monk.Liu@amd.com>
>Subject: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
>
>From: Victor Zhao <Victor.Zhao@amd.com>
>
>save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
>MP0_SMN_C2PMSG_102 reg
>
>Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
>Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
>Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
>drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 +
>drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 ++-
> 4 files changed, 6 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>index 55378c6b9722..20e06b3ec686 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>@@ -2701,6 +2701,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
> /* Update the write Pointer in DWORDs */
> psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) %
>ring_size_dw;
> psp_ring_set_wptr(psp, psp_write_ptr_reg);
>+ ring->ring_wptr = psp_write_ptr_reg;
> return 0;
> }
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>index 46a5328e00e0..60aa99a39a74 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>@@ -76,6 +76,7 @@ struct psp_ring
> uint64_t ring_mem_mc_addr;
> void *ring_mem_handle;
> uint32_t ring_size;
>+ uint32_t ring_wptr;
> };
>
> /* More registers may will be supported */ diff --git
>a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>index 1f2e7e35c91e..4a32b0c84ef4 100644
>--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>@@ -474,6 +474,7 @@ static int psp_v11_0_ring_create(struct psp_context
>*psp,
> return ret;
> }
>
>+ ring->ring_wptr = 0;
> /* Write low address of the ring to C2PMSG_102 */
> psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102,
>psp_ring_reg); @@ -733,7 +734,7 @@ static uint32_t
>psp_v11_0_ring_get_wptr(struct psp_context *psp)
> struct amdgpu_device *adev = psp->adev;
>
> if (amdgpu_sriov_vf(adev))
>- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
>+ data = psp->km_ring.ring_wptr;
> else
> data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>index f2e725f72d2f..160f78eb6403 100644
>--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>@@ -237,6 +237,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
> return ret;
> }
>
>+ ring->ring_wptr = 0;
> /* Write low address of the ring to C2PMSG_102 */
> psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102,
>psp_ring_reg); @@ -379,7 +380,7 @@ static uint32_t
>psp_v3_1_ring_get_wptr(struct psp_context *psp)
> struct amdgpu_device *adev = psp->adev;
>
> if (amdgpu_sriov_vf(adev))
>- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
>+ data = psp->km_ring.ring_wptr;
> else
> data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
> return data;
>--
>2.25.1
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
2021-05-26 6:55 [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack Jingwen Chen
2021-05-26 7:14 ` Deng, Emily
@ 2021-05-26 7:24 ` Liu, Monk
2021-05-26 7:43 ` Chen, JingWen
1 sibling, 1 reply; 4+ messages in thread
From: Liu, Monk @ 2021-05-26 7:24 UTC (permalink / raw)
To: Chen, JingWen, amd-gfx; +Cc: Chen, JingWen, Zhao, Victor
[AMD Official Use Only]
>>+ ring->ring_wptr = psp_write_ptr_reg;
Put the cache mechanism into the callbacks please
>>+ ring->ring_wptr = 0;
It is not needed
At last, try to put more details in the comment to let people know why we need this PSP WPTR cache mechanism
Thanks
------------------------------------------
Monk Liu | Cloud-GPU Core team
------------------------------------------
-----Original Message-----
From: Jingwen Chen <Jingwen.Chen2@amd.com>
Sent: Wednesday, May 26, 2021 2:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>; Zhao, Victor <Victor.Zhao@amd.com>; Chen, JingWen <JingWen.Chen2@amd.com>
Subject: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
From: Victor Zhao <Victor.Zhao@amd.com>
save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
MP0_SMN_C2PMSG_102 reg
Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 ++-
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..20e06b3ec686 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2701,6 +2701,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
/* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
psp_ring_set_wptr(psp, psp_write_ptr_reg);
+ ring->ring_wptr = psp_write_ptr_reg;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 46a5328e00e0..60aa99a39a74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -76,6 +76,7 @@ struct psp_ring
uint64_t ring_mem_mc_addr;
void *ring_mem_handle;
uint32_t ring_size;
+ uint32_t ring_wptr;
};
/* More registers may will be supported */ diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1f2e7e35c91e..4a32b0c84ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -474,6 +474,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
return ret;
}
+ ring->ring_wptr = 0;
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); @@ -733,7 +734,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f2e725f72d2f..160f78eb6403 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -237,6 +237,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
return ret;
}
+ ring->ring_wptr = 0;
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); @@ -379,7 +380,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
return data;
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
2021-05-26 7:24 ` Liu, Monk
@ 2021-05-26 7:43 ` Chen, JingWen
0 siblings, 0 replies; 4+ messages in thread
From: Chen, JingWen @ 2021-05-26 7:43 UTC (permalink / raw)
To: Liu, Monk, amd-gfx; +Cc: Deng, Emily, Zhao, Victor
Hi Monk,
New patch submitted according to your suggestion
Best Regards,
JingWen Chen
-----Original Message-----
From: Liu, Monk <Monk.Liu@amd.com>
Sent: Wednesday, May 26, 2021 3:24 PM
To: Chen, JingWen <JingWen.Chen2@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Zhao, Victor <Victor.Zhao@amd.com>; Chen, JingWen <JingWen.Chen2@amd.com>
Subject: RE: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
[AMD Official Use Only]
>>+ ring->ring_wptr = psp_write_ptr_reg;
Put the cache mechanism into the callbacks please
>>+ ring->ring_wptr = 0;
It is not needed
At last, try to put more details in the comment to let people know why we need this PSP WPTR cache mechanism
Thanks
------------------------------------------
Monk Liu | Cloud-GPU Core team
------------------------------------------
-----Original Message-----
From: Jingwen Chen <Jingwen.Chen2@amd.com>
Sent: Wednesday, May 26, 2021 2:55 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>; Zhao, Victor <Victor.Zhao@amd.com>; Chen, JingWen <JingWen.Chen2@amd.com>
Subject: [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack
From: Victor Zhao <Victor.Zhao@amd.com>
save psp ring wptr in SRIOV to avoid attack to avoid extra changes to
MP0_SMN_C2PMSG_102 reg
Change-Id: Idee78e8c1c781463048f2f6311fdc70488ef05b2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 3 ++-
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 55378c6b9722..20e06b3ec686 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -2701,6 +2701,7 @@ int psp_ring_cmd_submit(struct psp_context *psp,
/* Update the write Pointer in DWORDs */
psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
psp_ring_set_wptr(psp, psp_write_ptr_reg);
+ ring->ring_wptr = psp_write_ptr_reg;
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 46a5328e00e0..60aa99a39a74 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -76,6 +76,7 @@ struct psp_ring
uint64_t ring_mem_mc_addr;
void *ring_mem_handle;
uint32_t ring_size;
+ uint32_t ring_wptr;
};
/* More registers may will be supported */ diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1f2e7e35c91e..4a32b0c84ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -474,6 +474,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
return ret;
}
+ ring->ring_wptr = 0;
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); @@ -733,7 +734,7 @@ static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f2e725f72d2f..160f78eb6403 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -237,6 +237,7 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
return ret;
}
+ ring->ring_wptr = 0;
/* Write low address of the ring to C2PMSG_102 */
psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); @@ -379,7 +380,7 @@ static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp)
struct amdgpu_device *adev = psp->adev;
if (amdgpu_sriov_vf(adev))
- data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ data = psp->km_ring.ring_wptr;
else
data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
return data;
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-05-26 7:43 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-26 6:55 [PATCH] drm/amd/amdgpu:save psp ring wptr in SRIOV to avoid attack Jingwen Chen
2021-05-26 7:14 ` Deng, Emily
2021-05-26 7:24 ` Liu, Monk
2021-05-26 7:43 ` Chen, JingWen
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