[PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for vega10.

[PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for vega10.

[Rex Zhu]

clean up code in vega10_thermal.c

Change-Id: I2eb0b6c9afa4fa23d31b4dfed317689623fcbcda
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   | 49 ++++++++--------------
 1 file changed, 17 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
index 7bb4e46..1bc39ec 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
@@ -144,21 +144,13 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 				(cgs_read_register(hwmgr->device, reg) &
 				CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >>
 				CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
-		hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
-				CG_FDO_CTRL2__TMIN_MASK) >>
-				CG_FDO_CTRL2__TMIN__SHIFT;
 		hwmgr->fan_ctrl_is_in_default_mode = false;
 	}
 
 	cgs_write_register(hwmgr->device, reg,
 			(cgs_read_register(hwmgr->device, reg) &
-			~CG_FDO_CTRL2__TMIN_MASK) |
-			(0 << CG_FDO_CTRL2__TMIN__SHIFT));
-	cgs_write_register(hwmgr->device, reg,
-			(cgs_read_register(hwmgr->device, reg) &
 			~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
 			(mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
-
 	return 0;
 }
 
@@ -170,20 +162,18 @@ int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
 int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
 {
 	uint32_t reg;
+	uint32_t ctrl;
 
 	reg = soc15_get_register_offset(THM_HWID, 0,
 			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
 
 	if (!hwmgr->fan_ctrl_is_in_default_mode) {
-		cgs_write_register(hwmgr->device, reg,
-				(cgs_read_register(hwmgr->device, reg) &
-				~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
-				(hwmgr->fan_ctrl_default_mode <<
-				CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
-		cgs_write_register(hwmgr->device, reg,
-				(cgs_read_register(hwmgr->device, reg) &
-				~CG_FDO_CTRL2__TMIN_MASK) |
-				(hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
+		ctrl = cgs_read_register(hwmgr->device, reg);
+		ctrl = ctrl & (~(CG_FDO_CTRL2__FDO_PWM_MODE_MASK));
+		ctrl = ctrl | (hwmgr->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
+		ctrl = ctrl & (~(CG_FDO_CTRL2__TMIN_MASK));
+		ctrl = ctrl | (hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT);
+		cgs_write_register(hwmgr->device, reg, ctrl);
 		hwmgr->fan_ctrl_is_in_default_mode = true;
 	}
 
@@ -325,9 +315,9 @@ int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
 				FDO_PWM_MODE_STATIC);
 		if (!result)
 			result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
-	} else
+	} else {
 		result = vega10_fan_ctrl_set_default_mode(hwmgr);
-
+	}
 	return result;
 }
 
@@ -404,15 +394,10 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 {
 	uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-	uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
+	uint32_t high = 89 *
 			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
 	uint32_t val, reg;
 
-	if (low < range->min)
-		low = range->min;
-	if (high > range->max)
-		high = range->max;
-
 	if (low > high)
 		return -EINVAL;
 
@@ -420,7 +405,6 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 			mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
 
 	val = cgs_read_register(hwmgr->device, reg);
-
 	val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
 	val |=  (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
 
@@ -450,24 +434,25 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
 static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
 {
 	uint32_t reg;
+	uint32_t tmp;
 
 	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
 		reg = soc15_get_register_offset(THM_HWID, 0,
 				mmCG_TACH_CTRL_BASE_IDX, mmCG_TACH_CTRL);
-		cgs_write_register(hwmgr->device, reg,
-				(cgs_read_register(hwmgr->device, reg) &
+		tmp = (cgs_read_register(hwmgr->device, reg) &
 				~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
 				((hwmgr->thermal_controller.fanInfo.
 				ucTachometerPulsesPerRevolution - 1) <<
-				CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
+				CG_TACH_CTRL__EDGE_PER_REV__SHIFT);
+		cgs_write_register(hwmgr->device, reg, tmp);
 	}
 
 	reg = soc15_get_register_offset(THM_HWID, 0,
 			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
-	cgs_write_register(hwmgr->device, reg,
-			(cgs_read_register(hwmgr->device, reg) &
+	tmp = (cgs_read_register(hwmgr->device, reg) &
 			~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK) |
-			(0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
+			(0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT);
+	cgs_write_register(hwmgr->device, reg, tmp);
 
 	return 0;
 }
-- 
1.9.1

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[PATCH 2/4] drm/amd/powerplay: Add floor DCEF for DS on boot.

[Rex Zhu]

Change-Id: I2385a3695ce28139e51088d2eacae299aaf476aa
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 31 +++++++++++++++++++++-
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h |  3 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  4 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 +
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index 5602311..1ba05cc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -388,11 +388,33 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
+{
+	struct atom_get_smu_clock_info_parameters_v3_1   parameters;
+	struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
+	uint32_t ix;
+
+	parameters.clk_id = id;
+	parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+
+	ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);
+	if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, &parameters)) {
+		output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;
+		*frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
+	} else {
+		pr_info("Error execute_table getsmuclockinfo!");
+		return -1;
+	}
+
+	return 0;
+}
+
 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 			struct pp_atomfwctrl_bios_boot_up_values *boot_values)
 {
 	struct atom_firmware_info_v3_1 *info = NULL;
 	uint16_t ix;
+	uint32_t frequency = 0;
 
 	ix = GetIndexIntoMasterDataTable(firmwareinfo);
 	info = (struct atom_firmware_info_v3_1 *)
@@ -407,11 +429,18 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
 	boot_values->ulRevision = info->firmware_revision;
 	boot_values->ulGfxClk   = info->bootup_sclk_in10khz;
 	boot_values->ulUClk     = info->bootup_mclk_in10khz;
-	boot_values->ulSocClk   = 0;
 	boot_values->usVddc     = info->bootup_vddc_mv;
 	boot_values->usVddci    = info->bootup_vddci_mv;
 	boot_values->usMvddc    = info->bootup_mvddc_mv;
 	boot_values->usVddGfx   = info->bootup_vddgfx_mv;
+	boot_values->ulSocClk   = 0;
+	boot_values->ulDCEFClk   = 0;
+
+	if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency))
+		boot_values->ulSocClk   = frequency;
+
+	if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
+		boot_values->ulDCEFClk   = frequency;
 
 	return 0;
 }
\ No newline at end of file
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
index 43a6711..81908b5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
@@ -26,6 +26,8 @@
 
 #include "hwmgr.h"
 
+typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
+
 #define GetIndexIntoMasterCmdTable(FieldName) \
 	(((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
 #define GetIndexIntoMasterDataTable(FieldName) \
@@ -125,6 +127,7 @@ struct pp_atomfwctrl_bios_boot_up_values {
 	uint32_t   ulGfxClk;
 	uint32_t   ulUClk;
 	uint32_t   ulSocClk;
+	uint32_t   ulDCEFClk;
 	uint16_t   usVddc;
 	uint16_t   usVddci;
 	uint16_t   usMvddc;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index a50a6ef..30bc053 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2451,6 +2451,7 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
 		data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 		data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 		data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
+		data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 		if (0 != boot_up_values.usVddc) {
 			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 						PPSMC_MSG_SetFloorSocVoltage,
@@ -2459,6 +2460,9 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
 		} else {
 			data->vbios_boot_state.bsoc_vddc_lock = false;
 		}
+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+				PPSMC_MSG_SetMinDeepSleepDcefclk,
+			(uint32_t)(data->vbios_boot_state.dcef_clock / 100));
 	}
 
 	result = vega10_populate_avfs_parameters(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 1d7dbad..6e5c5b9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -185,6 +185,7 @@ struct vega10_vbios_boot_state {
 	uint32_t    gfx_clock;
 	uint32_t    mem_clock;
 	uint32_t    soc_clock;
+	uint32_t    dcef_clock;
 };
 
 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
-- 
1.9.1

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[PATCH 3/4] drm/amd/powerplay: Align with VBIOS to support AVFS parameters.

[Rex Zhu]

Change-Id: I2a98edd3fb4c5b83520df772ebd61a962c73e5ca
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/include/atomfirmware.h         | 12 ++++++------
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 12 ++++++------
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  4 ++--
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h
index d386875..0021a1c 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1206,10 +1206,10 @@ struct  atom_asic_profiling_info_v4_1
   uint32_t  gb_vdroop_table_ckson_a1;
   uint32_t  gb_vdroop_table_ckson_a2;
   uint32_t  avfsgb_fuse_table_cksoff_m1;
-  uint16_t  avfsgb_fuse_table_cksoff_m2;
+  uint32_t  avfsgb_fuse_table_cksoff_m2;
   uint32_t  avfsgb_fuse_table_cksoff_b;
   uint32_t  avfsgb_fuse_table_ckson_m1;	
-  uint16_t  avfsgb_fuse_table_ckson_m2;
+  uint32_t  avfsgb_fuse_table_ckson_m2;
   uint32_t  avfsgb_fuse_table_ckson_b;
   uint16_t  max_voltage_0_25mv;
   uint8_t   enable_gb_vdroop_table_cksoff;
@@ -1220,16 +1220,16 @@ struct  atom_asic_profiling_info_v4_1
   uint8_t   enable_apply_avfs_cksoff_voltage;
   uint8_t   reserved;
   uint32_t  dispclk2gfxclk_a;
-  uint16_t  dispclk2gfxclk_b;
+  uint32_t  dispclk2gfxclk_b;
   uint32_t  dispclk2gfxclk_c;
   uint32_t  pixclk2gfxclk_a;
-  uint16_t  pixclk2gfxclk_b;
+  uint32_t  pixclk2gfxclk_b;
   uint32_t  pixclk2gfxclk_c;
   uint32_t  dcefclk2gfxclk_a;
-  uint16_t  dcefclk2gfxclk_b;
+  uint32_t  dcefclk2gfxclk_b;
   uint32_t  dcefclk2gfxclk_c;
   uint32_t  phyclk2gfxclk_a;
-  uint16_t  phyclk2gfxclk_b;
+  uint32_t  phyclk2gfxclk_b;
   uint32_t  phyclk2gfxclk_c;
 };
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
index 1ba05cc..720d500 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
@@ -315,13 +315,13 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 	param->ulGbFuseTableCksoffM1 =
 			le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m1);
 	param->ulGbFuseTableCksoffM2 =
-			le16_to_cpu(profile->avfsgb_fuse_table_cksoff_m2);
+			le32_to_cpu(profile->avfsgb_fuse_table_cksoff_m2);
 	param->ulGbFuseTableCksoffB =
 			le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b);
 	param->ulGbFuseTableCksonM1 =
 			le32_to_cpu(profile->avfsgb_fuse_table_ckson_m1);
 	param->ulGbFuseTableCksonM2 =
-			le16_to_cpu(profile->avfsgb_fuse_table_ckson_m2);
+			le32_to_cpu(profile->avfsgb_fuse_table_ckson_m2);
 	param->ulGbFuseTableCksonB =
 			le32_to_cpu(profile->avfsgb_fuse_table_ckson_b);
 
@@ -335,25 +335,25 @@ int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
 	param->ulDispclk2GfxclkM1 =
 			le32_to_cpu(profile->dispclk2gfxclk_a);
 	param->ulDispclk2GfxclkM2 =
-			le16_to_cpu(profile->dispclk2gfxclk_b);
+			le32_to_cpu(profile->dispclk2gfxclk_b);
 	param->ulDispclk2GfxclkB =
 			le32_to_cpu(profile->dispclk2gfxclk_c);
 	param->ulDcefclk2GfxclkM1 =
 			le32_to_cpu(profile->dcefclk2gfxclk_a);
 	param->ulDcefclk2GfxclkM2 =
-			le16_to_cpu(profile->dcefclk2gfxclk_b);
+			le32_to_cpu(profile->dcefclk2gfxclk_b);
 	param->ulDcefclk2GfxclkB =
 			le32_to_cpu(profile->dcefclk2gfxclk_c);
 	param->ulPixelclk2GfxclkM1 =
 			le32_to_cpu(profile->pixclk2gfxclk_a);
 	param->ulPixelclk2GfxclkM2 =
-			le16_to_cpu(profile->pixclk2gfxclk_b);
+			le32_to_cpu(profile->pixclk2gfxclk_b);
 	param->ulPixelclk2GfxclkB =
 			le32_to_cpu(profile->pixclk2gfxclk_c);
 	param->ulPhyclk2GfxclkM1 =
 			le32_to_cpu(profile->phyclk2gfxclk_a);
 	param->ulPhyclk2GfxclkM2 =
-			le16_to_cpu(profile->phyclk2gfxclk_b);
+			le32_to_cpu(profile->phyclk2gfxclk_b);
 	param->ulPhyclk2GfxclkB =
 			le32_to_cpu(profile->phyclk2gfxclk_c);
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 30bc053..971f789 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -2097,7 +2097,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
 			pp_table->AvfsGbCksOn.m1 =
 					cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
 			pp_table->AvfsGbCksOn.m2 =
-					cpu_to_le16(avfs_params.ulGbFuseTableCksonM2);
+					cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
 			pp_table->AvfsGbCksOn.b =
 					cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
 			pp_table->AvfsGbCksOn.m1_shift = 24;
@@ -2109,7 +2109,7 @@ static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
 			pp_table->AvfsGbCksOff.m1 =
 					cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
 			pp_table->AvfsGbCksOff.m2 =
-					cpu_to_le16(avfs_params.ulGbFuseTableCksoffM2);
+					cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
 			pp_table->AvfsGbCksOff.b =
 					cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
 			pp_table->AvfsGbCksOff.m1_shift = 24;
-- 
1.9.1

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[PATCH 4/4] drm/amd/powerplay: enable CKS by default on vega10.

[Rex Zhu]

Change-Id: I0e41ec0fb9987c73bd38a7eaf8173b5ec5c50734
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 971f789..43812d2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -124,7 +124,7 @@ static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
 	}
 
 	data->registry_data.clock_stretcher_support =
-			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? false : true;
+			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
 
 	data->registry_data.ulv_support =
 			hwmgr->feature_mask & PP_ULV_MASK ? true : false;
-- 
1.9.1

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RE: [PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for vega10.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 1/4] drm/amd/powerplay: hardcode temp range to 0-89 for
> vega10.
> 
> clean up code in vega10_thermal.c

Please split this into 2 patches, one to clean up the code, one to make the change for the temp range.  For the temp range change, would it be better to change the current define to 89 rather than just hardcoding it as a magic number?

Alex

> 
> Change-Id: I2eb0b6c9afa4fa23d31b4dfed317689623fcbcda
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c   | 49 ++++++++-----
> ---------
>  1 file changed, 17 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> index 7bb4e46..1bc39ec 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> @@ -144,21 +144,13 @@ int vega10_fan_ctrl_set_static_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
>  				(cgs_read_register(hwmgr->device, reg) &
>  				CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
> >>
> 
> 	CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
> -		hwmgr->tmin = (cgs_read_register(hwmgr->device, reg) &
> -				CG_FDO_CTRL2__TMIN_MASK) >>
> -				CG_FDO_CTRL2__TMIN__SHIFT;
>  		hwmgr->fan_ctrl_is_in_default_mode = false;
>  	}
> 
>  	cgs_write_register(hwmgr->device, reg,
>  			(cgs_read_register(hwmgr->device, reg) &
> -			~CG_FDO_CTRL2__TMIN_MASK) |
> -			(0 << CG_FDO_CTRL2__TMIN__SHIFT));
> -	cgs_write_register(hwmgr->device, reg,
> -			(cgs_read_register(hwmgr->device, reg) &
>  			~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
>  			(mode <<
> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
> -
>  	return 0;
>  }
> 
> @@ -170,20 +162,18 @@ int vega10_fan_ctrl_set_static_mode(struct
> pp_hwmgr *hwmgr, uint32_t mode)
>  int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
>  {
>  	uint32_t reg;
> +	uint32_t ctrl;
> 
>  	reg = soc15_get_register_offset(THM_HWID, 0,
>  			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
> 
>  	if (!hwmgr->fan_ctrl_is_in_default_mode) {
> -		cgs_write_register(hwmgr->device, reg,
> -				(cgs_read_register(hwmgr->device, reg) &
> -
> 	~CG_FDO_CTRL2__FDO_PWM_MODE_MASK) |
> -				(hwmgr->fan_ctrl_default_mode <<
> -
> 	CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT));
> -		cgs_write_register(hwmgr->device, reg,
> -				(cgs_read_register(hwmgr->device, reg) &
> -				~CG_FDO_CTRL2__TMIN_MASK) |
> -				(hwmgr->tmin <<
> CG_FDO_CTRL2__TMIN__SHIFT));
> +		ctrl = cgs_read_register(hwmgr->device, reg);
> +		ctrl = ctrl & (~(CG_FDO_CTRL2__FDO_PWM_MODE_MASK));
> +		ctrl = ctrl | (hwmgr->fan_ctrl_default_mode <<
> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT);
> +		ctrl = ctrl & (~(CG_FDO_CTRL2__TMIN_MASK));
> +		ctrl = ctrl | (hwmgr->tmin <<
> CG_FDO_CTRL2__TMIN__SHIFT);
> +		cgs_write_register(hwmgr->device, reg, ctrl);
>  		hwmgr->fan_ctrl_is_in_default_mode = true;
>  	}
> 
> @@ -325,9 +315,9 @@ int
> vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
>  				FDO_PWM_MODE_STATIC);
>  		if (!result)
>  			result =
> vega10_fan_ctrl_start_smc_fan_control(hwmgr);
> -	} else
> +	} else {
>  		result = vega10_fan_ctrl_set_default_mode(hwmgr);
> -
> +	}
>  	return result;
>  }
> 
> @@ -404,15 +394,10 @@ static int
> vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
>  {
>  	uint32_t low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
>  			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
> -	uint32_t high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
> +	uint32_t high = 89 *
>  			PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
>  	uint32_t val, reg;
> 
> -	if (low < range->min)
> -		low = range->min;
> -	if (high > range->max)
> -		high = range->max;
> -
>  	if (low > high)
>  		return -EINVAL;
> 
> @@ -420,7 +405,6 @@ static int
> vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
>  			mmTHM_THERMAL_INT_CTRL_BASE_IDX,
> mmTHM_THERMAL_INT_CTRL);
> 
>  	val = cgs_read_register(hwmgr->device, reg);
> -
>  	val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
>  	val |=  (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
> 
> @@ -450,24 +434,25 @@ static int
> vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
>  static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
>  {
>  	uint32_t reg;
> +	uint32_t tmp;
> 
>  	if (hwmgr-
> >thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
>  		reg = soc15_get_register_offset(THM_HWID, 0,
>  				mmCG_TACH_CTRL_BASE_IDX,
> mmCG_TACH_CTRL);
> -		cgs_write_register(hwmgr->device, reg,
> -				(cgs_read_register(hwmgr->device, reg) &
> +		tmp = (cgs_read_register(hwmgr->device, reg) &
>  				~CG_TACH_CTRL__EDGE_PER_REV_MASK) |
>  				((hwmgr->thermal_controller.fanInfo.
>  				ucTachometerPulsesPerRevolution - 1) <<
> -				CG_TACH_CTRL__EDGE_PER_REV__SHIFT));
> +				CG_TACH_CTRL__EDGE_PER_REV__SHIFT);
> +		cgs_write_register(hwmgr->device, reg, tmp);
>  	}
> 
>  	reg = soc15_get_register_offset(THM_HWID, 0,
>  			mmCG_FDO_CTRL2_BASE_IDX, mmCG_FDO_CTRL2);
> -	cgs_write_register(hwmgr->device, reg,
> -			(cgs_read_register(hwmgr->device, reg) &
> +	tmp = (cgs_read_register(hwmgr->device, reg) &
>  			~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK)
> |
> -			(0x28 <<
> CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT));
> +			(0x28 <<
> CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT);
> +	cgs_write_register(hwmgr->device, reg, tmp);
> 
>  	return 0;
>  }
> --
> 1.9.1
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/4] drm/amd/powerplay: Add floor DCEF for DS on boot.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/4] drm/amd/powerplay: Add floor DCEF for DS on boot.
> 
> Change-Id: I2385a3695ce28139e51088d2eacae299aaf476aa
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Please include a better patch description.  Something like:
"Use the vbios to look up the default frequencies for socclk and dcefclk."
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 31
> +++++++++++++++++++++-
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h |  3 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  4 +++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |  1 +
>  4 files changed, 38 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> index 5602311..1ba05cc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> @@ -388,11 +388,33 @@ int pp_atomfwctrl_get_gpio_information(struct
> pp_hwmgr *hwmgr,
>  	return 0;
>  }
> 
> +int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr
> *hwmgr, BIOS_CLKID id, uint32_t *frequency)
> +{
> +	struct atom_get_smu_clock_info_parameters_v3_1   parameters;
> +	struct atom_get_smu_clock_info_output_parameters_v3_1
> *output;
> +	uint32_t ix;
> +
> +	parameters.clk_id = id;
> +	parameters.command =
> GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
> +
> +	ix = GetIndexIntoMasterCmdTable(getsmuclockinfo);
> +	if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, &parameters)) {
> +		output = (struct
> atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters;
> +		*frequency = output-
> >atom_smu_outputclkfreq.smu_clock_freq_hz / 10000;
> +	} else {
> +		pr_info("Error execute_table getsmuclockinfo!");
> +		return -1;
> +	}
> +
> +	return 0;
> +}
> +
>  int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
>  			struct pp_atomfwctrl_bios_boot_up_values
> *boot_values)
>  {
>  	struct atom_firmware_info_v3_1 *info = NULL;
>  	uint16_t ix;
> +	uint32_t frequency = 0;
> 
>  	ix = GetIndexIntoMasterDataTable(firmwareinfo);
>  	info = (struct atom_firmware_info_v3_1 *)
> @@ -407,11 +429,18 @@ int
> pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
>  	boot_values->ulRevision = info->firmware_revision;
>  	boot_values->ulGfxClk   = info->bootup_sclk_in10khz;
>  	boot_values->ulUClk     = info->bootup_mclk_in10khz;
> -	boot_values->ulSocClk   = 0;
>  	boot_values->usVddc     = info->bootup_vddc_mv;
>  	boot_values->usVddci    = info->bootup_vddci_mv;
>  	boot_values->usMvddc    = info->bootup_mvddc_mv;
>  	boot_values->usVddGfx   = info->bootup_vddgfx_mv;
> +	boot_values->ulSocClk   = 0;
> +	boot_values->ulDCEFClk   = 0;
> +
> +	if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr,
> SMU9_SYSPLL0_SOCCLK_ID, &frequency))
> +		boot_values->ulSocClk   = frequency;
> +
> +	if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr,
> SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
> +		boot_values->ulDCEFClk   = frequency;
> 
>  	return 0;
>  }
> \ No newline at end of file
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> index 43a6711..81908b5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> @@ -26,6 +26,8 @@
> 
>  #include "hwmgr.h"
> 
> +typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
> +
>  #define GetIndexIntoMasterCmdTable(FieldName) \
>  	(((char*)(&((struct
> atom_master_list_of_command_functions_v2_1*)0)->FieldName)-
> (char*)0)/sizeof(uint16_t))
>  #define GetIndexIntoMasterDataTable(FieldName) \
> @@ -125,6 +127,7 @@ struct pp_atomfwctrl_bios_boot_up_values {
>  	uint32_t   ulGfxClk;
>  	uint32_t   ulUClk;
>  	uint32_t   ulSocClk;
> +	uint32_t   ulDCEFClk;
>  	uint16_t   usVddc;
>  	uint16_t   usVddci;
>  	uint16_t   usMvddc;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index a50a6ef..30bc053 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2451,6 +2451,7 @@ static int vega10_init_smc_table(struct pp_hwmgr
> *hwmgr)
>  		data->vbios_boot_state.gfx_clock =
> boot_up_values.ulGfxClk;
>  		data->vbios_boot_state.mem_clock =
> boot_up_values.ulUClk;
>  		data->vbios_boot_state.soc_clock =
> boot_up_values.ulSocClk;
> +		data->vbios_boot_state.dcef_clock =
> boot_up_values.ulDCEFClk;
>  		if (0 != boot_up_values.usVddc) {
>  			smum_send_msg_to_smc_with_parameter(hwmgr-
> >smumgr,
> 
> 	PPSMC_MSG_SetFloorSocVoltage,
> @@ -2459,6 +2460,9 @@ static int vega10_init_smc_table(struct pp_hwmgr
> *hwmgr)
>  		} else {
>  			data->vbios_boot_state.bsoc_vddc_lock = false;
>  		}
> +		smum_send_msg_to_smc_with_parameter(hwmgr-
> >smumgr,
> +				PPSMC_MSG_SetMinDeepSleepDcefclk,
> +			(uint32_t)(data->vbios_boot_state.dcef_clock /
> 100));
>  	}
> 
>  	result = vega10_populate_avfs_parameters(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 1d7dbad..6e5c5b9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -185,6 +185,7 @@ struct vega10_vbios_boot_state {
>  	uint32_t    gfx_clock;
>  	uint32_t    mem_clock;
>  	uint32_t    soc_clock;
> +	uint32_t    dcef_clock;
>  };
> 
>  #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 3/4] drm/amd/powerplay: Align with VBIOS to support AVFS parameters.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/4] drm/amd/powerplay: Align with VBIOS to support AVFS
> parameters.
> 
> Change-Id: I2a98edd3fb4c5b83520df772ebd61a962c73e5ca
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/include/atomfirmware.h         | 12 ++++++------
>  drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 12 ++++++------
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |  4 ++--
>  3 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h
> b/drivers/gpu/drm/amd/include/atomfirmware.h
> index d386875..0021a1c 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -1206,10 +1206,10 @@ struct  atom_asic_profiling_info_v4_1
>    uint32_t  gb_vdroop_table_ckson_a1;
>    uint32_t  gb_vdroop_table_ckson_a2;
>    uint32_t  avfsgb_fuse_table_cksoff_m1;
> -  uint16_t  avfsgb_fuse_table_cksoff_m2;
> +  uint32_t  avfsgb_fuse_table_cksoff_m2;
>    uint32_t  avfsgb_fuse_table_cksoff_b;
>    uint32_t  avfsgb_fuse_table_ckson_m1;
> -  uint16_t  avfsgb_fuse_table_ckson_m2;
> +  uint32_t  avfsgb_fuse_table_ckson_m2;
>    uint32_t  avfsgb_fuse_table_ckson_b;
>    uint16_t  max_voltage_0_25mv;
>    uint8_t   enable_gb_vdroop_table_cksoff;
> @@ -1220,16 +1220,16 @@ struct  atom_asic_profiling_info_v4_1
>    uint8_t   enable_apply_avfs_cksoff_voltage;
>    uint8_t   reserved;
>    uint32_t  dispclk2gfxclk_a;
> -  uint16_t  dispclk2gfxclk_b;
> +  uint32_t  dispclk2gfxclk_b;
>    uint32_t  dispclk2gfxclk_c;
>    uint32_t  pixclk2gfxclk_a;
> -  uint16_t  pixclk2gfxclk_b;
> +  uint32_t  pixclk2gfxclk_b;
>    uint32_t  pixclk2gfxclk_c;
>    uint32_t  dcefclk2gfxclk_a;
> -  uint16_t  dcefclk2gfxclk_b;
> +  uint32_t  dcefclk2gfxclk_b;
>    uint32_t  dcefclk2gfxclk_c;
>    uint32_t  phyclk2gfxclk_a;
> -  uint16_t  phyclk2gfxclk_b;
> +  uint32_t  phyclk2gfxclk_b;
>    uint32_t  phyclk2gfxclk_c;
>  };
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> index 1ba05cc..720d500 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> @@ -315,13 +315,13 @@ int pp_atomfwctrl_get_avfs_information(struct
> pp_hwmgr *hwmgr,
>  	param->ulGbFuseTableCksoffM1 =
>  			le32_to_cpu(profile-
> >avfsgb_fuse_table_cksoff_m1);
>  	param->ulGbFuseTableCksoffM2 =
> -			le16_to_cpu(profile-
> >avfsgb_fuse_table_cksoff_m2);
> +			le32_to_cpu(profile-
> >avfsgb_fuse_table_cksoff_m2);
>  	param->ulGbFuseTableCksoffB =
>  			le32_to_cpu(profile->avfsgb_fuse_table_cksoff_b);
>  	param->ulGbFuseTableCksonM1 =
>  			le32_to_cpu(profile-
> >avfsgb_fuse_table_ckson_m1);
>  	param->ulGbFuseTableCksonM2 =
> -			le16_to_cpu(profile-
> >avfsgb_fuse_table_ckson_m2);
> +			le32_to_cpu(profile-
> >avfsgb_fuse_table_ckson_m2);
>  	param->ulGbFuseTableCksonB =
>  			le32_to_cpu(profile->avfsgb_fuse_table_ckson_b);
> 
> @@ -335,25 +335,25 @@ int pp_atomfwctrl_get_avfs_information(struct
> pp_hwmgr *hwmgr,
>  	param->ulDispclk2GfxclkM1 =
>  			le32_to_cpu(profile->dispclk2gfxclk_a);
>  	param->ulDispclk2GfxclkM2 =
> -			le16_to_cpu(profile->dispclk2gfxclk_b);
> +			le32_to_cpu(profile->dispclk2gfxclk_b);
>  	param->ulDispclk2GfxclkB =
>  			le32_to_cpu(profile->dispclk2gfxclk_c);
>  	param->ulDcefclk2GfxclkM1 =
>  			le32_to_cpu(profile->dcefclk2gfxclk_a);
>  	param->ulDcefclk2GfxclkM2 =
> -			le16_to_cpu(profile->dcefclk2gfxclk_b);
> +			le32_to_cpu(profile->dcefclk2gfxclk_b);
>  	param->ulDcefclk2GfxclkB =
>  			le32_to_cpu(profile->dcefclk2gfxclk_c);
>  	param->ulPixelclk2GfxclkM1 =
>  			le32_to_cpu(profile->pixclk2gfxclk_a);
>  	param->ulPixelclk2GfxclkM2 =
> -			le16_to_cpu(profile->pixclk2gfxclk_b);
> +			le32_to_cpu(profile->pixclk2gfxclk_b);
>  	param->ulPixelclk2GfxclkB =
>  			le32_to_cpu(profile->pixclk2gfxclk_c);
>  	param->ulPhyclk2GfxclkM1 =
>  			le32_to_cpu(profile->phyclk2gfxclk_a);
>  	param->ulPhyclk2GfxclkM2 =
> -			le16_to_cpu(profile->phyclk2gfxclk_b);
> +			le32_to_cpu(profile->phyclk2gfxclk_b);
>  	param->ulPhyclk2GfxclkB =
>  			le32_to_cpu(profile->phyclk2gfxclk_c);
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 30bc053..971f789 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2097,7 +2097,7 @@ static int vega10_populate_avfs_parameters(struct
> pp_hwmgr *hwmgr)
>  			pp_table->AvfsGbCksOn.m1 =
> 
> 	cpu_to_le32(avfs_params.ulGbFuseTableCksonM1);
>  			pp_table->AvfsGbCksOn.m2 =
> -
> 	cpu_to_le16(avfs_params.ulGbFuseTableCksonM2);
> +
> 	cpu_to_le32(avfs_params.ulGbFuseTableCksonM2);
>  			pp_table->AvfsGbCksOn.b =
> 
> 	cpu_to_le32(avfs_params.ulGbFuseTableCksonB);
>  			pp_table->AvfsGbCksOn.m1_shift = 24;
> @@ -2109,7 +2109,7 @@ static int vega10_populate_avfs_parameters(struct
> pp_hwmgr *hwmgr)
>  			pp_table->AvfsGbCksOff.m1 =
> 
> 	cpu_to_le32(avfs_params.ulGbFuseTableCksoffM1);
>  			pp_table->AvfsGbCksOff.m2 =
> -
> 	cpu_to_le16(avfs_params.ulGbFuseTableCksoffM2);
> +
> 	cpu_to_le32(avfs_params.ulGbFuseTableCksoffM2);
>  			pp_table->AvfsGbCksOff.b =
> 
> 	cpu_to_le32(avfs_params.ulGbFuseTableCksoffB);
>  			pp_table->AvfsGbCksOff.m1_shift = 24;
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 4/4] drm/amd/powerplay: enable CKS by default on vega10.

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Wednesday, May 31, 2017 8:16 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 4/4] drm/amd/powerplay: enable CKS by default on vega10.
> 
> Change-Id: I0e41ec0fb9987c73bd38a7eaf8173b5ec5c50734
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Assuming this is finally stable:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 971f789..43812d2 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -124,7 +124,7 @@ static void vega10_set_default_registry_data(struct
> pp_hwmgr *hwmgr)
>  	}
> 
>  	data->registry_data.clock_stretcher_support =
> -			hwmgr->feature_mask &
> PP_CLOCK_STRETCH_MASK ? false : true;
> +			hwmgr->feature_mask &
> PP_CLOCK_STRETCH_MASK ? true : false;
> 
>  	data->registry_data.ulv_support =
>  			hwmgr->feature_mask & PP_ULV_MASK ? true :
> false;
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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