[PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

[PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

[Evan Quan]

Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 901c960c..2b34971 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -70,7 +70,12 @@
 #define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26
 #define PPSMC_MSG_SetDppclkVoltageByFreq        0x27
 #define PPSMC_MSG_SetSoftMinVcn                 0x28
-#define PPSMC_Message_Count                     0x29
+#define PPSMC_MSG_GetGfxclkFrequency            0x2A
+#define PPSMC_MSG_GetFclkFrequency              0x2B
+#define PPSMC_MSG_GetMinGfxclkFrequency         0x2C
+#define PPSMC_MSG_GetMaxGfxclkFrequency         0x2D
+#define PPSMC_MSG_SoftReset                     0x2E
+#define PPSMC_Message_Count                     0x2F
 
 
 typedef uint16_t PPSMC_Result;
-- 
2.7.4

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[PATCH 2/4] drm/amd/powerplay: get raven max/min gfx clocks

[Evan Quan]

Change-Id: I56e713e16b9a794857e7ecbb7ca47e0ddd727862
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 20 ++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 6f0b2e5..e2ad41d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -421,6 +421,26 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
 	rv_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
 					ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 
+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+			PPSMC_MSG_GetMinGfxclkFrequency),
+			"Attempt to get min GFXCLK Failed!",
+			return -1);
+	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+			&result),
+			"Attempt to get min GFXCLK Failed!",
+			return -1);
+	rv_data->gfx_min_freq_limit = result * 100;
+
+	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+			PPSMC_MSG_GetMaxGfxclkFrequency),
+			"Attempt to get max GFXCLK Failed!",
+			return -1);
+	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+			&result),
+			"Attempt to get max GFXCLK Failed!",
+			return -1);
+	rv_data->gfx_max_freq_limit = result * 100;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 68d61bd..9dc5030 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -283,6 +283,8 @@ struct rv_hwmgr {
 	uint32_t                        vclk_soft_min;
 	uint32_t                        dclk_soft_min;
 	uint32_t                        gfx_actual_soft_min_freq;
+	uint32_t                        gfx_min_freq_limit;
+	uint32_t                        gfx_max_freq_limit;
 
 	bool                           vcn_power_gated;
 	bool                           vcn_dpg_mode;
-- 
2.7.4

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RE: [PATCH 2/4] drm/amd/powerplay: get raven max/min gfx clocks

[Deucher, Alexander]

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 2/4] drm/amd/powerplay: get raven max/min gfx clocks
> 
> Change-Id: I56e713e16b9a794857e7ecbb7ca47e0ddd727862
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 20
> ++++++++++++++++++++
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h |  2 ++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index 6f0b2e5..e2ad41d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -421,6 +421,26 @@ static int rv_populate_clock_table(struct pp_hwmgr
> *hwmgr)
>  	rv_get_clock_voltage_dependency_table(hwmgr, &pinfo-
> >vdd_dep_on_phyclk,
>  					ARRAY_SIZE(VddPhyClk),
> &VddPhyClk[0]);
> 
> +	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> +			PPSMC_MSG_GetMinGfxclkFrequency),
> +			"Attempt to get min GFXCLK Failed!",
> +			return -1);
> +	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
> +			&result),
> +			"Attempt to get min GFXCLK Failed!",
> +			return -1);
> +	rv_data->gfx_min_freq_limit = result * 100;
> +
> +	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> +			PPSMC_MSG_GetMaxGfxclkFrequency),
> +			"Attempt to get max GFXCLK Failed!",
> +			return -1);
> +	PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
> +			&result),
> +			"Attempt to get max GFXCLK Failed!",
> +			return -1);

Return proper error codes in this function.  Maybe -EINVAL?

With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> +	rv_data->gfx_max_freq_limit = result * 100;
> +
>  	return 0;
>  }
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> index 68d61bd..9dc5030 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> @@ -283,6 +283,8 @@ struct rv_hwmgr {
>  	uint32_t                        vclk_soft_min;
>  	uint32_t                        dclk_soft_min;
>  	uint32_t                        gfx_actual_soft_min_freq;
> +	uint32_t                        gfx_min_freq_limit;
> +	uint32_t                        gfx_max_freq_limit;
> 
>  	bool                           vcn_power_gated;
>  	bool                           vcn_dpg_mode;
> --
> 2.7.4

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[PATCH 3/4] drm/amd/powerplay: get raven current sclk and mclk

[Evan Quan]

Change-Id: I17120a53bc3cebd8cc7eb9f3d83124905632a409
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28 ++++++++++++++++++++++++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index e2ad41d..a20a6fe 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -850,13 +850,37 @@ static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
 static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 			  void *value, int *size)
 {
+	uint32_t sclk, mclk;
+	int ret = 0;
+
 	switch (idx) {
+	case AMDGPU_PP_SENSOR_GFX_SCLK:
+		ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetGfxclkFrequency);
+		if (!ret) {
+			rv_read_arg_from_smc(hwmgr->smumgr, &sclk);
+			/* in units of 10KHZ */
+			*((uint32_t *)value) = sclk * 100;
+			*size = 4;
+		}
+		break;
+	case AMDGPU_PP_SENSOR_GFX_MCLK:
+		ret = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_GetFclkFrequency);
+		if (!ret) {
+			rv_read_arg_from_smc(hwmgr->smumgr, &mclk);
+			/* in units of 10KHZ */
+			*((uint32_t *)value) = mclk * 100;
+			*size = 4;
+		}
+		break;
 	case AMDGPU_PP_SENSOR_GPU_TEMP:
 		*((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
-		return 0;
+		break;
 	default:
-		return -EINVAL;
+		ret = -EINVAL;
+		break;
 	}
+
+	return ret;
 }
 
 static const struct pp_hwmgr_func rv_hwmgr_funcs = {
-- 
2.7.4

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RE: [PATCH 3/4] drm/amd/powerplay: get raven current sclk and mclk

[Deucher, Alexander]

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 3/4] drm/amd/powerplay: get raven current sclk and mclk
> 
> Change-Id: I17120a53bc3cebd8cc7eb9f3d83124905632a409
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Add a better patch description.  Something like:
Add sclk and mclk support to the read sensors interface

With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 28
> ++++++++++++++++++++++++--
>  1 file changed, 26 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index e2ad41d..a20a6fe 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -850,13 +850,37 @@ static int rv_thermal_get_temperature(struct
> pp_hwmgr *hwmgr)
>  static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
>  			  void *value, int *size)
>  {
> +	uint32_t sclk, mclk;
> +	int ret = 0;
> +
>  	switch (idx) {
> +	case AMDGPU_PP_SENSOR_GFX_SCLK:
> +		ret = smum_send_msg_to_smc(hwmgr->smumgr,
> PPSMC_MSG_GetGfxclkFrequency);
> +		if (!ret) {
> +			rv_read_arg_from_smc(hwmgr->smumgr, &sclk);
> +			/* in units of 10KHZ */
> +			*((uint32_t *)value) = sclk * 100;
> +			*size = 4;
> +		}
> +		break;
> +	case AMDGPU_PP_SENSOR_GFX_MCLK:
> +		ret = smum_send_msg_to_smc(hwmgr->smumgr,
> PPSMC_MSG_GetFclkFrequency);
> +		if (!ret) {
> +			rv_read_arg_from_smc(hwmgr->smumgr, &mclk);
> +			/* in units of 10KHZ */
> +			*((uint32_t *)value) = mclk * 100;
> +			*size = 4;
> +		}
> +		break;
>  	case AMDGPU_PP_SENSOR_GPU_TEMP:
>  		*((uint32_t *)value) =
> rv_thermal_get_temperature(hwmgr);
> -		return 0;
> +		break;
>  	default:
> -		return -EINVAL;
> +		ret = -EINVAL;
> +		break;
>  	}
> +
> +	return ret;
>  }
> 
>  static const struct pp_hwmgr_func rv_hwmgr_funcs = {
> --
> 2.7.4

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[PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels

[Evan Quan]

Change-Id: I40fa698cd9a25df43aa4bf476c4aa0a8b043edf9
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 48 +++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index a20a6fe..5135328 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -619,7 +619,53 @@ static int rv_force_clock_level(struct pp_hwmgr *hwmgr,
 static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
 		enum pp_clock_type type, char *buf)
 {
-	return 0;
+	struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
+	struct rv_voltage_dependency_table *mclk_table =
+			data->clock_vol_info.vdd_dep_on_fclk;
+	int i, now, size = 0;
+
+	switch (type) {
+	case PP_SCLK:
+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+				PPSMC_MSG_GetGfxclkFrequency),
+				"Attempt to get current GFXCLK Failed!",
+				return -1);
+		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+				&now),
+				"Attempt to get current GFXCLK Failed!",
+				return -1);
+
+		size += sprintf(buf + size, "0: %uMhz %s\n",
+				data->gfx_min_freq_limit / 100,
+				((data->gfx_min_freq_limit / 100)
+				 == now) ? "*" : "");
+		size += sprintf(buf + size, "1: %uMhz %s\n",
+				data->gfx_max_freq_limit / 100,
+				((data->gfx_max_freq_limit / 100)
+				 == now) ? "*" : "");
+		break;
+	case PP_MCLK:
+		PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr->smumgr,
+				PPSMC_MSG_GetFclkFrequency),
+				"Attempt to get current MEMCLK Failed!",
+				return -1);
+		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr->smumgr,
+				&now),
+				"Attempt to get current MEMCLK Failed!",
+				return -1);
+
+		for (i = 0; i < mclk_table->count; i++)
+			size += sprintf(buf + size, "%d: %uMhz %s\n",
+					i,
+					mclk_table->entries[i].clk / 100,
+					((mclk_table->entries[i].clk / 100)
+					 == now) ? "*" : "");
+		break;
+	default:
+		break;
+	}
+
+	return size;
 }
 
 static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
-- 
2.7.4

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RE: [PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels

[Deucher, Alexander]

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 4/4] drm/amd/powerplay: get raven sclk and mclk levels
> 

Add a better patch description.  Something like:
Add query for sclk and mclk to the sysfs interface.

> Change-Id: I40fa698cd9a25df43aa4bf476c4aa0a8b043edf9
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 48
> +++++++++++++++++++++++++-
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index a20a6fe..5135328 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -619,7 +619,53 @@ static int rv_force_clock_level(struct pp_hwmgr
> *hwmgr,
>  static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>  		enum pp_clock_type type, char *buf)
>  {
> -	return 0;
> +	struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
> +	struct rv_voltage_dependency_table *mclk_table =
> +			data->clock_vol_info.vdd_dep_on_fclk;
> +	int i, now, size = 0;
> +
> +	switch (type) {
> +	case PP_SCLK:
> +
> 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> +				PPSMC_MSG_GetGfxclkFrequency),
> +				"Attempt to get current GFXCLK Failed!",
> +				return -1);
> +		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr-
> >smumgr,
> +				&now),
> +				"Attempt to get current GFXCLK Failed!",
> +				return -1);
> +
> +		size += sprintf(buf + size, "0: %uMhz %s\n",
> +				data->gfx_min_freq_limit / 100,
> +				((data->gfx_min_freq_limit / 100)
> +				 == now) ? "*" : "");
> +		size += sprintf(buf + size, "1: %uMhz %s\n",
> +				data->gfx_max_freq_limit / 100,
> +				((data->gfx_max_freq_limit / 100)
> +				 == now) ? "*" : "");
> +		break;
> +	case PP_MCLK:
> +
> 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr-
> >smumgr,
> +				PPSMC_MSG_GetFclkFrequency),
> +				"Attempt to get current MEMCLK Failed!",
> +				return -1);
> +		PP_ASSERT_WITH_CODE(!rv_read_arg_from_smc(hwmgr-
> >smumgr,
> +				&now),
> +				"Attempt to get current MEMCLK Failed!",
> +				return -1);

Return proper error codes in this function.

With the above comments fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> +
> +		for (i = 0; i < mclk_table->count; i++)
> +			size += sprintf(buf + size, "%d: %uMhz %s\n",
> +					i,
> +					mclk_table->entries[i].clk / 100,
> +					((mclk_table->entries[i].clk / 100)
> +					 == now) ? "*" : "");
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return size;
>  }
> 
>  static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct
> pp_hw_power_state *state,
> --
> 2.7.4

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Re: [PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

[Zhang, Jerry (Junwei)]

On 09/30/2017 09:10 AM, Evan Quan wrote:
> Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
> Signed-off-by: Evan Quan <evan.quan@amd.com>
the series is
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++++++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> index 901c960c..2b34971 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> @@ -70,7 +70,12 @@
>   #define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26
>   #define PPSMC_MSG_SetDppclkVoltageByFreq        0x27
>   #define PPSMC_MSG_SetSoftMinVcn                 0x28
> -#define PPSMC_Message_Count                     0x29
> +#define PPSMC_MSG_GetGfxclkFrequency            0x2A
> +#define PPSMC_MSG_GetFclkFrequency              0x2B
> +#define PPSMC_MSG_GetMinGfxclkFrequency         0x2C
> +#define PPSMC_MSG_GetMaxGfxclkFrequency         0x2D
> +#define PPSMC_MSG_SoftReset                     0x2E
> +#define PPSMC_Message_Count                     0x2F
>
>
>   typedef uint16_t PPSMC_Result;
>
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RE: [PATCH 1/4] drm/amd/powerplay: added new raven ppsmc messages

[Deucher, Alexander]

> -----Original Message-----
> From: Evan Quan [mailto:evan.quan@amd.com]
> Sent: Friday, September 29, 2017 9:10 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Zhang, Jerry; Quan, Evan
> Subject: [PATCH 1/4] drm/amd/powerplay: added new raven ppsmc
> messages
> 
> Change-Id: I598f8ab583fc9c7045a4852d6972df90a82f7472
> Signed-off-by: Evan Quan <evan.quan@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> index 901c960c..2b34971 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
> @@ -70,7 +70,12 @@
>  #define PPSMC_MSG_SetPhyclkVoltageByFreq        0x26
>  #define PPSMC_MSG_SetDppclkVoltageByFreq        0x27
>  #define PPSMC_MSG_SetSoftMinVcn                 0x28
> -#define PPSMC_Message_Count                     0x29
> +#define PPSMC_MSG_GetGfxclkFrequency            0x2A
> +#define PPSMC_MSG_GetFclkFrequency              0x2B
> +#define PPSMC_MSG_GetMinGfxclkFrequency         0x2C
> +#define PPSMC_MSG_GetMaxGfxclkFrequency         0x2D
> +#define PPSMC_MSG_SoftReset                     0x2E
> +#define PPSMC_Message_Count                     0x2F
> 
> 
>  typedef uint16_t PPSMC_Result;
> --
> 2.7.4

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