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From: "Deucher, Alexander" <Alexander.Deucher@amd.com>
To: 'Jean Delvare' <jdelvare@suse.de>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Cc: "Cui, Flora" <Flora.Cui@amd.com>, "Zhang, Jerry" <Jerry.Zhang@amd.com>
Subject: RE: [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan"
Date: Thu, 2 Mar 2017 17:58:14 +0000	[thread overview]
Message-ID: <BN6PR12MB165224DE7BE8DDDAE7A025FCF7280@BN6PR12MB1652.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20170302182135.3afe11e1@endymion>

> -----Original Message-----
> From: Jean Delvare [mailto:jdelvare@suse.de]
> Sent: Thursday, March 02, 2017 12:22 PM
> To: stable@vger.kernel.org
> Cc: Cui, Flora; Zhang, Jerry; Deucher, Alexander
> Subject: [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan"
> 
> Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for
> oland/hainan") as it is causing ugly visual artifacts on at least
> Oland. This is only an optimization so we can live without it.
> 
> This fixes kernel bug #194761:
> amdgpu driver breaks on Oland (SI)
> https://bugzilla.kernel.org/show_bug.cgi?id=194761
> 
> Signed-off-by: Jean Delvare <jdelvare@suse.de>
> Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
> Cc: Flora Cui <Flora.Cui@amd.com>
> Cc: Junwei Zhang <Jerry.Zhang@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>

Acked-by: Alex Deucher <alexander.deucher@amd.com>

> ---
> Note: This is for stable v4.10 branch only. v4.11 and later have a
> different fix, but it's much larger and more intrusive so not suitable
> for a stable branch.
> 
>  drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 ++++++++++++++----------
> ----------
>  1 file changed, 139 insertions(+), 191 deletions(-)
> 
> --- linux-4.10.orig/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c	2017-02-19
> 23:34:00.000000000 +0100
> +++ linux-4.10/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c	2017-03-02
> 18:10:45.786414946 +0100
> @@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
>  		for (reg_offset = 0; reg_offset < num_tile_mode_states;
> reg_offset++) {
>  			switch (reg_offset) {
>  			case 0:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 1:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 2:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 3:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 4:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 5:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(split_equal_to_row_size) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 6:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(split_equal_to_row_size) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 7:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(split_equal_to_row_size) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 8:
> -				gb_tile_moden =
> (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 9:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 10:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 11:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 12:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 13:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 14:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 15:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 16:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 17:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> -				break;
> -			case 18:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_1D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P2));
> -				break;
> -			case 19:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> +
> TILE_SPLIT(split_equal_to_row_size) |
> 
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> -				break;
> -			case 20:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THICK) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> -
> NUM_BANKS(ADDR_SURF_16_BANK) |
> -
> TILE_SPLIT(split_equal_to_row_size));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 21:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 22:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> +
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> +
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
>  				break;
>  			case 23:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 24:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
> +
> NUM_BANKS(ADDR_SURF_16_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_8_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
>  				break;
>  			case 25:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> +				gb_tile_moden =
> (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> +
> MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> +
> PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> 
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> -				break;
> -			case 26:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> -				break;
> -			case 27:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> -				break;
> -			case 28:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> -				break;
> -			case 29:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
> -
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> -
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> -				break;
> -			case 30:
> -				gb_tile_moden =
> (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
> -
> ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> -
> PIPE_CONFIG(ADDR_SURF_P2) |
> -
> TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
> +
> NUM_BANKS(ADDR_SURF_8_BANK) |
> 
> BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> 
> BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> -
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> -
> NUM_BANKS(ADDR_SURF_4_BANK));
> +
> MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
>  				break;
>  			default:
> -				continue;
> +				gb_tile_moden = 0;
> +				break;
>  			}
>  			adev->gfx.config.tile_mode_array[reg_offset] =
> gb_tile_moden;
>  			WREG32(mmGB_TILE_MODE0 + reg_offset,
> gb_tile_moden);
> 
> 
> --
> Jean Delvare
> SUSE L3 Support

  reply	other threads:[~2017-03-02 18:34 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-02 17:21 [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan" Jean Delvare
2017-03-02 17:58 ` Deucher, Alexander [this message]
2017-03-02 19:32 ` Greg KH
2017-03-02 21:04   ` Jean Delvare
2017-03-02 21:23     ` Deucher, Alexander
2017-03-12 19:17 ` Patch "Revert "drm/amdgpu: update tile table for oland/hainan"" has been added to the 4.10-stable tree gregkh

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