* [PATCH] drm/amdgpu: allow shifts >= 32 in AMDGPU_TILING_SET/GET
@ 2017-03-21 19:44 Marek Olšák
[not found] ` <1490125443-2458-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Marek Olšák @ 2017-03-21 19:44 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Marek Olšák <marek.olsak@amd.com>
also adjust the comments
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
include/uapi/drm/amdgpu_drm.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 7c6cc11..7fb9d10 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -204,46 +204,48 @@ union drm_amdgpu_ctx {
struct drm_amdgpu_gem_userptr {
__u64 addr;
__u64 size;
/* AMDGPU_GEM_USERPTR_* */
__u32 flags;
/* Resulting GEM handle */
__u32 handle;
};
+/* SI-CI-VI: */
/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
-/* Tiling flags for GFX9. */
+
+/* GFX9 and later: */
#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
/* Set/Get helpers for tiling flags. */
#define AMDGPU_TILING_SET(field, value) \
- (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
+ (((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
#define AMDGPU_TILING_GET(value, field) \
- (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
+ (((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
/** The same structure is shared for input/output */
struct drm_amdgpu_gem_metadata {
/** GEM Object handle */
__u32 handle;
/** Do we want get or set metadata */
__u32 op;
--
2.7.4
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amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread[parent not found: <1490125443-2458-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* RE: [PATCH] drm/amdgpu: allow shifts >= 32 in AMDGPU_TILING_SET/GET [not found] ` <1490125443-2458-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2017-03-21 20:05 ` Deucher, Alexander 2017-03-22 10:43 ` Grazvydas Ignotas 1 sibling, 0 replies; 4+ messages in thread From: Deucher, Alexander @ 2017-03-21 20:05 UTC (permalink / raw) To: 'Marek Olšák', amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf > Of Marek Olšák > Sent: Tuesday, March 21, 2017 3:44 PM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH] drm/amdgpu: allow shifts >= 32 in > AMDGPU_TILING_SET/GET > > From: Marek Olšák <marek.olsak@amd.com> > > also adjust the comments > > Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > include/uapi/drm/amdgpu_drm.h | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/include/uapi/drm/amdgpu_drm.h > b/include/uapi/drm/amdgpu_drm.h > index 7c6cc11..7fb9d10 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -204,46 +204,48 @@ union drm_amdgpu_ctx { > > struct drm_amdgpu_gem_userptr { > __u64 addr; > __u64 size; > /* AMDGPU_GEM_USERPTR_* */ > __u32 flags; > /* Resulting GEM handle */ > __u32 handle; > }; > > +/* SI-CI-VI: */ > /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields > */ > #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 > #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf > #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 > #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f > #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 > #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 > #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 > #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 > #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 > #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 > #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 > #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 > #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 > #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 > #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 > #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 > -/* Tiling flags for GFX9. */ > + > +/* GFX9 and later: */ > #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 > #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f > > /* Set/Get helpers for tiling flags. */ > #define AMDGPU_TILING_SET(field, value) \ > - (((value) & AMDGPU_TILING_##field##_MASK) << > AMDGPU_TILING_##field##_SHIFT) > + (((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << > AMDGPU_TILING_##field##_SHIFT) > #define AMDGPU_TILING_GET(value, field) \ > - (((value) >> AMDGPU_TILING_##field##_SHIFT) & > AMDGPU_TILING_##field##_MASK) > + (((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & > AMDGPU_TILING_##field##_MASK) > > #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 > #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 > > /** The same structure is shared for input/output */ > struct drm_amdgpu_gem_metadata { > /** GEM Object handle */ > __u32 handle; > /** Do we want get or set metadata */ > __u32 op; > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: allow shifts >= 32 in AMDGPU_TILING_SET/GET [not found] ` <1490125443-2458-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2017-03-21 20:05 ` Deucher, Alexander @ 2017-03-22 10:43 ` Grazvydas Ignotas [not found] ` <CANOLnOPaUu1_U7eq2Mk-8G=zws8x5a2fLp-svKEHkfmPkrpitQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 1 sibling, 1 reply; 4+ messages in thread From: Grazvydas Ignotas @ 2017-03-22 10:43 UTC (permalink / raw) To: Marek Olšák; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW On Tue, Mar 21, 2017 at 9:44 PM, Marek Olšák <maraeo@gmail.com> wrote: > From: Marek Olšák <marek.olsak@amd.com> > > also adjust the comments > > Signed-off-by: Marek Olšák <marek.olsak@amd.com> > --- > include/uapi/drm/amdgpu_drm.h | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index 7c6cc11..7fb9d10 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -204,46 +204,48 @@ union drm_amdgpu_ctx { > > struct drm_amdgpu_gem_userptr { > __u64 addr; > __u64 size; > /* AMDGPU_GEM_USERPTR_* */ > __u32 flags; > /* Resulting GEM handle */ > __u32 handle; > }; > > +/* SI-CI-VI: */ > /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ > #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 > #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf > #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 > #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f > #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 > #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 > #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 > #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 > #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 > #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 > #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 > #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 > #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 > #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 > #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 > #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 > -/* Tiling flags for GFX9. */ > + > +/* GFX9 and later: */ > #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 > #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f > > /* Set/Get helpers for tiling flags. */ > #define AMDGPU_TILING_SET(field, value) \ > - (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) > + (((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) > #define AMDGPU_TILING_GET(value, field) \ > - (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) > + (((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) Shouldn't it be __u64 instead of uint64_t? The kernel header doesn't include stdint.h or use any uint* types. Gražvydas _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <CANOLnOPaUu1_U7eq2Mk-8G=zws8x5a2fLp-svKEHkfmPkrpitQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: allow shifts >= 32 in AMDGPU_TILING_SET/GET [not found] ` <CANOLnOPaUu1_U7eq2Mk-8G=zws8x5a2fLp-svKEHkfmPkrpitQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2017-03-22 16:32 ` Marek Olšák 0 siblings, 0 replies; 4+ messages in thread From: Marek Olšák @ 2017-03-22 16:32 UTC (permalink / raw) To: Grazvydas Ignotas; +Cc: amd-gfx mailing list On Wed, Mar 22, 2017 at 11:43 AM, Grazvydas Ignotas <notasas@gmail.com> wrote: > On Tue, Mar 21, 2017 at 9:44 PM, Marek Olšák <maraeo@gmail.com> wrote: >> From: Marek Olšák <marek.olsak@amd.com> >> >> also adjust the comments >> >> Signed-off-by: Marek Olšák <marek.olsak@amd.com> >> --- >> include/uapi/drm/amdgpu_drm.h | 8 +++++--- >> 1 file changed, 5 insertions(+), 3 deletions(-) >> >> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h >> index 7c6cc11..7fb9d10 100644 >> --- a/include/uapi/drm/amdgpu_drm.h >> +++ b/include/uapi/drm/amdgpu_drm.h >> @@ -204,46 +204,48 @@ union drm_amdgpu_ctx { >> >> struct drm_amdgpu_gem_userptr { >> __u64 addr; >> __u64 size; >> /* AMDGPU_GEM_USERPTR_* */ >> __u32 flags; >> /* Resulting GEM handle */ >> __u32 handle; >> }; >> >> +/* SI-CI-VI: */ >> /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ >> #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 >> #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf >> #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 >> #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f >> #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 >> #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 >> #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 >> #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 >> #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 >> #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 >> #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 >> #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 >> #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 >> #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 >> #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 >> #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 >> -/* Tiling flags for GFX9. */ >> + >> +/* GFX9 and later: */ >> #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 >> #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f >> >> /* Set/Get helpers for tiling flags. */ >> #define AMDGPU_TILING_SET(field, value) \ >> - (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) >> + (((uint64_t)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) >> #define AMDGPU_TILING_GET(value, field) \ >> - (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) >> + (((uint64_t)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) > > Shouldn't it be __u64 instead of uint64_t? The kernel header doesn't > include stdint.h or use any uint* types. Yeah, I'll fix that before pushing. Marek _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-03-21 19:44 [PATCH] drm/amdgpu: allow shifts >= 32 in AMDGPU_TILING_SET/GET Marek Olšák
[not found] ` <1490125443-2458-1-git-send-email-maraeo-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-03-21 20:05 ` Deucher, Alexander
2017-03-22 10:43 ` Grazvydas Ignotas
[not found] ` <CANOLnOPaUu1_U7eq2Mk-8G=zws8x5a2fLp-svKEHkfmPkrpitQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-03-22 16:32 ` Marek Olšák
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