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* [PATCH 1/2] drm/amd/pp: Add a new pp feature mask bit for OD feature
@ 2018-01-04  9:58 Rex Zhu
       [not found] ` <1515059910-29827-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2018-01-04  9:58 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

when this bit was set on module load,
driver will allow the user over/under gpu
clock and voltage through sysfs.

by default, this bit was not set.

Change-Id: I4ec2d3a689ae946d4af9f904c59b42da5b929181
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        | 3 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++----
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          | 2 ++
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 50afcf6..defe73a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -119,7 +119,7 @@
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0xffffffff;
+uint amdgpu_pp_feature_mask = 0x2fff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index e35bdc5..ebfbbcf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_CAC);
 	}
 
+	if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
+		hwmgr->od_enabled = true;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index fdbe117..9b17cec 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3606,8 +3606,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
 		dpm_table->sclk_table.dpm_levels
 		[dpm_table->sclk_table.count - 1].value = sclk;
 
-		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+		if (hwmgr->od_enabled) {
 		/* Need to do calculation based on the golden DPM table
 		 * as the Heatmap GPU Clock axis is also based on the default values
 		 */
@@ -3652,8 +3651,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
 		dpm_table->mclk_table.dpm_levels
 			[dpm_table->mclk_table.count - 1].value = mclk;
 
-		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-		    phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+		if (hwmgr->od_enabled) {
 
 			PP_ASSERT_WITH_CODE(
 					(golden_dpm_table->mclk_table.dpm_levels
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 7e6feed..4219004 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3394,8 +3394,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
 				dpm_table->
 				gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
 				value = sclk;
-				if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-				    PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
+				if (hwmgr->od_enabled) {
 					/* Need to do calculation based on the golden DPM table
 					 * as the Heatmap GPU Clock axis is also based on
 					 * the default values
@@ -3449,9 +3448,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
 			mem_table.dpm_levels[dpm_table->mem_table.count - 1].
 			value = mclk;
 
-			if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-			    PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
+			if (hwmgr->od_enabled) {
 				PP_ASSERT_WITH_CODE(
 					golden_dpm_table->mem_table.dpm_levels
 					[golden_dpm_table->mem_table.count - 1].value,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index f37f211..5d92f13 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
 	PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
 	PP_SOCCLK_DPM_MASK = 0x1000,
 	PP_DCEFCLK_DPM_MASK = 0x2000,
+	PP_OVER_DRIVER_MASK = 0x4000,
 };
 
 enum PHM_BackEnd_Magic {
@@ -750,6 +751,7 @@ struct pp_hwmgr {
 	struct amd_pp_profile default_compute_power_profile;
 	enum amd_pp_profile_type current_power_profile;
 	bool en_umd_pstate;
+	bool od_enabled;
 };
 
 struct cgs_irq_src_funcs {
-- 
1.9.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.
       [not found] ` <1515059910-29827-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-04  9:58   ` Rex Zhu
       [not found]     ` <1515059910-29827-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2018-01-04 14:28   ` [PATCH 1/2] drm/amd/pp: Add a new pp feature mask bit for OD feature Deucher, Alexander
  1 sibling, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2018-01-04  9:58 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

Change-Id: I05db3fe2a274ce9666a5074c82448bf8bd6e7ee8
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 73 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 14 +++++
 2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 9b17cec..863f0d6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -792,6 +792,74 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
 	return 0;
 }
 
+static int smu7_get_voltage_dependency_table(
+			const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
+			struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+	uint8_t i = 0;
+	PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
+				"Voltage Lookup Table empty",
+				return -EINVAL);
+
+	dep_table->count = allowed_dep_table->count;
+	for (i=0; i<dep_table->count; i++) {
+		dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
+		dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
+		dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
+		dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
+		dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
+		dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
+		dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
+		dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
+		dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
+		dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
+	}
+
+	return 0;
+}
+
+static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+	struct phm_ppt_v1_information *table_info =
+			(struct phm_ppt_v1_information *)(hwmgr->pptable);
+	uint32_t i;
+
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+	struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+
+	if (table_info == NULL)
+		return -EINVAL;
+
+	dep_sclk_table = table_info->vdd_dep_on_sclk;
+	dep_mclk_table = table_info->vdd_dep_on_mclk;
+
+	odn_table->odn_core_clock_dpm_levels.number_of_performance_levels =
+						data->dpm_table.sclk_table.count;
+	for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+		odn_table->odn_core_clock_dpm_levels.entries[i].clock =
+					data->dpm_table.sclk_table.dpm_levels[i].value;
+		odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
+	}
+
+	smu7_get_voltage_dependency_table(dep_sclk_table,
+		(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
+
+	odn_table->odn_memory_clock_dpm_levels.number_of_performance_levels =
+						data->dpm_table.mclk_table.count;
+	for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+		odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
+					data->dpm_table.mclk_table.dpm_levels[i].value;
+		odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
+	}
+
+	smu7_get_voltage_dependency_table(dep_mclk_table,
+		(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
+
+	return 0;
+}
+
 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 {
 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -808,6 +876,11 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 	/* save a copy of the default DPM table */
 	memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 			sizeof(struct smu7_dpm_table));
+
+	/* initialize ODN table */
+	if (hwmgr->od_enabled)
+		smu7_odn_initial_default_setting(hwmgr);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index beba25c..8eec974 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -178,9 +178,23 @@ struct smu7_pcie_perf_range {
 	uint16_t  min;
 };
 
+struct smu7_odn_clock_voltage_dependency_table {
+	uint32_t count;
+	phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct smu7_odn_dpm_table {
+	struct phm_odn_clock_levels		odn_core_clock_dpm_levels;
+	struct phm_odn_clock_levels		odn_memory_clock_dpm_levels;
+	struct smu7_odn_clock_voltage_dependency_table	vdd_dependency_on_sclk;
+	struct smu7_odn_clock_voltage_dependency_table	vdd_dependency_on_mclk;
+	uint32_t					odn_mclk_min_limit;
+};
+
 struct smu7_hwmgr {
 	struct smu7_dpm_table			dpm_table;
 	struct smu7_dpm_table			golden_dpm_table;
+	struct smu7_odn_dpm_table		odn_dpm_table;
 
 	uint32_t						voting_rights_clients[8];
 	uint32_t						static_screen_threshold_unit;
-- 
1.9.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/amd/pp: Add a new pp feature mask bit for OD feature
       [not found] ` <1515059910-29827-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2018-01-04  9:58   ` [PATCH 2/2] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI Rex Zhu
@ 2018-01-04 14:28   ` Deucher, Alexander
  1 sibling, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2018-01-04 14:28 UTC (permalink / raw)
  To: Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


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Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, January 4, 2018 4:58:29 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 1/2] drm/amd/pp: Add a new pp feature mask bit for OD feature

when this bit was set on module load,
driver will allow the user over/under gpu
clock and voltage through sysfs.

by default, this bit was not set.

Change-Id: I4ec2d3a689ae946d4af9f904c59b42da5b929181
Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        | 3 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 6 ++----
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++-----
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          | 2 ++
 5 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 50afcf6..defe73a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -119,7 +119,7 @@
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0xffffffff;
+uint amdgpu_pp_feature_mask = 0x2fff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index e35bdc5..ebfbbcf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
                         PHM_PlatformCaps_CAC);
         }

+       if (hwmgr->feature_mask & PP_OVER_DRIVER_MASK)
+               hwmgr->od_enabled = true;
+
         return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index fdbe117..9b17cec 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3606,8 +3606,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
                 dpm_table->sclk_table.dpm_levels
                 [dpm_table->sclk_table.count - 1].value = sclk;

-               if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-                   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+               if (hwmgr->od_enabled) {
                 /* Need to do calculation based on the golden DPM table
                  * as the Heatmap GPU Clock axis is also based on the default values
                  */
@@ -3652,8 +3651,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
                 dpm_table->mclk_table.dpm_levels
                         [dpm_table->mclk_table.count - 1].value = mclk;

-               if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) ||
-                   phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) {
+               if (hwmgr->od_enabled) {

                         PP_ASSERT_WITH_CODE(
                                         (golden_dpm_table->mclk_table.dpm_levels
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 7e6feed..4219004 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3394,8 +3394,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
                                 dpm_table->
                                 gfx_table.dpm_levels[dpm_table->gfx_table.count - 1].
                                 value = sclk;
-                               if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-                                   PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
+                               if (hwmgr->od_enabled) {
                                         /* Need to do calculation based on the golden DPM table
                                          * as the Heatmap GPU Clock axis is also based on
                                          * the default values
@@ -3449,9 +3448,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
                         mem_table.dpm_levels[dpm_table->mem_table.count - 1].
                         value = mclk;

-                       if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) ||
-                           PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) {
-
+                       if (hwmgr->od_enabled) {
                                 PP_ASSERT_WITH_CODE(
                                         golden_dpm_table->mem_table.dpm_levels
                                         [golden_dpm_table->mem_table.count - 1].value,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index f37f211..5d92f13 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -84,6 +84,7 @@ enum PP_FEATURE_MASK {
         PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
         PP_SOCCLK_DPM_MASK = 0x1000,
         PP_DCEFCLK_DPM_MASK = 0x2000,
+       PP_OVER_DRIVER_MASK = 0x4000,
 };

 enum PHM_BackEnd_Magic {
@@ -750,6 +751,7 @@ struct pp_hwmgr {
         struct amd_pp_profile default_compute_power_profile;
         enum amd_pp_profile_type current_power_profile;
         bool en_umd_pstate;
+       bool od_enabled;
 };

 struct cgs_irq_src_funcs {
--
1.9.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.
       [not found]     ` <1515059910-29827-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-04 14:31       ` Deucher, Alexander
  0 siblings, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2018-01-04 14:31 UTC (permalink / raw)
  To: Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 6849 bytes --]

Please include a commit message.  Something like:

Add initial infrastructure for manual dpm control.

With that fixed:

Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>

________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, January 4, 2018 4:58:30 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 2/2] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.

Change-Id: I05db3fe2a274ce9666a5074c82448bf8bd6e7ee8
Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 73 ++++++++++++++++++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 14 +++++
 2 files changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 9b17cec..863f0d6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -792,6 +792,74 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
         return 0;
 }

+static int smu7_get_voltage_dependency_table(
+                       const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
+                       struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
+{
+       uint8_t i = 0;
+       PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
+                               "Voltage Lookup Table empty",
+                               return -EINVAL);
+
+       dep_table->count = allowed_dep_table->count;
+       for (i=0; i<dep_table->count; i++) {
+               dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
+               dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
+               dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
+               dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
+               dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
+               dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
+               dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
+               dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
+               dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
+               dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
+       }
+
+       return 0;
+}
+
+static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
+{
+       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+       struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+       struct phm_ppt_v1_information *table_info =
+                       (struct phm_ppt_v1_information *)(hwmgr->pptable);
+       uint32_t i;
+
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
+
+       if (table_info == NULL)
+               return -EINVAL;
+
+       dep_sclk_table = table_info->vdd_dep_on_sclk;
+       dep_mclk_table = table_info->vdd_dep_on_mclk;
+
+       odn_table->odn_core_clock_dpm_levels.number_of_performance_levels =
+                                               data->dpm_table.sclk_table.count;
+       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+               odn_table->odn_core_clock_dpm_levels.entries[i].clock =
+                                       data->dpm_table.sclk_table.dpm_levels[i].value;
+               odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
+       }
+
+       smu7_get_voltage_dependency_table(dep_sclk_table,
+               (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
+
+       odn_table->odn_memory_clock_dpm_levels.number_of_performance_levels =
+                                               data->dpm_table.mclk_table.count;
+       for (i=0; i<data->dpm_table.sclk_table.count; i++) {
+               odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
+                                       data->dpm_table.mclk_table.dpm_levels[i].value;
+               odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
+       }
+
+       smu7_get_voltage_dependency_table(dep_mclk_table,
+               (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
+
+       return 0;
+}
+
 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 {
         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
@@ -808,6 +876,11 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
         /* save a copy of the default DPM table */
         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
                         sizeof(struct smu7_dpm_table));
+
+       /* initialize ODN table */
+       if (hwmgr->od_enabled)
+               smu7_odn_initial_default_setting(hwmgr);
+
         return 0;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index beba25c..8eec974 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -178,9 +178,23 @@ struct smu7_pcie_perf_range {
         uint16_t  min;
 };

+struct smu7_odn_clock_voltage_dependency_table {
+       uint32_t count;
+       phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
+};
+
+struct smu7_odn_dpm_table {
+       struct phm_odn_clock_levels             odn_core_clock_dpm_levels;
+       struct phm_odn_clock_levels             odn_memory_clock_dpm_levels;
+       struct smu7_odn_clock_voltage_dependency_table  vdd_dependency_on_sclk;
+       struct smu7_odn_clock_voltage_dependency_table  vdd_dependency_on_mclk;
+       uint32_t                                        odn_mclk_min_limit;
+};
+
 struct smu7_hwmgr {
         struct smu7_dpm_table                   dpm_table;
         struct smu7_dpm_table                   golden_dpm_table;
+       struct smu7_odn_dpm_table               odn_dpm_table;

         uint32_t                                                voting_rights_clients[8];
         uint32_t                                                static_screen_threshold_unit;
--
1.9.1

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^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-01-04 14:31 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-04  9:58 [PATCH 1/2] drm/amd/pp: Add a new pp feature mask bit for OD feature Rex Zhu
     [not found] ` <1515059910-29827-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-04  9:58   ` [PATCH 2/2] drm/amd/pp: Add and initialize OD_dpm_table for CI/VI Rex Zhu
     [not found]     ` <1515059910-29827-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-04 14:31       ` Deucher, Alexander
2018-01-04 14:28   ` [PATCH 1/2] drm/amd/pp: Add a new pp feature mask bit for OD feature Deucher, Alexander

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