[PATCH 1/4] drm/amd/powerplay: add dummy pp table for raven.

[PATCH 1/4] drm/amd/powerplay: add dummy pp table for raven.

[Rex Zhu]

Change-Id: I235d31017ebc2801e57a60e7e6293172dbf1c7d7
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../gpu/drm/amd/powerplay/hwmgr/processpptables.c  | 62 +++++++++++++++++-----
 1 file changed, 50 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index 2716721..707809b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -678,7 +678,8 @@ static PP_StateClassificationFlags make_classification_flags(
 static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
 						struct pp_power_state *ps,
 							    uint8_t version,
-			 const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info) {
+			 const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info)
+{
 	unsigned long rrr_index;
 	unsigned long tmp;
 
@@ -790,6 +791,39 @@ static const ATOM_PPLIB_STATE_V2 *get_state_entry_v2(
 	return pstate;
 }
 
+static unsigned char soft_dummy_pp_table[] = {
+	0xe1, 0x01, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x4a, 0x00, 0x6c, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x42, 0x00, 0x02, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00,
+	0x00, 0x4e, 0x00, 0x88, 0x00, 0x00, 0x9e, 0x00, 0x17, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00,
+	0x07, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+	0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x18, 0x05, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x00, 0x43, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x8e, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c,
+	0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x70, 0x00, 0x91, 0xf4, 0x00,
+	0x64, 0x00, 0x40, 0x19, 0x01, 0x5a, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a,
+	0x00, 0x00, 0x09, 0x30, 0x75, 0x00, 0x30, 0x75, 0x00, 0x40, 0x9c, 0x00, 0x40, 0x9c, 0x00, 0x59,
+	0xd8, 0x00, 0x59, 0xd8, 0x00, 0x91, 0xf4, 0x00, 0x91, 0xf4, 0x00, 0x0e, 0x28, 0x01, 0x0e, 0x28,
+	0x01, 0x90, 0x5f, 0x01, 0x90, 0x5f, 0x01, 0x00, 0x77, 0x01, 0x00, 0x77, 0x01, 0xca, 0x91, 0x01,
+	0xca, 0x91, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01,
+	0x7c, 0x00, 0x02, 0x70, 0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a,
+	0x00, 0x07, 0x08, 0x08, 0x00, 0x08, 0x00, 0x01, 0x02, 0x02, 0x02, 0x01, 0x02, 0x02, 0x02, 0x03,
+	0x02, 0x04, 0x02, 0x00, 0x08, 0x40, 0x9c, 0x00, 0x30, 0x75, 0x00, 0x74, 0xb5, 0x00, 0xa0, 0x8c,
+	0x00, 0x60, 0xea, 0x00, 0x74, 0xb5, 0x00, 0x0e, 0x28, 0x01, 0x60, 0xea, 0x00, 0x90, 0x5f, 0x01,
+	0x40, 0x19, 0x01, 0xb2, 0xb0, 0x01, 0x90, 0x5f, 0x01, 0xc0, 0xd4, 0x01, 0x00, 0x77, 0x01, 0x5e,
+	0xff, 0x01, 0xca, 0x91, 0x01, 0x08, 0x80, 0x00, 0x00, 0x7e, 0x00, 0x01, 0x7c, 0x00, 0x02, 0x70,
+	0x00, 0x03, 0x64, 0x00, 0x04, 0x5a, 0x00, 0x05, 0x52, 0x00, 0x06, 0x4a, 0x00, 0x07, 0x00, 0x08,
+	0x80, 0x00, 0x30, 0x75, 0x00, 0x7e, 0x00, 0x40, 0x9c, 0x00, 0x7c, 0x00, 0x59, 0xd8, 0x00, 0x70,
+	0x00, 0xdc, 0x0b, 0x01, 0x64, 0x00, 0x80, 0x38, 0x01, 0x5a, 0x00, 0x80, 0x38, 0x01, 0x52, 0x00,
+	0x80, 0x38, 0x01, 0x4a, 0x00, 0x80, 0x38, 0x01, 0x08, 0x30, 0x75, 0x00, 0x80, 0x00, 0xa0, 0x8c,
+	0x00, 0x7e, 0x00, 0x71, 0xa5, 0x00, 0x7c, 0x00, 0xe5, 0xc8, 0x00, 0x74, 0x00, 0x91, 0xf4, 0x00,
+	0x66, 0x00, 0x40, 0x19, 0x01, 0x58, 0x00, 0x0e, 0x28, 0x01, 0x52, 0x00, 0x80, 0x38, 0x01, 0x4a,
+	0x00
+};
 
 static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
 				     struct pp_hwmgr *hwmgr)
@@ -799,12 +833,17 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
 	uint16_t size;
 
 	if (!table_addr) {
-		table_addr = cgs_atom_get_data_table(hwmgr->device,
-				GetIndexIntoMasterTable(DATA, PowerPlayInfo),
-				&size, &frev, &crev);
-
-		hwmgr->soft_pp_table = table_addr;
-		hwmgr->soft_pp_table_size = size;
+		if (hwmgr->chip_id == CHIP_RAVEN) {
+			table_addr = &soft_dummy_pp_table[0];
+			hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
+			hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
+		} else {
+			table_addr = cgs_atom_get_data_table(hwmgr->device,
+					GetIndexIntoMasterTable(DATA, PowerPlayInfo),
+					&size, &frev, &crev);
+			hwmgr->soft_pp_table = table_addr;
+			hwmgr->soft_pp_table_size = size;
+		}
 	}
 
 	return (const ATOM_PPLIB_POWERPLAYTABLE *)table_addr;
@@ -924,15 +963,14 @@ int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
 		}
 	}
 
-	if ((0 == result) &&
-		(0 != (ps->classification.flags & PP_StateClassificationFlag_Boot)))
-		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
+	if ((0 == result) && (0 != (ps->classification.flags & PP_StateClassificationFlag_Boot))) {
+		if (hwmgr->chip_family < AMDGPU_FAMILY_RV)
+			result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
+	}
 
 	return result;
 }
 
-
-
 static int init_powerplay_tables(
 			struct pp_hwmgr *hwmgr,
 			const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table
-- 
1.9.1

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[PATCH 2/4] drm/amd/powerplay: Remove obsolete code of reduced refresh rate featur

[Rex Zhu]

this feature was not supported on linux and obsolete.

Change-Id: I7434e9370e4a29489bff7feb1421e028710fbe14
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/include/pptable.h                 |  6 ------
 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 18 ------------------
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c      |  1 -
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c    |  1 -
 drivers/gpu/drm/amd/powerplay/inc/power_state.h       |  4 ----
 5 files changed, 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/pptable.h b/drivers/gpu/drm/amd/include/pptable.h
index 0b6a057..1dda72a 100644
--- a/drivers/gpu/drm/amd/include/pptable.h
+++ b/drivers/gpu/drm/amd/include/pptable.h
@@ -285,12 +285,6 @@
 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK            0x000000F8
 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT           3
 
-// lookup into reduced refresh-rate table
-#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK  0x00000F00
-#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
-
-#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED    0
-#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ         1
 // 2-15 TBD as needed.
 
 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING        0x00001000
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
index 707809b..f974832 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
@@ -680,7 +680,6 @@ static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
 							    uint8_t version,
 			 const ATOM_PPLIB_NONCLOCK_INFO *pnon_clock_info)
 {
-	unsigned long rrr_index;
 	unsigned long tmp;
 
 	ps->classification.ui_label = (le16_to_cpu(pnon_clock_info->usClassification) &
@@ -709,23 +708,6 @@ static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
 
 	ps->display.disableFrameModulation = false;
 
-	rrr_index = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
-			ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK) >>
-			ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT;
-
-	if (rrr_index != ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED) {
-		static const uint8_t look_up[(ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK >> ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT) + 1] = \
-								{ 0, 50, 0 };
-
-		ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;
-		ps->display.explicitRefreshrate = look_up[rrr_index];
-		ps->display.limitRefreshrate = true;
-
-		if (ps->display.explicitRefreshrate == 0)
-			ps->display.limitRefreshrate = false;
-	} else
-		ps->display.limitRefreshrate = false;
-
 	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
 		ATOM_PPLIB_ENABLE_VARIBRIGHT;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 736f193..27bd1a0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2990,7 +2990,6 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
 	power_state->pcie.lanes = 0;
 
 	power_state->display.disableFrameModulation = false;
-	power_state->display.limitRefreshrate = false;
 	power_state->display.enableVariBright =
 			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
 					ATOM_Tonga_ENABLE_VARIBRIGHT));
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 29e44c3..f20758f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3021,7 +3021,6 @@ static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
 					ATOM_Vega10_DISALLOW_ON_DC) != 0);
 
 	power_state->display.disableFrameModulation = false;
-	power_state->display.limitRefreshrate = false;
 	power_state->display.enableVariBright =
 			((le32_to_cpu(state_entry->ulCapsAndSettings) &
 					ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
index 827860f..44069f7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
@@ -98,10 +98,6 @@ enum PP_RefreshrateSource {
 
 struct PP_StateDisplayBlock {
 	bool              disableFrameModulation;
-	bool              limitRefreshrate;
-	enum PP_RefreshrateSource refreshrateSource;
-	int                  explicitRefreshrate;
-	int                  edidRefreshrateIndex;
 	bool              enableVariBright;
 };
 
-- 
1.9.1

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[PATCH 3/4] drm/amd/powerplay: refine pp code for raven

[Rex Zhu]

delete useless code.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Conflicts:
	drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c

Change-Id: I403457762ee4cadb357f69ed0846adfa55a9dbea
---
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 111 +++++++++----------------
 1 file changed, 37 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 4c7f430..5bbefdd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -38,19 +38,39 @@
 #include "pp_soc15.h"
 
 #define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID     5
-#define RAVEN_MINIMUM_ENGINE_CLOCK         800   //8Mhz, the low boundary of engine clock allowed on this chip
+#define RAVEN_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
 #define SCLK_MIN_DIV_INTV_SHIFT         12
-#define RAVEN_DISPCLK_BYPASS_THRESHOLD     10000 //100mhz
+#define RAVEN_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
 #define SMC_RAM_END                     0x40000
 
 static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
+
+
 int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 		struct pp_display_clock_request *clock_req);
 
 struct phm_vq_budgeting_record rv_vqtable[] = {
-	/* _TBD
-	 * CUs, SSP low, SSP High, Min Sclk Low, Min Sclk, High, AWD/non-AWD, DCLK, ECLK, Sustainable Sclk, Sustainable CUs */
-	{ 8, 0, 45, 0, 0, VQ_DisplayConfig_NoneAWD, 80000, 120000, 4, 0 },
+/* CUs, SSP low, SSP High, Display Configuration, AWD/non-AWD,
+ * Sustainable GFXCLK, Sustainable FCLK, Sustainable CUs,
+ * unused, unused, unused
+ */
+	{ 11, 30, 60, VQ_DisplayConfig_NoneAWD,  80000, 160000, 11, 0, 0, 0 },
+	{ 11, 30, 60, VQ_DisplayConfig_AWD,      80000, 160000, 11, 0, 0, 0 },
+
+	{  8, 30, 60, VQ_DisplayConfig_NoneAWD, 100000, 160000,  8, 0, 0, 0 },
+	{  8, 30, 60, VQ_DisplayConfig_AWD,     100000, 160000,  8, 0, 0, 0 },
+
+	{ 10, 12, 30, VQ_DisplayConfig_NoneAWD,  40000, 120000, 10, 0, 0, 0 },
+	{ 10, 12, 30, VQ_DisplayConfig_AWD,      40000, 120000, 10, 0, 0, 0 },
+
+	{  8, 12, 30, VQ_DisplayConfig_NoneAWD,  45000, 120000,  8, 0, 0, 0 },
+	{  8, 12, 30, VQ_DisplayConfig_AWD,      45000, 120000,  8, 0, 0, 0 },
+
+	{  6, 12, 30, VQ_DisplayConfig_NoneAWD,  45000, 120000,  6, 0, 0, 0 },
+	{  6, 12, 30, VQ_DisplayConfig_AWD,      45000, 120000,  6, 0, 0, 0 },
+
+	{  3, 12, 30, VQ_DisplayConfig_NoneAWD,  45000, 120000,  3, 0, 0, 0 },
+	{  3, 12, 30, VQ_DisplayConfig_AWD,      45000, 120000,  3, 0, 0, 0 },
 };
 
 static struct rv_power_state *cast_rv_ps(struct pp_hw_power_state *hw_ps)
@@ -109,62 +129,21 @@ static int rv_init_vq_budget_table(struct pp_hwmgr *hwmgr)
 static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 {
 	struct rv_hwmgr *rv_hwmgr = (struct rv_hwmgr *)(hwmgr->backend);
-	struct cgs_system_info sys_info = {0};
-	int result;
 
-	rv_hwmgr->ddi_power_gating_disabled = 0;
-	rv_hwmgr->bapm_enabled = 1;
 	rv_hwmgr->dce_slow_sclk_threshold = 30000;
-	rv_hwmgr->disable_driver_thermal_policy = 1;
 	rv_hwmgr->thermal_auto_throttling_treshold = 0;
 	rv_hwmgr->is_nb_dpm_enabled = 1;
 	rv_hwmgr->dpm_flags = 1;
-	rv_hwmgr->disable_smu_acp_s3_handshake = 1;
-	rv_hwmgr->disable_notify_smu_vpu_recovery = 0;
 	rv_hwmgr->gfx_off_controled_by_driver = false;
 
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_DynamicM3Arbiter);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_UVDPowerGating);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_UVDDynamicPowerGating);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_VCEPowerGating);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_SamuPowerGating);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_ACP);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_SclkDeepSleep);
 
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-				PHM_PlatformCaps_GFXDynamicMGPowerGating);
-
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 				PHM_PlatformCaps_SclkThrottleLowNotification);
 
-	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
-				PHM_PlatformCaps_DisableVoltageIsland);
-
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-					PHM_PlatformCaps_DynamicUVDState);
-
-	sys_info.size = sizeof(struct cgs_system_info);
-	sys_info.info_id = CGS_SYSTEM_INFO_PG_FLAGS;
-	result = cgs_query_system_info(hwmgr->device, &sys_info);
-	if (!result) {
-		if (sys_info.value & AMD_PG_SUPPORT_GFX_DMG)
-			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-				      PHM_PlatformCaps_GFXDynamicMGPowerGating);
-	}
-
+				PHM_PlatformCaps_PowerPlaySupport);
 	return 0;
 }
 
@@ -256,14 +235,6 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 					PPSMC_MSG_SetMinDeepSleepDcefclk,
 					clocks.dcefClockInSR / 100);
-	/*
-	if(!rv_data->isp_tileA_power_gated || !rv_data->isp_tileB_power_gated) {
-		if ((hwmgr->ispArbiter.iclk != 0) && (rv_data->ISPActualHardMinFreq != (hwmgr->ispArbiter.iclk / 100) )) {
-			smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-					PPSMC_MSG_SetHardMinIspclkByFreq, hwmgr->ispArbiter.iclk / 100);
-			rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->ISPActualHardMinFreq),
-		}
-	} */
 
 	if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
 		((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
@@ -271,7 +242,7 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
 					PPSMC_MSG_SetHardMinSocclkByFreq,
 					hwmgr->gfx_arbiter.sclk_hard_min / 100);
 			rv_read_arg_from_smc(hwmgr->smumgr, &rv_data->soc_actual_hard_min_freq);
-	}
+		}
 
 	if ((hwmgr->gfx_arbiter.gfxclk != 0) &&
 		(rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) {
@@ -292,6 +263,7 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
+
 static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
 				void *output, void *storage, int result)
 {
@@ -304,6 +276,7 @@ static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
 	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 				PPSMC_MSG_SetDisplayCount,
 				num_of_active_displays);
+
 	return 0;
 }
 
@@ -554,9 +527,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		return result;
 	}
 
-	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
-                PHM_PlatformCaps_PowerPlaySupport);
-
 	rv_populate_clock_table(hwmgr);
 
 	result = rv_get_system_info_data(hwmgr);
@@ -702,18 +672,9 @@ static int rv_dpm_get_pp_table_entry_callback(
 {
 	struct rv_power_state *rv_ps = cast_rv_ps(hw_ps);
 
-	const ATOM_PPLIB_CZ_CLOCK_INFO *rv_clock_info = clock_info;
-
-	struct phm_clock_voltage_dependency_table *table =
-				    hwmgr->dyn_state.vddc_dependency_on_sclk;
-	uint8_t clock_info_index = rv_clock_info->index;
-
-	if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
-		clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
-
-	rv_ps->levels[index].engine_clock = table->entries[clock_info_index].clk;
-	rv_ps->levels[index].vddc_index = (uint8_t)table->entries[clock_info_index].v;
+	rv_ps->levels[index].engine_clock = 0;
 
+	rv_ps->levels[index].vddc_index = 0;
 	rv_ps->level = index + 1;
 
 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
@@ -805,12 +766,12 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p
 	ps = cast_const_rv_ps(state);
 
 	level_index = index > ps->level - 1 ? ps->level - 1 : index;
-	level->coreClock = ps->levels[level_index].engine_clock;
+	level->coreClock = 30000;
 
 	if (designation == PHM_PerformanceLevelDesignation_PowerContainment) {
 		for (i = 1; i < ps->level; i++) {
 			if (ps->levels[i].engine_clock > data->dce_slow_sclk_threshold) {
-				level->coreClock = ps->levels[i].engine_clock;
+				level->coreClock = 30000;
 				break;
 			}
 		}
@@ -820,8 +781,9 @@ static int rv_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_p
 		vol_dep_record_index = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
 		level->memory_clock =
 			data->clock_vol_info.vdd_dep_on_fclk->entries[vol_dep_record_index].clk;
-	} else
+	} else {
 		level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
+	}
 
 	level->nonLocalMemoryFreq = 0;
 	level->nonLocalMemoryWidth = 0;
@@ -992,7 +954,8 @@ int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
 
 static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
 {
-	return -EINVAL;
+	clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
+	return 0;
 }
 
 static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
-- 
1.9.1

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[PATCH 4/4] drm/amd/powerplay: fix flicker issue when HDP enabled

[Rex Zhu]

cherry-pick this change from windows.

Change-Id: If6eb8b096275e32a94e9ed1568fc1466b2417ecd
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Conflicts:
	drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
---
 .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  | 14 ++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c     | 42 ++++++++++++----------
 drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h     |  4 ++-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |  2 ++
 4 files changed, 43 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index fcc722e..967f50f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -323,6 +323,9 @@ int phm_check_states_equal(struct pp_hwmgr *hwmgr,
 int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 		    const struct amd_pp_display_configuration *display_config)
 {
+	int index = 0;
+	int number_of_active_display = 0;
+
 	PHM_FUNC_CHECK(hwmgr);
 
 	if (display_config == NULL)
@@ -330,6 +333,17 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
 
 	hwmgr->display_config = *display_config;
 
+	if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
+		hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, hwmgr->display_config.min_dcef_deep_sleep_set_clk);
+
+	for (index = 0; index < hwmgr->display_config.num_path_including_non_display; index++) {
+		if (hwmgr->display_config.displays[index].controller_id != 0)
+			number_of_active_display++;
+	}
+
+	if (NULL != hwmgr->hwmgr_func->set_active_display_count)
+		hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
+
 	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
 		return -EINVAL;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 5bbefdd..a5fa546 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -135,6 +135,9 @@ static int rv_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 	rv_hwmgr->is_nb_dpm_enabled = 1;
 	rv_hwmgr->dpm_flags = 1;
 	rv_hwmgr->gfx_off_controled_by_driver = false;
+	rv_hwmgr->need_min_deep_sleep_dcefclk = true;
+	rv_hwmgr->num_active_display = 0;
+	rv_hwmgr->deep_sleep_dcefclk = 0;
 
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 					PHM_PlatformCaps_SclkDeepSleep);
@@ -225,17 +228,9 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
 	clock_req.clock_type = amd_pp_dcf_clock;
 	clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 
-	if (clocks.dcefClock == 0 && clocks.dcefClockInSR == 0)
-		clock_req.clock_freq_in_khz = rv_data->dcf_actual_hard_min_freq;
-
 	PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req),
 				"Attempt to set DCF Clock Failed!", return -EINVAL);
 
-	if(rv_data->need_min_deep_sleep_dcefclk && 0 != clocks.dcefClockInSR)
-		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-					PPSMC_MSG_SetMinDeepSleepDcefclk,
-					clocks.dcefClockInSR / 100);
-
 	if((hwmgr->gfx_arbiter.sclk_hard_min != 0) &&
 		((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) {
 		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
@@ -263,26 +258,35 @@ static int rv_tf_set_clock_limit(struct pp_hwmgr *hwmgr, void *input,
 	return 0;
 }
 
-
-static int rv_tf_set_num_active_display(struct pp_hwmgr *hwmgr, void *input,
-				void *output, void *storage, int result)
+static int rv_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
 {
-	uint32_t  num_of_active_displays = 0;
-	struct cgs_display_info info = {0};
+	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 
-	cgs_get_active_displays_info(hwmgr->device, &info);
-	num_of_active_displays = info.display_count;
+	if (rv_data->need_min_deep_sleep_dcefclk && rv_data->deep_sleep_dcefclk != clock/100) {
+		rv_data->deep_sleep_dcefclk = clock/100;
+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+					PPSMC_MSG_SetMinDeepSleepDcefclk,
+					rv_data->deep_sleep_dcefclk);
+	}
+	return 0;
+}
+
+static int rv_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
+{
+	struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
 
-	smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+	if (rv_data->num_active_display != count) {
+		rv_data->num_active_display = count;
+		smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
 				PPSMC_MSG_SetDisplayCount,
-				num_of_active_displays);
+				rv_data->num_active_display);
+	}
 
 	return 0;
 }
 
 static const struct phm_master_table_item rv_set_power_state_list[] = {
 	{ NULL, rv_tf_set_clock_limit },
-	{ NULL, rv_tf_set_num_active_display },
 	{ }
 };
 
@@ -1012,6 +1016,8 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	.get_clock_by_type_with_voltage = rv_get_clock_by_type_with_voltage,
 	.get_max_high_clocks = rv_get_max_high_clocks,
 	.read_sensor = rv_read_sensor,
+	.set_active_display_count = rv_set_active_display_count,
+	.set_deep_sleep_dcefclk = rv_set_deep_sleep_dcefclk,
 };
 
 int rv_init_function_pointers(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index afb8522..228e0cf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -291,7 +291,9 @@ struct rv_hwmgr {
 	DpmClocks_t                       clock_table;
 
 	uint32_t active_process_mask;
-	bool need_min_deep_sleep_dcefclk; /* disabled by default */
+	bool need_min_deep_sleep_dcefclk;
+	uint32_t                             deep_sleep_dcefclk;
+	uint32_t                             num_active_display;
 };
 
 struct pp_hwmgr;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 47e57bd..990d156 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -376,6 +376,8 @@ struct pp_hwmgr_func {
 			struct amd_pp_profile *request);
 	int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
 	int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
+	int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
+	int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
 };
 
 struct pp_table_func {
-- 
1.9.1

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RE: [PATCH 2/4] drm/amd/powerplay: Remove obsolete code of reduced refresh rate featur

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Friday, August 25, 2017 5:27 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 2/4] drm/amd/powerplay: Remove obsolete code of
> reduced refresh rate featur

Typo in patch title:  featur -> feature

With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> 
> this feature was not supported on linux and obsolete.
> 
> Change-Id: I7434e9370e4a29489bff7feb1421e028710fbe14
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/include/pptable.h                 |  6 ------
>  drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c | 18 -------------
> -----
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c      |  1 -
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c    |  1 -
>  drivers/gpu/drm/amd/powerplay/inc/power_state.h       |  4 ----
>  5 files changed, 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/pptable.h
> b/drivers/gpu/drm/amd/include/pptable.h
> index 0b6a057..1dda72a 100644
> --- a/drivers/gpu/drm/amd/include/pptable.h
> +++ b/drivers/gpu/drm/amd/include/pptable.h
> @@ -285,12 +285,6 @@
>  #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK            0x000000F8
>  #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT           3
> 
> -// lookup into reduced refresh-rate table
> -#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK  0x00000F00
> -#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
> -
> -#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED    0
> -#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ         1
>  // 2-15 TBD as needed.
> 
>  #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING
> 0x00001000
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> index 707809b..f974832 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
> @@ -680,7 +680,6 @@ static int init_non_clock_fields(struct pp_hwmgr
> *hwmgr,
>  							    uint8_t version,
>  			 const ATOM_PPLIB_NONCLOCK_INFO
> *pnon_clock_info)
>  {
> -	unsigned long rrr_index;
>  	unsigned long tmp;
> 
>  	ps->classification.ui_label = (le16_to_cpu(pnon_clock_info-
> >usClassification) &
> @@ -709,23 +708,6 @@ static int init_non_clock_fields(struct pp_hwmgr
> *hwmgr,
> 
>  	ps->display.disableFrameModulation = false;
> 
> -	rrr_index = (le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
> -
> 	ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK) >>
> -			ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT;
> -
> -	if (rrr_index != ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED) {
> -		static const uint8_t
> look_up[(ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK >>
> ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT) + 1] = \
> -								{ 0, 50, 0 };
> -
> -		ps->display.refreshrateSource =
> PP_RefreshrateSource_Explicit;
> -		ps->display.explicitRefreshrate = look_up[rrr_index];
> -		ps->display.limitRefreshrate = true;
> -
> -		if (ps->display.explicitRefreshrate == 0)
> -			ps->display.limitRefreshrate = false;
> -	} else
> -		ps->display.limitRefreshrate = false;
> -
>  	tmp = le32_to_cpu(pnon_clock_info->ulCapsAndSettings) &
>  		ATOM_PPLIB_ENABLE_VARIBRIGHT;
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 736f193..27bd1a0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2990,7 +2990,6 @@ static int
> smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
>  	power_state->pcie.lanes = 0;
> 
>  	power_state->display.disableFrameModulation = false;
> -	power_state->display.limitRefreshrate = false;
>  	power_state->display.enableVariBright =
>  			(0 != (le32_to_cpu(state_entry->ulCapsAndSettings)
> &
> 
> 	ATOM_Tonga_ENABLE_VARIBRIGHT));
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 29e44c3..f20758f 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3021,7 +3021,6 @@ static int
> vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
>  					ATOM_Vega10_DISALLOW_ON_DC)
> != 0);
> 
>  	power_state->display.disableFrameModulation = false;
> -	power_state->display.limitRefreshrate = false;
>  	power_state->display.enableVariBright =
>  			((le32_to_cpu(state_entry->ulCapsAndSettings) &
> 
> 	ATOM_Vega10_ENABLE_VARIBRIGHT) != 0);
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
> b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
> index 827860f..44069f7 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/power_state.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/power_state.h
> @@ -98,10 +98,6 @@ enum PP_RefreshrateSource {
> 
>  struct PP_StateDisplayBlock {
>  	bool              disableFrameModulation;
> -	bool              limitRefreshrate;
> -	enum PP_RefreshrateSource refreshrateSource;
> -	int                  explicitRefreshrate;
> -	int                  edidRefreshrateIndex;
>  	bool              enableVariBright;
>  };
> 
> --
> 1.9.1
> 
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