* add gfx capability by gpu info
@ 2017-02-16 2:53 Junwei Zhang
[not found] ` <1487213588-26299-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 10+ messages in thread
From: Junwei Zhang @ 2017-02-16 2:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Vulkan needs to read the gfx hw capability info via gpu info.
According to the vaule, get different performance from device to device.
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^ permalink raw reply [flat|nested] 10+ messages in thread[parent not found: <1487213588-26299-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <1487213588-26299-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> @ 2017-02-16 2:53 ` Junwei Zhang [not found] ` <1487213588-26299-2-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Junwei Zhang @ 2017-02-16 2:53 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Junwei Zhang Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ include/uapi/drm/amdgpu_drm.h | 1 + 6 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 1ad3f08..cdc2b2a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); }; +struct amdgpu_gfx_cap { + uint32_t gc_double_offchip_lds_buf; +}; + struct amdgpu_gfx { struct mutex gpu_clock_mutex; struct amdgpu_gca_config config; @@ -911,6 +915,8 @@ struct amdgpu_gfx { /* reset mask */ uint32_t grbm_soft_reset; uint32_t srbm_soft_reset; + + struct amdgpu_gfx_cap cap; }; int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 7f59608..e7aa382 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; cap.direct_gma_size = amdgpu_direct_gma_size; } + cap.gc_double_offchip_lds_buf = + adev->gfx.cap.gc_double_offchip_lds_buf; return copy_to_user(out, &cap, min((size_t)size, sizeof(cap))) ? -EFAULT : 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index ce75d46..a1e221b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, mutex_unlock(&adev->grbm_idx_mutex); } +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) +{ + adev->gfx.cap.gc_double_offchip_lds_buf = 1; +} + static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) { u32 gb_addr_config = 0; @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) adev->gfx.config.max_cu_per_sh); gfx_v6_0_get_cu_info(adev); + gfx_v6_0_cap_init(adev); WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index aaf66fe..e1e97ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); } +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) +{ + adev->gfx.cap.gc_double_offchip_lds_buf = 1; +} + /** * gfx_v7_0_gpu_init - setup the 3D engine * @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) gfx_v7_0_setup_rb(adev); gfx_v7_0_get_cu_info(adev); + gfx_v7_0_cap_init(adev); /* set HW defaults for 3D engine */ WREG32(mmCP_MEQ_THRESHOLDS, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index ce05e38..934fc71 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) mutex_unlock(&adev->srbm_mutex); } +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) +{ + switch (adev->asic_type) { + default: + adev->gfx.cap.gc_double_offchip_lds_buf = 1; + break; + case CHIP_CARRIZO: + case CHIP_STONEY: + adev->gfx.cap.gc_double_offchip_lds_buf = 0; + break; + } +} + static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) { u32 tmp, sh_static_mem_cfg; @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) gfx_v8_0_tiling_mode_table_init(adev); gfx_v8_0_setup_rb(adev); gfx_v8_0_get_cu_info(adev); + gfx_v8_0_cap_init(adev); /* XXX SH_MEM regs */ /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 04daab3..7064fdc 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { struct drm_amdgpu_capability { __u32 flag; __u32 direct_gma_size; + __u32 gc_double_offchip_lds_buf; }; /* -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <1487213588-26299-2-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <1487213588-26299-2-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> @ 2017-02-16 4:37 ` Edward O'Callaghan [not found] ` <2ee3024b-cd44-9fd6-62f7-fb8117dd2e74-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org> 2017-02-16 9:11 ` Christian König 1 sibling, 1 reply; 10+ messages in thread From: Edward O'Callaghan @ 2017-02-16 4:37 UTC (permalink / raw) To: Junwei Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW [-- Attachment #1.1.1: Type: text/plain, Size: 5559 bytes --] Hi, Question, is this a bit premature to have a new function and struct for this, could it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to start growing quickly with far more cap state info? Kind Regards, Edward. On 02/16/2017 01:53 PM, Junwei Zhang wrote: > Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a > Signed-off-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ > include/uapi/drm/amdgpu_drm.h | 1 + > 6 files changed, 35 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 1ad3f08..cdc2b2a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { > void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); > }; > > +struct amdgpu_gfx_cap { > + uint32_t gc_double_offchip_lds_buf; > +}; > + > struct amdgpu_gfx { > struct mutex gpu_clock_mutex; > struct amdgpu_gca_config config; > @@ -911,6 +915,8 @@ struct amdgpu_gfx { > /* reset mask */ > uint32_t grbm_soft_reset; > uint32_t srbm_soft_reset; > + > + struct amdgpu_gfx_cap cap; > }; > > int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index 7f59608..e7aa382 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file > cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; > cap.direct_gma_size = amdgpu_direct_gma_size; > } > + cap.gc_double_offchip_lds_buf = > + adev->gfx.cap.gc_double_offchip_lds_buf; > return copy_to_user(out, &cap, > min((size_t)size, sizeof(cap))) ? -EFAULT : 0; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > index ce75d46..a1e221b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, > mutex_unlock(&adev->grbm_idx_mutex); > } > > +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) > +{ > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > +} > + > static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) > { > u32 gb_addr_config = 0; > @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) > adev->gfx.config.max_cu_per_sh); > > gfx_v6_0_get_cu_info(adev); > + gfx_v6_0_cap_init(adev); > > WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | > (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index aaf66fe..e1e97ae 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) > mutex_unlock(&adev->srbm_mutex); > } > > +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) > +{ > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > +} > + > /** > * gfx_v7_0_gpu_init - setup the 3D engine > * > @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) > > gfx_v7_0_setup_rb(adev); > gfx_v7_0_get_cu_info(adev); > + gfx_v7_0_cap_init(adev); > > /* set HW defaults for 3D engine */ > WREG32(mmCP_MEQ_THRESHOLDS, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index ce05e38..934fc71 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) > mutex_unlock(&adev->srbm_mutex); > } > > +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) > +{ > + switch (adev->asic_type) { > + default: > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > + break; > + case CHIP_CARRIZO: > + case CHIP_STONEY: > + adev->gfx.cap.gc_double_offchip_lds_buf = 0; > + break; > + } > +} > + > static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > { > u32 tmp, sh_static_mem_cfg; > @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > gfx_v8_0_tiling_mode_table_init(adev); > gfx_v8_0_setup_rb(adev); > gfx_v8_0_get_cu_info(adev); > + gfx_v8_0_cap_init(adev); > > /* XXX SH_MEM regs */ > /* where to put LDS, scratch, GPUVM in FSA64 space */ > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index 04daab3..7064fdc 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { > struct drm_amdgpu_capability { > __u32 flag; > __u32 direct_gma_size; > + __u32 gc_double_offchip_lds_buf; > }; > > /* > [-- Attachment #1.2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <2ee3024b-cd44-9fd6-62f7-fb8117dd2e74-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>]
* RE: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <2ee3024b-cd44-9fd6-62f7-fb8117dd2e74-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org> @ 2017-02-16 5:46 ` Zhang, Jerry [not found] ` <BN6PR12MB1809B9E0ECE9A87C21C92A41FF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Zhang, Jerry @ 2017-02-16 5:46 UTC (permalink / raw) To: Edward O'Callaghan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Hi Edward, > Question, is this a bit premature to have a new function and struct for this, could > it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to > start growing quickly with far more cap state info? Yes, we will add more in the future. Ideally we'd like to add a feature structure to export all supported by current amdgpu_device. Now it's only one for gfx, so I insert a structure in amdgpu_gfx, which was verified by vulkan carrizo. Then I send it out for guys review whether to add in the amdgpu_device directly or keep current style till we have other features besides gfx. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _____________________________________ > -----Original Message----- > From: Edward O'Callaghan [mailto:funfunctor@folklore1984.net] > Sent: Thursday, February 16, 2017 12:38 > To: Zhang, Jerry; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info > > Hi, > > Question, is this a bit premature to have a new function and struct for this, could > it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to > start growing quickly with far more cap state info? > > Kind Regards, > Edward. > > On 02/16/2017 01:53 PM, Junwei Zhang wrote: > > Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a > > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ > > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ > > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ > > include/uapi/drm/amdgpu_drm.h | 1 + > > 6 files changed, 35 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > index 1ad3f08..cdc2b2a 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { > > void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, > > uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); }; > > > > +struct amdgpu_gfx_cap { > > + uint32_t gc_double_offchip_lds_buf; > > +}; > > + > > struct amdgpu_gfx { > > struct mutex gpu_clock_mutex; > > struct amdgpu_gca_config config; > > @@ -911,6 +915,8 @@ struct amdgpu_gfx { > > /* reset mask */ > > uint32_t grbm_soft_reset; > > uint32_t srbm_soft_reset; > > + > > + struct amdgpu_gfx_cap cap; > > }; > > > > int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > index 7f59608..e7aa382 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, > void *data, struct drm_file > > cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; > > cap.direct_gma_size = amdgpu_direct_gma_size; > > } > > + cap.gc_double_offchip_lds_buf = > > + adev->gfx.cap.gc_double_offchip_lds_buf; > > return copy_to_user(out, &cap, > > min((size_t)size, sizeof(cap))) ? -EFAULT : 0; > > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > index ce75d46..a1e221b 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct > amdgpu_device *adev, > > mutex_unlock(&adev->grbm_idx_mutex); > > } > > > > +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) { > > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } > > + > > static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) { > > u32 gb_addr_config = 0; > > @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device > *adev) > > adev->gfx.config.max_cu_per_sh); > > > > gfx_v6_0_get_cu_info(adev); > > + gfx_v6_0_cap_init(adev); > > > > WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << > CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | > > (0x2b << > CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > index aaf66fe..e1e97ae 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct > amdgpu_device *adev) > > mutex_unlock(&adev->srbm_mutex); > > } > > > > +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) { > > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } > > + > > /** > > * gfx_v7_0_gpu_init - setup the 3D engine > > * > > @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct > > amdgpu_device *adev) > > > > gfx_v7_0_setup_rb(adev); > > gfx_v7_0_get_cu_info(adev); > > + gfx_v7_0_cap_init(adev); > > > > /* set HW defaults for 3D engine */ > > WREG32(mmCP_MEQ_THRESHOLDS, > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > index ce05e38..934fc71 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct > amdgpu_device *adev) > > mutex_unlock(&adev->srbm_mutex); > > } > > > > +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) { > > + switch (adev->asic_type) { > > + default: > > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > > + break; > > + case CHIP_CARRIZO: > > + case CHIP_STONEY: > > + adev->gfx.cap.gc_double_offchip_lds_buf = 0; > > + break; > > + } > > +} > > + > > static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) { > > u32 tmp, sh_static_mem_cfg; > > @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device > *adev) > > gfx_v8_0_tiling_mode_table_init(adev); > > gfx_v8_0_setup_rb(adev); > > gfx_v8_0_get_cu_info(adev); > > + gfx_v8_0_cap_init(adev); > > > > /* XXX SH_MEM regs */ > > /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git > > a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index > > 04daab3..7064fdc 100644 > > --- a/include/uapi/drm/amdgpu_drm.h > > +++ b/include/uapi/drm/amdgpu_drm.h > > @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { struct > > drm_amdgpu_capability { > > __u32 flag; > > __u32 direct_gma_size; > > + __u32 gc_double_offchip_lds_buf; > > }; > > > > /* > > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <BN6PR12MB1809B9E0ECE9A87C21C92A41FF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <BN6PR12MB1809B9E0ECE9A87C21C92A41FF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2017-02-16 7:17 ` Edward O'Callaghan 0 siblings, 0 replies; 10+ messages in thread From: Edward O'Callaghan @ 2017-02-16 7:17 UTC (permalink / raw) To: Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW [-- Attachment #1.1.1: Type: text/plain, Size: 7208 bytes --] On 02/16/2017 04:46 PM, Zhang, Jerry wrote: > Hi Edward, > >> Question, is this a bit premature to have a new function and struct for this, could >> it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to >> start growing quickly with far more cap state info? > Yes, we will add more in the future. > > Ideally we'd like to add a feature structure to export all supported by current amdgpu_device. > Now it's only one for gfx, so I insert a structure in amdgpu_gfx, which was verified by vulkan carrizo. > Then I send it out for guys review whether to add in the amdgpu_device directly > or keep current style till we have other features besides gfx. Hmmk, its nothing to stress about I was just more curious about it. Reviewed-by: Edward O'Callaghan <funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org> Kindly, Edward. > > Regards, > Jerry (Junwei Zhang) > > Linux Base Graphics > SRDC Software Development > _____________________________________ > > >> -----Original Message----- >> From: Edward O'Callaghan [mailto:funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org] >> Sent: Thursday, February 16, 2017 12:38 >> To: Zhang, Jerry; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org >> Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info >> >> Hi, >> >> Question, is this a bit premature to have a new function and struct for this, could >> it just be put in amdgpu_gfx for now or are we expecting amdgpu_gfx_cap to >> start growing quickly with far more cap state info? >> >> Kind Regards, >> Edward. >> >> On 02/16/2017 01:53 PM, Junwei Zhang wrote: >>> Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a >>> Signed-off-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ >>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ >>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ >>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ >>> include/uapi/drm/amdgpu_drm.h | 1 + >>> 6 files changed, 35 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> index 1ad3f08..cdc2b2a 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { >>> void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, >>> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); }; >>> >>> +struct amdgpu_gfx_cap { >>> + uint32_t gc_double_offchip_lds_buf; >>> +}; >>> + >>> struct amdgpu_gfx { >>> struct mutex gpu_clock_mutex; >>> struct amdgpu_gca_config config; >>> @@ -911,6 +915,8 @@ struct amdgpu_gfx { >>> /* reset mask */ >>> uint32_t grbm_soft_reset; >>> uint32_t srbm_soft_reset; >>> + >>> + struct amdgpu_gfx_cap cap; >>> }; >>> >>> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> index 7f59608..e7aa382 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, >> void *data, struct drm_file >>> cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; >>> cap.direct_gma_size = amdgpu_direct_gma_size; >>> } >>> + cap.gc_double_offchip_lds_buf = >>> + adev->gfx.cap.gc_double_offchip_lds_buf; >>> return copy_to_user(out, &cap, >>> min((size_t)size, sizeof(cap))) ? -EFAULT : 0; >>> } >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> index ce75d46..a1e221b 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct >> amdgpu_device *adev, >>> mutex_unlock(&adev->grbm_idx_mutex); >>> } >>> >>> +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) { >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } >>> + >>> static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) { >>> u32 gb_addr_config = 0; >>> @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device >> *adev) >>> adev->gfx.config.max_cu_per_sh); >>> >>> gfx_v6_0_get_cu_info(adev); >>> + gfx_v6_0_cap_init(adev); >>> >>> WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << >> CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | >>> (0x2b << >> CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> index aaf66fe..e1e97ae 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct >> amdgpu_device *adev) >>> mutex_unlock(&adev->srbm_mutex); >>> } >>> >>> +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) { >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } >>> + >>> /** >>> * gfx_v7_0_gpu_init - setup the 3D engine >>> * >>> @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct >>> amdgpu_device *adev) >>> >>> gfx_v7_0_setup_rb(adev); >>> gfx_v7_0_get_cu_info(adev); >>> + gfx_v7_0_cap_init(adev); >>> >>> /* set HW defaults for 3D engine */ >>> WREG32(mmCP_MEQ_THRESHOLDS, >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> index ce05e38..934fc71 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct >> amdgpu_device *adev) >>> mutex_unlock(&adev->srbm_mutex); >>> } >>> >>> +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) { >>> + switch (adev->asic_type) { >>> + default: >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; >>> + break; >>> + case CHIP_CARRIZO: >>> + case CHIP_STONEY: >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 0; >>> + break; >>> + } >>> +} >>> + >>> static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) { >>> u32 tmp, sh_static_mem_cfg; >>> @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device >> *adev) >>> gfx_v8_0_tiling_mode_table_init(adev); >>> gfx_v8_0_setup_rb(adev); >>> gfx_v8_0_get_cu_info(adev); >>> + gfx_v8_0_cap_init(adev); >>> >>> /* XXX SH_MEM regs */ >>> /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git >>> a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index >>> 04daab3..7064fdc 100644 >>> --- a/include/uapi/drm/amdgpu_drm.h >>> +++ b/include/uapi/drm/amdgpu_drm.h >>> @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { struct >>> drm_amdgpu_capability { >>> __u32 flag; >>> __u32 direct_gma_size; >>> + __u32 gc_double_offchip_lds_buf; >>> }; >>> >>> /* >>> > [-- Attachment #1.2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 819 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <1487213588-26299-2-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> 2017-02-16 4:37 ` Edward O'Callaghan @ 2017-02-16 9:11 ` Christian König [not found] ` <2bae755f-f1e2-57de-257c-e1d155723122-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 1 sibling, 1 reply; 10+ messages in thread From: Christian König @ 2017-02-16 9:11 UTC (permalink / raw) To: Junwei Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 16.02.2017 um 03:53 schrieb Junwei Zhang: > Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Complete NAK on this. The drm_amdgpu_capability structure is specific to the pro driver. The Vulkan stack on the other hand is supposed to work on the open stack as well. So please but that into the drm_amdgpu_info_device structure and the new field in the amdgpu_gca_config structure (you might as well want to rename the amdgpu_gca_config structure). Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ > include/uapi/drm/amdgpu_drm.h | 1 + > 6 files changed, 35 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 1ad3f08..cdc2b2a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { > void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); > }; > > +struct amdgpu_gfx_cap { > + uint32_t gc_double_offchip_lds_buf; > +}; > + > struct amdgpu_gfx { > struct mutex gpu_clock_mutex; > struct amdgpu_gca_config config; > @@ -911,6 +915,8 @@ struct amdgpu_gfx { > /* reset mask */ > uint32_t grbm_soft_reset; > uint32_t srbm_soft_reset; > + > + struct amdgpu_gfx_cap cap; > }; > > int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > index 7f59608..e7aa382 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file > cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; > cap.direct_gma_size = amdgpu_direct_gma_size; > } > + cap.gc_double_offchip_lds_buf = > + adev->gfx.cap.gc_double_offchip_lds_buf; > return copy_to_user(out, &cap, > min((size_t)size, sizeof(cap))) ? -EFAULT : 0; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > index ce75d46..a1e221b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev, > mutex_unlock(&adev->grbm_idx_mutex); > } > > +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) > +{ > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > +} > + > static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) > { > u32 gb_addr_config = 0; > @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) > adev->gfx.config.max_cu_per_sh); > > gfx_v6_0_get_cu_info(adev); > + gfx_v6_0_cap_init(adev); > > WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | > (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index aaf66fe..e1e97ae 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev) > mutex_unlock(&adev->srbm_mutex); > } > > +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) > +{ > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > +} > + > /** > * gfx_v7_0_gpu_init - setup the 3D engine > * > @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) > > gfx_v7_0_setup_rb(adev); > gfx_v7_0_get_cu_info(adev); > + gfx_v7_0_cap_init(adev); > > /* set HW defaults for 3D engine */ > WREG32(mmCP_MEQ_THRESHOLDS, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index ce05e38..934fc71 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) > mutex_unlock(&adev->srbm_mutex); > } > > +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) > +{ > + switch (adev->asic_type) { > + default: > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > + break; > + case CHIP_CARRIZO: > + case CHIP_STONEY: > + adev->gfx.cap.gc_double_offchip_lds_buf = 0; > + break; > + } > +} > + > static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > { > u32 tmp, sh_static_mem_cfg; > @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > gfx_v8_0_tiling_mode_table_init(adev); > gfx_v8_0_setup_rb(adev); > gfx_v8_0_get_cu_info(adev); > + gfx_v8_0_cap_init(adev); > > /* XXX SH_MEM regs */ > /* where to put LDS, scratch, GPUVM in FSA64 space */ > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index 04daab3..7064fdc 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { > struct drm_amdgpu_capability { > __u32 flag; > __u32 direct_gma_size; > + __u32 gc_double_offchip_lds_buf; > }; > > /* _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <2bae755f-f1e2-57de-257c-e1d155723122-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* RE: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <2bae755f-f1e2-57de-257c-e1d155723122-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2017-02-16 9:24 ` Zhang, Jerry [not found] ` <BN6PR12MB18098E6B408580D7847D84EBFF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Zhang, Jerry @ 2017-02-16 9:24 UTC (permalink / raw) To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW > -----Original Message----- > From: Christian König [mailto:deathsimple@vodafone.de] > Sent: Thursday, February 16, 2017 17:12 > To: Zhang, Jerry; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info > > Am 16.02.2017 um 03:53 schrieb Junwei Zhang: > > Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a > > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> > > Complete NAK on this. The drm_amdgpu_capability structure is specific to the > pro driver. Thanks to reminder it. I neglect it. > > The Vulkan stack on the other hand is supposed to work on the open stack as > well. > > So please but that into the drm_amdgpu_info_device structure and the new field > in the amdgpu_gca_config structure (you might as well want to rename the > amdgpu_gca_config structure). So you mean add the feature or config structure in amdgpu_device directly from now on. Right? Could you explain the meaning about gca? BTW, 1) in the future we may add more feature/config in the same structure, but may not for gfx. 2) Shall we add a version to control these features? UMD could know the features status according to the version. > > Regards, > Christian. > > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ > > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ > > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ > > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ > > include/uapi/drm/amdgpu_drm.h | 1 + > > 6 files changed, 35 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > index 1ad3f08..cdc2b2a 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > > @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { > > void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, > uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); > > }; > > > > +struct amdgpu_gfx_cap { > > + uint32_t gc_double_offchip_lds_buf; > > +}; > > + > > struct amdgpu_gfx { > > struct mutex gpu_clock_mutex; > > struct amdgpu_gca_config config; > > @@ -911,6 +915,8 @@ struct amdgpu_gfx { > > /* reset mask */ > > uint32_t grbm_soft_reset; > > uint32_t srbm_soft_reset; > > + > > + struct amdgpu_gfx_cap cap; > > }; > > > > int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > index 7f59608..e7aa382 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > > @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, > void *data, struct drm_file > > cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; > > cap.direct_gma_size = amdgpu_direct_gma_size; > > } > > + cap.gc_double_offchip_lds_buf = > > + adev->gfx.cap.gc_double_offchip_lds_buf; > > return copy_to_user(out, &cap, > > min((size_t)size, sizeof(cap))) ? -EFAULT : 0; > > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > index ce75d46..a1e221b 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct > amdgpu_device *adev, > > mutex_unlock(&adev->grbm_idx_mutex); > > } > > > > +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) { > > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } > > + > > static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) > > { > > u32 gb_addr_config = 0; > > @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device > *adev) > > adev->gfx.config.max_cu_per_sh); > > > > gfx_v6_0_get_cu_info(adev); > > + gfx_v6_0_cap_init(adev); > > > > WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << > CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | > > (0x2b << > CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > index aaf66fe..e1e97ae 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct > amdgpu_device *adev) > > mutex_unlock(&adev->srbm_mutex); > > } > > > > +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) { > > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } > > + > > /** > > * gfx_v7_0_gpu_init - setup the 3D engine > > * > > @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct > > amdgpu_device *adev) > > > > gfx_v7_0_setup_rb(adev); > > gfx_v7_0_get_cu_info(adev); > > + gfx_v7_0_cap_init(adev); > > > > /* set HW defaults for 3D engine */ > > WREG32(mmCP_MEQ_THRESHOLDS, > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > index ce05e38..934fc71 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct > amdgpu_device *adev) > > mutex_unlock(&adev->srbm_mutex); > > } > > > > +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) { > > + switch (adev->asic_type) { > > + default: > > + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > > + break; > > + case CHIP_CARRIZO: > > + case CHIP_STONEY: > > + adev->gfx.cap.gc_double_offchip_lds_buf = 0; > > + break; > > + } > > +} > > + > > static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > > { > > u32 tmp, sh_static_mem_cfg; > > @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device > *adev) > > gfx_v8_0_tiling_mode_table_init(adev); > > gfx_v8_0_setup_rb(adev); > > gfx_v8_0_get_cu_info(adev); > > + gfx_v8_0_cap_init(adev); > > > > /* XXX SH_MEM regs */ > > /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git > > a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index > > 04daab3..7064fdc 100644 > > --- a/include/uapi/drm/amdgpu_drm.h > > +++ b/include/uapi/drm/amdgpu_drm.h > > @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { > > struct drm_amdgpu_capability { > > __u32 flag; > > __u32 direct_gma_size; > > + __u32 gc_double_offchip_lds_buf; > > }; > > > > /* > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <BN6PR12MB18098E6B408580D7847D84EBFF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <BN6PR12MB18098E6B408580D7847D84EBFF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2017-02-16 9:36 ` Christian König [not found] ` <ea0dbd80-8ebf-908f-3d7f-78501b06fc53-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Christian König @ 2017-02-16 9:36 UTC (permalink / raw) To: Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 16.02.2017 um 10:24 schrieb Zhang, Jerry: >> -----Original Message----- >> From: Christian König [mailto:deathsimple@vodafone.de] >> Sent: Thursday, February 16, 2017 17:12 >> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org >> Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info >> >> Am 16.02.2017 um 03:53 schrieb Junwei Zhang: >>> Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a >>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> >> Complete NAK on this. The drm_amdgpu_capability structure is specific to the >> pro driver. > Thanks to reminder it. > I neglect it. > >> The Vulkan stack on the other hand is supposed to work on the open stack as >> well. >> >> So please but that into the drm_amdgpu_info_device structure and the new field >> in the amdgpu_gca_config structure (you might as well want to rename the >> amdgpu_gca_config structure). > So you mean add the feature or config structure in amdgpu_device directly from now on. > Right? No, just forget about the config or feature structure. Add gfx features to amdgpu_gca_config. > Could you explain the meaning about gca? I just think that the naming isn't the best, something like amdgpu_gfx_config would probably be better. > > BTW, > 1) in the future we may add more feature/config in the same structure, but may not for gfx. Stop, that is really bad design. The features/config should be kept on a per IP basis. So gfx config/features should only be grouped together with gfx features. Don't mix features from different block inside the kernel module. The IOCTL interface is a different story, here we have the drm_amdgpu_info_device structure for information about the whole GPU as well as individual structures about each IP block (like firmware versions etc...). For the current case adding that to drm_amdgpu_info_device sounds like the right approach to me. > 2) Shall we add a version to control these features? UMD could know the features status according to the version. No, the size of the drm_amdgpu_info_device structure is already version controlled. Just make sure that the default value is zero, this way you keep backward compatible with older kernel interfaces. Regards, Christian. > >> Regards, >> Christian. >> >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ >>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ >>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ >>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ >>> include/uapi/drm/amdgpu_drm.h | 1 + >>> 6 files changed, 35 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> index 1ad3f08..cdc2b2a 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { >>> void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, >> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); >>> }; >>> >>> +struct amdgpu_gfx_cap { >>> + uint32_t gc_double_offchip_lds_buf; >>> +}; >>> + >>> struct amdgpu_gfx { >>> struct mutex gpu_clock_mutex; >>> struct amdgpu_gca_config config; >>> @@ -911,6 +915,8 @@ struct amdgpu_gfx { >>> /* reset mask */ >>> uint32_t grbm_soft_reset; >>> uint32_t srbm_soft_reset; >>> + >>> + struct amdgpu_gfx_cap cap; >>> }; >>> >>> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> index 7f59608..e7aa382 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>> @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, >> void *data, struct drm_file >>> cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; >>> cap.direct_gma_size = amdgpu_direct_gma_size; >>> } >>> + cap.gc_double_offchip_lds_buf = >>> + adev->gfx.cap.gc_double_offchip_lds_buf; >>> return copy_to_user(out, &cap, >>> min((size_t)size, sizeof(cap))) ? -EFAULT : 0; >>> } >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> index ce75d46..a1e221b 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>> @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct >> amdgpu_device *adev, >>> mutex_unlock(&adev->grbm_idx_mutex); >>> } >>> >>> +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) { >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } >>> + >>> static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) >>> { >>> u32 gb_addr_config = 0; >>> @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct amdgpu_device >> *adev) >>> adev->gfx.config.max_cu_per_sh); >>> >>> gfx_v6_0_get_cu_info(adev); >>> + gfx_v6_0_cap_init(adev); >>> >>> WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << >> CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | >>> (0x2b << >> CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> index aaf66fe..e1e97ae 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>> @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct >> amdgpu_device *adev) >>> mutex_unlock(&adev->srbm_mutex); >>> } >>> >>> +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) { >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } >>> + >>> /** >>> * gfx_v7_0_gpu_init - setup the 3D engine >>> * >>> @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct >>> amdgpu_device *adev) >>> >>> gfx_v7_0_setup_rb(adev); >>> gfx_v7_0_get_cu_info(adev); >>> + gfx_v7_0_cap_init(adev); >>> >>> /* set HW defaults for 3D engine */ >>> WREG32(mmCP_MEQ_THRESHOLDS, >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> index ce05e38..934fc71 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>> @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct >> amdgpu_device *adev) >>> mutex_unlock(&adev->srbm_mutex); >>> } >>> >>> +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) { >>> + switch (adev->asic_type) { >>> + default: >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; >>> + break; >>> + case CHIP_CARRIZO: >>> + case CHIP_STONEY: >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 0; >>> + break; >>> + } >>> +} >>> + >>> static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) >>> { >>> u32 tmp, sh_static_mem_cfg; >>> @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device >> *adev) >>> gfx_v8_0_tiling_mode_table_init(adev); >>> gfx_v8_0_setup_rb(adev); >>> gfx_v8_0_get_cu_info(adev); >>> + gfx_v8_0_cap_init(adev); >>> >>> /* XXX SH_MEM regs */ >>> /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git >>> a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index >>> 04daab3..7064fdc 100644 >>> --- a/include/uapi/drm/amdgpu_drm.h >>> +++ b/include/uapi/drm/amdgpu_drm.h >>> @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { >>> struct drm_amdgpu_capability { >>> __u32 flag; >>> __u32 direct_gma_size; >>> + __u32 gc_double_offchip_lds_buf; >>> }; >>> >>> /* > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <ea0dbd80-8ebf-908f-3d7f-78501b06fc53-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* RE: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <ea0dbd80-8ebf-908f-3d7f-78501b06fc53-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2017-02-17 5:02 ` Zhang, Jerry [not found] ` <BN6PR12MB180905873C26301AFC42915DFF5D0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Zhang, Jerry @ 2017-02-17 5:02 UTC (permalink / raw) To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Hi Christian, Thanks for specifying it. Please check my update in another mail if getting the correct info as you mentioned. > Just make sure that the default value is zero, this way you keep backward > compatible with older kernel interfaces. I have checked all gfx from 6 to 8. By default they are 1. Just 2 APUs(gfxv8) are 0. Regards, Jerry (Junwei Zhang) Linux Base Graphics SRDC Software Development _____________________________________ > -----Original Message----- > From: Christian König [mailto:deathsimple@vodafone.de] > Sent: Thursday, February 16, 2017 17:37 > To: Zhang, Jerry; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info > > Am 16.02.2017 um 10:24 schrieb Zhang, Jerry: > >> -----Original Message----- > >> From: Christian König [mailto:deathsimple@vodafone.de] > >> Sent: Thursday, February 16, 2017 17:12 > >> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org > >> Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu > >> info > >> > >> Am 16.02.2017 um 03:53 schrieb Junwei Zhang: > >>> Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a > >>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> > >> Complete NAK on this. The drm_amdgpu_capability structure is specific > >> to the pro driver. > > Thanks to reminder it. > > I neglect it. > > > >> The Vulkan stack on the other hand is supposed to work on the open > >> stack as well. > >> > >> So please but that into the drm_amdgpu_info_device structure and the > >> new field in the amdgpu_gca_config structure (you might as well want > >> to rename the amdgpu_gca_config structure). > > So you mean add the feature or config structure in amdgpu_device directly > from now on. > > Right? > > No, just forget about the config or feature structure. Add gfx features to > amdgpu_gca_config. > > > Could you explain the meaning about gca? > > I just think that the naming isn't the best, something like amdgpu_gfx_config > would probably be better. > > > > > BTW, > > 1) in the future we may add more feature/config in the same structure, but > may not for gfx. > > Stop, that is really bad design. The features/config should be kept on a per IP > basis. > > So gfx config/features should only be grouped together with gfx features. Don't > mix features from different block inside the kernel module. > > The IOCTL interface is a different story, here we have the > drm_amdgpu_info_device structure for information about the whole GPU as > well as individual structures about each IP block (like firmware versions etc...). > > For the current case adding that to drm_amdgpu_info_device sounds like the > right approach to me. > > > 2) Shall we add a version to control these features? UMD could know the > features status according to the version. > > No, the size of the drm_amdgpu_info_device structure is already version > controlled. > > Just make sure that the default value is zero, this way you keep backward > compatible with older kernel interfaces. > > Regards, > Christian. > > > > >> Regards, > >> Christian. > >> > >>> --- > >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ > >>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ > >>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ > >>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ > >>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ > >>> include/uapi/drm/amdgpu_drm.h | 1 + > >>> 6 files changed, 35 insertions(+) > >>> > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >>> index 1ad3f08..cdc2b2a 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > >>> @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { > >>> void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t > >>> simd, > >> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); > >>> }; > >>> > >>> +struct amdgpu_gfx_cap { > >>> + uint32_t gc_double_offchip_lds_buf; }; > >>> + > >>> struct amdgpu_gfx { > >>> struct mutex gpu_clock_mutex; > >>> struct amdgpu_gca_config config; > >>> @@ -911,6 +915,8 @@ struct amdgpu_gfx { > >>> /* reset mask */ > >>> uint32_t grbm_soft_reset; > >>> uint32_t srbm_soft_reset; > >>> + > >>> + struct amdgpu_gfx_cap cap; > >>> }; > >>> > >>> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm > >>> *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > >>> index 7f59608..e7aa382 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c > >>> @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device > >>> *dev, > >> void *data, struct drm_file > >>> cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; > >>> cap.direct_gma_size = amdgpu_direct_gma_size; > >>> } > >>> + cap.gc_double_offchip_lds_buf = > >>> + adev->gfx.cap.gc_double_offchip_lds_buf; > >>> return copy_to_user(out, &cap, > >>> min((size_t)size, sizeof(cap))) ? -EFAULT : 0; > >>> } > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>> index ce75d46..a1e221b 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>> @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct > >> amdgpu_device *adev, > >>> mutex_unlock(&adev->grbm_idx_mutex); > >>> } > >>> > >>> +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) { > >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } > >>> + > >>> static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) > >>> { > >>> u32 gb_addr_config = 0; > >>> @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct > >>> amdgpu_device > >> *adev) > >>> adev->gfx.config.max_cu_per_sh); > >>> > >>> gfx_v6_0_get_cu_info(adev); > >>> + gfx_v6_0_cap_init(adev); > >>> > >>> WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << > >> CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | > >>> (0x2b << > >> CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>> index aaf66fe..e1e97ae 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>> @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct > >> amdgpu_device *adev) > >>> mutex_unlock(&adev->srbm_mutex); > >>> } > >>> > >>> +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) { > >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } > >>> + > >>> /** > >>> * gfx_v7_0_gpu_init - setup the 3D engine > >>> * > >>> @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct > >>> amdgpu_device *adev) > >>> > >>> gfx_v7_0_setup_rb(adev); > >>> gfx_v7_0_get_cu_info(adev); > >>> + gfx_v7_0_cap_init(adev); > >>> > >>> /* set HW defaults for 3D engine */ > >>> WREG32(mmCP_MEQ_THRESHOLDS, > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>> index ce05e38..934fc71 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>> @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct > >> amdgpu_device *adev) > >>> mutex_unlock(&adev->srbm_mutex); > >>> } > >>> > >>> +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) { > >>> + switch (adev->asic_type) { > >>> + default: > >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; > >>> + break; > >>> + case CHIP_CARRIZO: > >>> + case CHIP_STONEY: > >>> + adev->gfx.cap.gc_double_offchip_lds_buf = 0; > >>> + break; > >>> + } > >>> +} > >>> + > >>> static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) > >>> { > >>> u32 tmp, sh_static_mem_cfg; > >>> @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct > >>> amdgpu_device > >> *adev) > >>> gfx_v8_0_tiling_mode_table_init(adev); > >>> gfx_v8_0_setup_rb(adev); > >>> gfx_v8_0_get_cu_info(adev); > >>> + gfx_v8_0_cap_init(adev); > >>> > >>> /* XXX SH_MEM regs */ > >>> /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git > >>> a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > >>> index 04daab3..7064fdc 100644 > >>> --- a/include/uapi/drm/amdgpu_drm.h > >>> +++ b/include/uapi/drm/amdgpu_drm.h > >>> @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { > >>> struct drm_amdgpu_capability { > >>> __u32 flag; > >>> __u32 direct_gma_size; > >>> + __u32 gc_double_offchip_lds_buf; > >>> }; > >>> > >>> /* > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <BN6PR12MB180905873C26301AFC42915DFF5D0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info [not found] ` <BN6PR12MB180905873C26301AFC42915DFF5D0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2017-02-17 10:21 ` Christian König 0 siblings, 0 replies; 10+ messages in thread From: Christian König @ 2017-02-17 10:21 UTC (permalink / raw) To: Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 17.02.2017 um 06:02 schrieb Zhang, Jerry: > Hi Christian, > > Thanks for specifying it. > > Please check my update in another mail if getting the correct info as you mentioned. > >> Just make sure that the default value is zero, this way you keep backward >> compatible with older kernel interfaces. > I have checked all gfx from 6 to 8. By default they are 1. Just 2 APUs(gfxv8) are 0. In this case you might want to bump the driver minor number as well to indicate validity of that field. See we can extend the structures by adding new fields to the end, but old kernels will not set those fields (so they stay zero cleared). Not sure what the UMD is expecting here. Regards, Christian. > > Regards, > Jerry (Junwei Zhang) > > Linux Base Graphics > SRDC Software Development > _____________________________________ > > >> -----Original Message----- >> From: Christian König [mailto:deathsimple@vodafone.de] >> Sent: Thursday, February 16, 2017 17:37 >> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org >> Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu info >> >> Am 16.02.2017 um 10:24 schrieb Zhang, Jerry: >>>> -----Original Message----- >>>> From: Christian König [mailto:deathsimple@vodafone.de] >>>> Sent: Thursday, February 16, 2017 17:12 >>>> To: Zhang, Jerry; amd-gfx@lists.freedesktop.org >>>> Subject: Re: [PATCH 1/1] drm/amdgpu: export gfx capability by gpu >>>> info >>>> >>>> Am 16.02.2017 um 03:53 schrieb Junwei Zhang: >>>>> Change-Id: Ibf3e4dbb7deb83271adabc275c9b7a0e0652541a >>>>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> >>>> Complete NAK on this. The drm_amdgpu_capability structure is specific >>>> to the pro driver. >>> Thanks to reminder it. >>> I neglect it. >>> >>>> The Vulkan stack on the other hand is supposed to work on the open >>>> stack as well. >>>> >>>> So please but that into the drm_amdgpu_info_device structure and the >>>> new field in the amdgpu_gca_config structure (you might as well want >>>> to rename the amdgpu_gca_config structure). >>> So you mean add the feature or config structure in amdgpu_device directly >> from now on. >>> Right? >> No, just forget about the config or feature structure. Add gfx features to >> amdgpu_gca_config. >> >>> Could you explain the meaning about gca? >> I just think that the naming isn't the best, something like amdgpu_gfx_config >> would probably be better. >> >>> BTW, >>> 1) in the future we may add more feature/config in the same structure, but >> may not for gfx. >> >> Stop, that is really bad design. The features/config should be kept on a per IP >> basis. >> >> So gfx config/features should only be grouped together with gfx features. Don't >> mix features from different block inside the kernel module. >> >> The IOCTL interface is a different story, here we have the >> drm_amdgpu_info_device structure for information about the whole GPU as >> well as individual structures about each IP block (like firmware versions etc...). >> >> For the current case adding that to drm_amdgpu_info_device sounds like the >> right approach to me. >> >>> 2) Shall we add a version to control these features? UMD could know the >> features status according to the version. >> >> No, the size of the drm_amdgpu_info_device structure is already version >> controlled. >> >> Just make sure that the default value is zero, this way you keep backward >> compatible with older kernel interfaces. >> >> Regards, >> Christian. >> >>>> Regards, >>>> Christian. >>>> >>>>> --- >>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 ++++++ >>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ >>>>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++++ >>>>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++++ >>>>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++++++++ >>>>> include/uapi/drm/amdgpu_drm.h | 1 + >>>>> 6 files changed, 35 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> index 1ad3f08..cdc2b2a 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> @@ -869,6 +869,10 @@ struct amdgpu_gfx_funcs { >>>>> void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t >>>>> simd, >>>> uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); >>>>> }; >>>>> >>>>> +struct amdgpu_gfx_cap { >>>>> + uint32_t gc_double_offchip_lds_buf; }; >>>>> + >>>>> struct amdgpu_gfx { >>>>> struct mutex gpu_clock_mutex; >>>>> struct amdgpu_gca_config config; >>>>> @@ -911,6 +915,8 @@ struct amdgpu_gfx { >>>>> /* reset mask */ >>>>> uint32_t grbm_soft_reset; >>>>> uint32_t srbm_soft_reset; >>>>> + >>>>> + struct amdgpu_gfx_cap cap; >>>>> }; >>>>> >>>>> int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm >>>>> *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>>> index 7f59608..e7aa382 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c >>>>> @@ -618,6 +618,8 @@ static int amdgpu_info_ioctl(struct drm_device >>>>> *dev, >>>> void *data, struct drm_file >>>>> cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; >>>>> cap.direct_gma_size = amdgpu_direct_gma_size; >>>>> } >>>>> + cap.gc_double_offchip_lds_buf = >>>>> + adev->gfx.cap.gc_double_offchip_lds_buf; >>>>> return copy_to_user(out, &cap, >>>>> min((size_t)size, sizeof(cap))) ? -EFAULT : 0; >>>>> } >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>> index ce75d46..a1e221b 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>> @@ -1534,6 +1534,11 @@ static void gfx_v6_0_setup_spi(struct >>>> amdgpu_device *adev, >>>>> mutex_unlock(&adev->grbm_idx_mutex); >>>>> } >>>>> >>>>> +static void gfx_v6_0_cap_init(struct amdgpu_device *adev) { >>>>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } >>>>> + >>>>> static void gfx_v6_0_gpu_init(struct amdgpu_device *adev) >>>>> { >>>>> u32 gb_addr_config = 0; >>>>> @@ -1692,6 +1697,7 @@ static void gfx_v6_0_gpu_init(struct >>>>> amdgpu_device >>>> *adev) >>>>> adev->gfx.config.max_cu_per_sh); >>>>> >>>>> gfx_v6_0_get_cu_info(adev); >>>>> + gfx_v6_0_cap_init(adev); >>>>> >>>>> WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << >>>> CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) | >>>>> (0x2b << >>>> CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT))); >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>> index aaf66fe..e1e97ae 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>> @@ -1876,6 +1876,11 @@ static void gmc_v7_0_init_compute_vmid(struct >>>> amdgpu_device *adev) >>>>> mutex_unlock(&adev->srbm_mutex); >>>>> } >>>>> >>>>> +static void gfx_v7_0_cap_init(struct amdgpu_device *adev) { >>>>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; } >>>>> + >>>>> /** >>>>> * gfx_v7_0_gpu_init - setup the 3D engine >>>>> * >>>>> @@ -1900,6 +1905,7 @@ static void gfx_v7_0_gpu_init(struct >>>>> amdgpu_device *adev) >>>>> >>>>> gfx_v7_0_setup_rb(adev); >>>>> gfx_v7_0_get_cu_info(adev); >>>>> + gfx_v7_0_cap_init(adev); >>>>> >>>>> /* set HW defaults for 3D engine */ >>>>> WREG32(mmCP_MEQ_THRESHOLDS, >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>> index ce05e38..934fc71 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>> @@ -3826,6 +3826,19 @@ static void gfx_v8_0_init_compute_vmid(struct >>>> amdgpu_device *adev) >>>>> mutex_unlock(&adev->srbm_mutex); >>>>> } >>>>> >>>>> +static void gfx_v8_0_cap_init(struct amdgpu_device *adev) { >>>>> + switch (adev->asic_type) { >>>>> + default: >>>>> + adev->gfx.cap.gc_double_offchip_lds_buf = 1; >>>>> + break; >>>>> + case CHIP_CARRIZO: >>>>> + case CHIP_STONEY: >>>>> + adev->gfx.cap.gc_double_offchip_lds_buf = 0; >>>>> + break; >>>>> + } >>>>> +} >>>>> + >>>>> static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) >>>>> { >>>>> u32 tmp, sh_static_mem_cfg; >>>>> @@ -3839,6 +3852,7 @@ static void gfx_v8_0_gpu_init(struct >>>>> amdgpu_device >>>> *adev) >>>>> gfx_v8_0_tiling_mode_table_init(adev); >>>>> gfx_v8_0_setup_rb(adev); >>>>> gfx_v8_0_get_cu_info(adev); >>>>> + gfx_v8_0_cap_init(adev); >>>>> >>>>> /* XXX SH_MEM regs */ >>>>> /* where to put LDS, scratch, GPUVM in FSA64 space */ diff --git >>>>> a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h >>>>> index 04daab3..7064fdc 100644 >>>>> --- a/include/uapi/drm/amdgpu_drm.h >>>>> +++ b/include/uapi/drm/amdgpu_drm.h >>>>> @@ -853,6 +853,7 @@ struct drm_amdgpu_virtual_range { >>>>> struct drm_amdgpu_capability { >>>>> __u32 flag; >>>>> __u32 direct_gma_size; >>>>> + __u32 gc_double_offchip_lds_buf; >>>>> }; >>>>> >>>>> /* >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-02-17 10:21 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2017-02-16 2:53 add gfx capability by gpu info Junwei Zhang
[not found] ` <1487213588-26299-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
2017-02-16 2:53 ` [PATCH 1/1] drm/amdgpu: export " Junwei Zhang
[not found] ` <1487213588-26299-2-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
2017-02-16 4:37 ` Edward O'Callaghan
[not found] ` <2ee3024b-cd44-9fd6-62f7-fb8117dd2e74-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
2017-02-16 5:46 ` Zhang, Jerry
[not found] ` <BN6PR12MB1809B9E0ECE9A87C21C92A41FF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-02-16 7:17 ` Edward O'Callaghan
2017-02-16 9:11 ` Christian König
[not found] ` <2bae755f-f1e2-57de-257c-e1d155723122-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-02-16 9:24 ` Zhang, Jerry
[not found] ` <BN6PR12MB18098E6B408580D7847D84EBFF5A0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-02-16 9:36 ` Christian König
[not found] ` <ea0dbd80-8ebf-908f-3d7f-78501b06fc53-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-02-17 5:02 ` Zhang, Jerry
[not found] ` <BN6PR12MB180905873C26301AFC42915DFF5D0-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-02-17 10:21 ` Christian König
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