* [Qemu-devel] [PATCH v8 01/38] target/mips: Define R5900 instructions and CPU preprocessor constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
@ 2018-10-21 15:31 ` Fredrik Noring
2018-10-21 15:31 ` [Qemu-devel] [PATCH v8 02/38] disas/mips: Define R5900 disassembly constants Fredrik Noring
` (37 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:31 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
The R5900 implements the 64-bit MIPS III instruction set except DMULT,
DMULTU, DDIV, DDIVU, LL, SC, LLD and SCD. The MIPS IV instructions MOVN,
MOVZ and PREF are implemented. It has the R5900-specific three-operand
instructions MADD, MADDU, MULT and MULTU as well as pipeline 1 versions
MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and
MTLO1. A set of 93 128-bit multimedia instructions specific to the
R5900 is also implemented.
The Toshiba TX System RISC TX79 Core Architecture manual
https://wiki.qemu.org/File:C790.pdf
describes the C790 processor that is a follow-up to the R5900. There
are a few notable differences in that the R5900 FPU
- is not IEEE 754-1985 compliant,
- does not implement double format, and
- its machine code is nonstandard.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 71ea4ef892..f017551e15 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -64,6 +64,7 @@
#define INSN_LOONGSON2E 0x0001000000000000ULL
#define INSN_LOONGSON2F 0x0002000000000000ULL
#define INSN_VR54XX 0x0004000000000000ULL
+#define INSN_R5900 0x0008000000000000ULL
/*
* bits 56-63: vendor-specific ASEs
*/
@@ -74,6 +75,7 @@
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
+#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 02/38] disas/mips: Define R5900 disassembly constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
2018-10-21 15:31 ` [Qemu-devel] [PATCH v8 01/38] target/mips: Define R5900 instructions and CPU preprocessor constants Fredrik Noring
@ 2018-10-21 15:31 ` Fredrik Noring
2018-10-21 15:32 ` [Qemu-devel] [PATCH v8 03/38] target/mips: R5900 Multimedia Instruction overview note Fredrik Noring
` (36 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:31 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
disas/mips.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/disas/mips.c b/disas/mips.c
index 97f661a37e..ae72059c46 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -611,6 +611,9 @@ struct mips_opcode
/* ST Microelectronics Loongson 2F. */
#define INSN_LOONGSON_2F 0x80000000
+/* Sony/Toshiba R5900 */
+#define INSN_5900 0x100000000
+
/* MIPS ISA defines, use instead of hardcoding ISA level. */
#define ISA_UNKNOWN 0 /* Gas internal use. */
@@ -646,6 +649,7 @@ struct mips_opcode
#define CPU_R5000 5000
#define CPU_VR5400 5400
#define CPU_VR5500 5500
+#define CPU_R5900 5900
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
@@ -1193,6 +1197,7 @@ extern const int bfd_mips16_num_opcodes;
#define N5 (INSN_5400 | INSN_5500)
#define N54 INSN_5400
#define N55 INSN_5500
+#define EE INSN_5900 /* Emotion Engine */
#define G1 (T3 \
)
@@ -3861,6 +3866,7 @@ struct mips_arch_choice
#define bfd_mach_mips5000 5000
#define bfd_mach_mips5400 5400
#define bfd_mach_mips5500 5500
+#define bfd_mach_mips5900 5900
#define bfd_mach_mips6000 6000
#define bfd_mach_mips7000 7000
#define bfd_mach_mips8000 8000
@@ -3908,6 +3914,8 @@ static const struct mips_arch_choice mips_arch_choices[] =
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
+ { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3,
+ mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
{ "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 03/38] target/mips: R5900 Multimedia Instruction overview note
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
2018-10-21 15:31 ` [Qemu-devel] [PATCH v8 01/38] target/mips: Define R5900 instructions and CPU preprocessor constants Fredrik Noring
2018-10-21 15:31 ` [Qemu-devel] [PATCH v8 02/38] disas/mips: Define R5900 disassembly constants Fredrik Noring
@ 2018-10-21 15:32 ` Fredrik Noring
2018-10-21 15:33 ` [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants Fredrik Noring
` (35 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:32 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 161 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 161 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3a0bdd55c8..32d1d2d83f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1927,6 +1927,167 @@ enum {
OPC_MXU_Q8MACSU = 0x01,
};
+/*
+ * Overview of the TX79-specific instruction set
+ * =============================================
+ *
+ * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits
+ * are only used by the specific quadword (128-bit) LQ/SQ load/store
+ * instructions and certain multimedia instructions (MMIs). These MMIs
+ * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit
+ * or sixteen 8-bit paths.
+ *
+ * Reference:
+ *
+ * The Toshiba TX System RISC TX79 Core Architecture manual,
+ * https://wiki.qemu.org/File:C790.pdf
+ *
+ * Three-Operand Multiply and Multiply-Add (4 instructions)
+ * --------------------------------------------------------
+ * MADD [rd,] rs, rt Multiply/Add
+ * MADDU [rd,] rs, rt Multiply/Add Unsigned
+ * MULT [rd,] rs, rt Multiply (3-operand)
+ * MULTU [rd,] rs, rt Multiply Unsigned (3-operand)
+ *
+ * Multiply Instructions for Pipeline 1 (10 instructions)
+ * ------------------------------------------------------
+ * MULT1 [rd,] rs, rt Multiply Pipeline 1
+ * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1
+ * DIV1 rs, rt Divide Pipeline 1
+ * DIVU1 rs, rt Divide Unsigned Pipeline 1
+ * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1
+ * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1
+ * MFHI1 rd Move From HI1 Register
+ * MFLO1 rd Move From LO1 Register
+ * MTHI1 rs Move To HI1 Register
+ * MTLO1 rs Move To LO1 Register
+ *
+ * Arithmetic (19 instructions)
+ * ----------------------------
+ * PADDB rd, rs, rt Parallel Add Byte
+ * PSUBB rd, rs, rt Parallel Subtract Byte
+ * PADDH rd, rs, rt Parallel Add Halfword
+ * PSUBH rd, rs, rt Parallel Subtract Halfword
+ * PADDW rd, rs, rt Parallel Add Word
+ * PSUBW rd, rs, rt Parallel Subtract Word
+ * PADSBH rd, rs, rt Parallel Add/Subtract Halfword
+ * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte
+ * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte
+ * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword
+ * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword
+ * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word
+ * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word
+ * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte
+ * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte
+ * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword
+ * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword
+ * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word
+ * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word
+ *
+ * Min/Max (4 instructions)
+ * ------------------------
+ * PMAXH rd, rs, rt Parallel Maximum Halfword
+ * PMINH rd, rs, rt Parallel Minimum Halfword
+ * PMAXW rd, rs, rt Parallel Maximum Word
+ * PMINW rd, rs, rt Parallel Minimum Word
+ *
+ * Absolute (2 instructions)
+ * -------------------------
+ * PABSH rd, rt Parallel Absolute Halfword
+ * PABSW rd, rt Parallel Absolute Word
+ *
+ * Logical (4 instructions)
+ * ------------------------
+ * PAND rd, rs, rt Parallel AND
+ * POR rd, rs, rt Parallel OR
+ * PXOR rd, rs, rt Parallel XOR
+ * PNOR rd, rs, rt Parallel NOR
+ *
+ * Shift (9 instructions)
+ * ----------------------
+ * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword
+ * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword
+ * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword
+ * PSLLW rd, rt, sa Parallel Shift Left Logical Word
+ * PSRLW rd, rt, sa Parallel Shift Right Logical Word
+ * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word
+ * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word
+ * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word
+ * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word
+ *
+ * Compare (6 instructions)
+ * ------------------------
+ * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte
+ * PCEQB rd, rs, rt Parallel Compare for Equal Byte
+ * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword
+ * PCEQH rd, rs, rt Parallel Compare for Equal Halfword
+ * PCGTW rd, rs, rt Parallel Compare for Greater Than Word
+ * PCEQW rd, rs, rt Parallel Compare for Equal Word
+ *
+ * LZC (1 instruction)
+ * -------------------
+ * PLZCW rd, rs Parallel Leading Zero or One Count Word
+ *
+ * Quadword Load and Store (2 instructions)
+ * ----------------------------------------
+ * LQ rt, offset(base) Load Quadword
+ * SQ rt, offset(base) Store Quadword
+ *
+ * Multiply and Divide (19 instructions)
+ * -------------------------------------
+ * PMULTW rd, rs, rt Parallel Multiply Word
+ * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word
+ * PDIVW rs, rt Parallel Divide Word
+ * PDIVUW rs, rt Parallel Divide Unsigned Word
+ * PMADDW rd, rs, rt Parallel Multiply-Add Word
+ * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word
+ * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word
+ * PMULTH rd, rs, rt Parallel Multiply Halfword
+ * PMADDH rd, rs, rt Parallel Multiply-Add Halfword
+ * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword
+ * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword
+ * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword
+ * PDIVBW rs, rt Parallel Divide Broadcast Word
+ * PMFHI rd Parallel Move From HI Register
+ * PMFLO rd Parallel Move From LO Register
+ * PMTHI rs Parallel Move To HI Register
+ * PMTLO rs Parallel Move To LO Register
+ * PMFHL rd Parallel Move From HI/LO Register
+ * PMTHL rs Parallel Move To HI/LO Register
+ *
+ * Pack/Extend (11 instructions)
+ * -----------------------------
+ * PPAC5 rd, rt Parallel Pack to 5 bits
+ * PPACB rd, rs, rt Parallel Pack to Byte
+ * PPACH rd, rs, rt Parallel Pack to Halfword
+ * PPACW rd, rs, rt Parallel Pack to Word
+ * PEXT5 rd, rt Parallel Extend Upper from 5 bits
+ * PEXTUB rd, rs, rt Parallel Extend Upper from Byte
+ * PEXTLB rd, rs, rt Parallel Extend Lower from Byte
+ * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword
+ * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword
+ * PEXTUW rd, rs, rt Parallel Extend Upper from Word
+ * PEXTLW rd, rs, rt Parallel Extend Lower from Word
+ *
+ * Others (16 instructions)
+ * ------------------------
+ * PCPYH rd, rt Parallel Copy Halfword
+ * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword
+ * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword
+ * PREVH rd, rt Parallel Reverse Halfword
+ * PINTH rd, rs, rt Parallel Interleave Halfword
+ * PINTEH rd, rs, rt Parallel Interleave Even Halfword
+ * PEXEH rd, rt Parallel Exchange Even Halfword
+ * PEXCH rd, rt Parallel Exchange Center Halfword
+ * PEXEW rd, rt Parallel Exchange Even Word
+ * PEXCW rd, rt Parallel Exchange Center Word
+ * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable
+ * MFSA rd Move from Shift Amount Register
+ * MTSA rs Move to Shift Amount Register
+ * MTSAB rs, immediate Move Byte Count to Shift Amount Register
+ * MTSAH rs, immediate Move Halfword Count to Shift Amount Register
+ * PROT3W rd, rt Parallel Rotate 3 Words
+ */
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (2 preceding siblings ...)
2018-10-21 15:32 ` [Qemu-devel] [PATCH v8 03/38] target/mips: R5900 Multimedia Instruction overview note Fredrik Noring
@ 2018-10-21 15:33 ` Fredrik Noring
2018-10-21 15:33 ` [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI " Fredrik Noring
` (34 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:33 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 32d1d2d83f..e205c3eaef 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2087,8 +2087,48 @@ enum {
* MTSAB rs, immediate Move Byte Count to Shift Amount Register
* MTSAH rs, immediate Move Halfword Count to Shift Amount Register
* PROT3W rd, rt Parallel Rotate 3 Words
+ *
+ * The TX79-specific Multimedia Instruction encodings
+ * ==================================================
+ *
+ * TX79 Multimedia Instruction encoding table keys:
+ *
+ * * This code is reserved for future use. An attempt to execute it
+ * causes a Reserved Instruction exception.
+ * % This code indicates an instruction class. The instruction word
+ * must be further decoded by examining additional tables that show
+ * the values for other instruction fields.
+ * # This code is reserved for the unsupported instructions DMULT,
+ * DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
+ * to execute it causes a Reserved Instruction exception.
+ *
+ * TX79 Multimedia Instructions encoded by opcode field (MMI, LQ, SQ):
+ *
+ * 31 26 0
+ * +--------+----------------------------------------+
+ * | opcode | |
+ * +--------+----------------------------------------+
+ *
+ * opcode bits 28..26
+ * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
+ * 31..29 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+ * -------+-------+-------+-------+-------+-------+-------+-------+-------
+ * 0 000 |SPECIAL| REGIMM| J | JAL | BEQ | BNE | BLEZ | BGTZ
+ * 1 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI
+ * 2 010 | COP0 | COP1 | * | * | BEQL | BNEL | BLEZL | BGTZL
+ * 3 011 | DADDI | DADDIU| LDL | LDR | MMI% | * | LQ | SQ
+ * 4 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU
+ * 5 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE
+ * 6 110 | # | LWC1 | # | PREF | # | LDC1 | # | LD
+ * 7 111 | # | SWC1 | # | * | # | SDC1 | # | SD
*/
+enum {
+ TX79_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
+ TX79_LQ = 0x1E << 26, /* Same as OPC_MSA */
+ TX79_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (3 preceding siblings ...)
2018-10-21 15:33 ` [Qemu-devel] [PATCH v8 04/38] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants Fredrik Noring
@ 2018-10-21 15:33 ` Fredrik Noring
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 " Fredrik Noring
` (33 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:33 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 51 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e205c3eaef..ae988177a1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2129,6 +2129,57 @@ enum {
TX79_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI:
+ *
+ * 31 26 5 0
+ * +--------+-------------------------------+--------+
+ * | MMI | |function|
+ * +--------+-------------------------------+--------+
+ *
+ * function bits 2..0
+ * bits | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7
+ * 5..3 | 000 | 001 | 010 | 011 | 100 | 101 | 110 | 111
+ * -------+-------+-------+-------+-------+-------+-------+-------+-------
+ * 0 000 | MADD | MADDU | * | * | PLZCW | * | * | *
+ * 1 001 | MMI0% | MMI2% | * | * | * | * | * | *
+ * 2 010 | MFHI1 | MTHI1 | MFLO1 | MTLO1 | * | * | * | *
+ * 3 011 | MULT1 | MULTU1| DIV1 | DIVU1 | * | * | * | *
+ * 4 100 | MADD1 | MADDU1| * | * | * | * | * | *
+ * 5 101 | MMI1% | MMI3% | * | * | * | * | * | *
+ * 6 110 | PMFHL | PMTHL | * | * | PSLLH | * | PSRLH | PSRAH
+ * 7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
+ */
+
+#define MASK_TX79_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
+enum {
+ TX79_MMI_MADD = 0x00 | TX79_CLASS_MMI, /* Same as OPC_MADD */
+ TX79_MMI_MADDU = 0x01 | TX79_CLASS_MMI, /* Same as OPC_MADDU */
+ TX79_MMI_PLZCW = 0x04 | TX79_CLASS_MMI,
+ TX79_MMI_CLASS_MMI0 = 0x08 | TX79_CLASS_MMI,
+ TX79_MMI_CLASS_MMI2 = 0x09 | TX79_CLASS_MMI,
+ TX79_MMI_MFHI1 = 0x10 | TX79_CLASS_MMI, /* Same minor as OPC_MFHI */
+ TX79_MMI_MTHI1 = 0x11 | TX79_CLASS_MMI, /* Same minor as OPC_MTHI */
+ TX79_MMI_MFLO1 = 0x12 | TX79_CLASS_MMI, /* Same minor as OPC_MFLO */
+ TX79_MMI_MTLO1 = 0x13 | TX79_CLASS_MMI, /* Same minor as OPC_MTLO */
+ TX79_MMI_MULT1 = 0x18 | TX79_CLASS_MMI, /* Same minor as OPC_MULT */
+ TX79_MMI_MULTU1 = 0x19 | TX79_CLASS_MMI, /* Same minor as OPC_MULTU */
+ TX79_MMI_DIV1 = 0x1A | TX79_CLASS_MMI, /* Same minor as OPC_DIV */
+ TX79_MMI_DIVU1 = 0x1B | TX79_CLASS_MMI, /* Same minor as OPC_DIVU */
+ TX79_MMI_MADD1 = 0x20 | TX79_CLASS_MMI,
+ TX79_MMI_MADDU1 = 0x21 | TX79_CLASS_MMI,
+ TX79_MMI_CLASS_MMI1 = 0x28 | TX79_CLASS_MMI,
+ TX79_MMI_CLASS_MMI3 = 0x29 | TX79_CLASS_MMI,
+ TX79_MMI_PMFHL = 0x30 | TX79_CLASS_MMI,
+ TX79_MMI_PMTHL = 0x31 | TX79_CLASS_MMI,
+ TX79_MMI_PSLLH = 0x34 | TX79_CLASS_MMI,
+ TX79_MMI_PSRLH = 0x36 | TX79_CLASS_MMI,
+ TX79_MMI_PSRAH = 0x37 | TX79_CLASS_MMI,
+ TX79_MMI_PSLLW = 0x3C | TX79_CLASS_MMI,
+ TX79_MMI_PSRLW = 0x3E | TX79_CLASS_MMI,
+ TX79_MMI_PSRAW = 0x3F | TX79_CLASS_MMI,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 opcode constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (4 preceding siblings ...)
2018-10-21 15:33 ` [Qemu-devel] [PATCH v8 05/38] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI " Fredrik Noring
@ 2018-10-21 15:34 ` Fredrik Noring
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 " Fredrik Noring
` (32 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:34 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 51 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ae988177a1..242f2df2e2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2180,6 +2180,57 @@ enum {
TX79_MMI_PSRAW = 0x3F | TX79_CLASS_MMI,
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI0:
+ *
+ * 31 26 10 6 5 0
+ * +--------+----------------------+--------+--------+
+ * | MMI | |function| MMI0 |
+ * +--------+----------------------+--------+--------+
+ *
+ * function bits 7..6
+ * bits | 0 | 1 | 2 | 3
+ * 10..8 | 00 | 01 | 10 | 11
+ * -------+-------+-------+-------+-------
+ * 0 000 | PADDW | PSUBW | PCGTW | PMAXW
+ * 1 001 | PADDH | PSUBH | PCGTH | PMAXH
+ * 2 010 | PADDB | PSUBB | PCGTB | *
+ * 3 011 | * | * | * | *
+ * 4 100 | PADDSW| PSUBSW| PEXTLW| PPACW
+ * 5 101 | PADDSH| PSUBSH| PEXTLH| PPACH
+ * 6 110 | PADDSB| PSUBSB| PEXTLB| PPACB
+ * 7 111 | * | * | PEXT5 | PPAC5
+ */
+
+#define MASK_TX79_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
+enum {
+ TX79_MMI0_PADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBW = (0x01 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PCGTW = (0x02 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PMAXW = (0x03 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDH = (0x04 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBH = (0x05 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PCGTH = (0x06 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PMAXH = (0x07 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDB = (0x08 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBB = (0x09 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PCGTB = (0x0A << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDSW = (0x10 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBSW = (0x11 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXTLW = (0x12 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPACW = (0x13 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDSH = (0x14 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBSH = (0x15 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXTLH = (0x16 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPACH = (0x17 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PADDSB = (0x18 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PSUBSB = (0x19 << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXTLB = (0x1A << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPACB = (0x1B << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PEXT5 = (0x1E << 6) | TX79_MMI_CLASS_MMI0,
+ TX79_MMI0_PPAC5 = (0x1F << 6) | TX79_MMI_CLASS_MMI0,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 opcode constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (5 preceding siblings ...)
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 06/38] target/mips: Define R5900 MMI0 " Fredrik Noring
@ 2018-10-21 15:34 ` Fredrik Noring
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 " Fredrik Noring
` (31 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:34 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 44 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 242f2df2e2..e233b87324 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2231,6 +2231,50 @@ enum {
TX79_MMI0_PPAC5 = (0x1F << 6) | TX79_MMI_CLASS_MMI0,
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI1:
+ *
+ * 31 26 10 6 5 0
+ * +--------+----------------------+--------+--------+
+ * | MMI | |function| MMI1 |
+ * +--------+----------------------+--------+--------+
+ *
+ * function bits 7..6
+ * bits | 0 | 1 | 2 | 3
+ * 10..8 | 00 | 01 | 10 | 11
+ * -------+-------+-------+-------+-------
+ * 0 000 | * | PABSW | PCEQW | PMINW
+ * 1 001 | PADSBH| PABSH | PCEQH | PMINH
+ * 2 010 | * | * | PCEQB | *
+ * 3 011 | * | * | * | *
+ * 4 100 | PADDUW| PSUBUW| PEXTUW| *
+ * 5 101 | PADDUH| PSUBUH| PEXTUH| *
+ * 6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV
+ * 7 111 | * | * | * | *
+ */
+
+#define MASK_TX79_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
+enum {
+ TX79_MMI1_PABSW = (0x01 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PCEQW = (0x02 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PMINW = (0x03 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PADSBH = (0x04 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PABSH = (0x05 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PCEQH = (0x06 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PMINH = (0x07 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PCEQB = (0x0A << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PADDUW = (0x10 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PSUBUW = (0x11 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PEXTUW = (0x12 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PADDUH = (0x14 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PSUBUH = (0x15 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PEXTUH = (0x16 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PADDUB = (0x18 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PSUBUB = (0x19 << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_PEXTUB = (0x1A << 6) | TX79_MMI_CLASS_MMI1,
+ TX79_MMI1_QFSRV = (0x1B << 6) | TX79_MMI_CLASS_MMI1,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 opcode constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (6 preceding siblings ...)
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 07/38] target/mips: Define R5900 MMI1 " Fredrik Noring
@ 2018-10-21 15:34 ` Fredrik Noring
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 " Fredrik Noring
` (30 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:34 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 48 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e233b87324..bd51443ac1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2275,6 +2275,54 @@ enum {
TX79_MMI1_QFSRV = (0x1B << 6) | TX79_MMI_CLASS_MMI1,
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI2:
+ *
+ * 31 26 10 6 5 0
+ * +--------+----------------------+--------+--------+
+ * | MMI | |function| MMI2 |
+ * +--------+----------------------+--------+--------+
+ *
+ * function bits 7..6
+ * bits | 0 | 1 | 2 | 3
+ * 10..8 | 00 | 01 | 10 | 11
+ * -------+-------+-------+-------+-------
+ * 0 000 | PMADDW| * | PSLLVW| PSRLVW
+ * 1 001 | PMSUBW| * | * | *
+ * 2 010 | PMFHI | PMFLO | PINTH | *
+ * 3 011 | PMULTW| PDIVW | PCPYLD| *
+ * 4 100 | PMADDH| PHMADH| PAND | PXOR
+ * 5 101 | PMSUBH| PHMSBH| * | *
+ * 6 110 | * | * | PEXEH | PREVH
+ * 7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
+ */
+
+#define MASK_TX79_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
+enum {
+ TX79_MMI2_PMADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PSLLVW = (0x02 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PSRLVW = (0x03 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMSUBW = (0x04 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMFHI = (0x08 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMFLO = (0x09 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PINTH = (0x0A << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMULTW = (0x0C << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PDIVW = (0x0D << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PCPYLD = (0x0E << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMADDH = (0x10 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PHMADH = (0x11 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PAND = (0x12 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PXOR = (0x13 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMSUBH = (0x14 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PHMSBH = (0x15 << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PEXEH = (0x1A << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PREVH = (0x1B << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PMULTH = (0x1C << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PDIVBW = (0x1D << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PEXEW = (0x1E << 6) | TX79_MMI_CLASS_MMI2,
+ TX79_MMI2_PROT3W = (0x1F << 6) | TX79_MMI_CLASS_MMI2,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 opcode constants
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (7 preceding siblings ...)
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 08/38] target/mips: Define R5900 MMI2 " Fredrik Noring
@ 2018-10-21 15:34 ` Fredrik Noring
2018-10-21 15:35 ` [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR Fredrik Noring
` (29 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:34 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bd51443ac1..3c6a2c99a6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2323,6 +2323,45 @@ enum {
TX79_MMI2_PROT3W = (0x1F << 6) | TX79_MMI_CLASS_MMI2,
};
+/*
+ * TX79 Multimedia Instructions with opcode field = MMI and bits 5..0 = MMI3:
+ *
+ * 31 26 10 6 5 0
+ * +--------+----------------------+--------+--------+
+ * | MMI | |function| MMI3 |
+ * +--------+----------------------+--------+--------+
+ *
+ * function bits 7..6
+ * bits | 0 | 1 | 2 | 3
+ * 10..8 | 00 | 01 | 10 | 11
+ * -------+-------+-------+-------+-------
+ * 0 000 |PMADDUW| * | * | PSRAVW
+ * 1 001 | * | * | * | *
+ * 2 010 | PMTHI | PMTLO | PINTEH| *
+ * 3 011 |PMULTUW| PDIVUW| PCPYUD| *
+ * 4 100 | * | * | POR | PNOR
+ * 5 101 | * | * | * | *
+ * 6 110 | * | * | PEXCH | PCPYH
+ * 7 111 | * | * | PEXCW | *
+ */
+
+#define MASK_TX79_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
+enum {
+ TX79_MMI3_PMADDUW = (0x00 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PSRAVW = (0x03 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PMTHI = (0x08 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PMTLO = (0x09 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PINTEH = (0x0A << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PMULTUW = (0x0C << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PDIVUW = (0x0D << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PCPYUD = (0x0E << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_POR = (0x12 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PNOR = (0x13 << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PEXCH = (0x1A << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PCPYH = (0x1B << 6) | TX79_MMI_CLASS_MMI3,
+ TX79_MMI3_PEXCW = (0x1E << 6) | TX79_MMI_CLASS_MMI3,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (8 preceding siblings ...)
2018-10-21 15:34 ` [Qemu-devel] [PATCH v8 09/38] target/mips: Define R5900 MMI3 " Fredrik Noring
@ 2018-10-21 15:35 ` Fredrik Noring
2018-10-21 15:35 ` [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ Fredrik Noring
` (28 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:35 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 53 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3c6a2c99a6..19a8abad54 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,53 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
+{
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */
+}
+
+/*
+ * The TX79-specific instruction Store Quadword
+ *
+ * +--------+-------+-------+------------------------+
+ * | 011111 | base | rt | offset | SQ
+ * +--------+-------+-------+------------------------+
+ * 6 5 5 16
+ *
+ * has the same opcode as the Read Hardware Register instruction
+ *
+ * +--------+-------+-------+-------+-------+--------+
+ * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR
+ * +--------+-------+-------+-------+-------+--------+
+ * 6 5 5 5 5 6
+ *
+ * that is required, trapped and emulated by the Linux kernel. However, all
+ * RDHWR encodings yield address error exceptions on the TX79 since the SQ
+ * offset is odd. Therefore all valid SQ instructions can execute normally.
+ * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
+ * between SQ and RDHWR, as the Linux kernel does.
+ */
+static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
+{
+ int base = extract32(ctx->opcode, 21, 5);
+ int rt = extract32(ctx->opcode, 16, 5);
+ int offset = extract32(ctx->opcode, 0, 16);
+
+#ifdef CONFIG_USER_ONLY
+ uint32_t op1 = MASK_SPECIAL3(ctx->opcode);
+ uint32_t op2 = extract32(ctx->opcode, 6, 5);
+
+ if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) {
+ int rd = extract32(ctx->opcode, 11, 5);
+
+ gen_rdhwr(ctx, rt, rd, 0);
+ return;
+ }
+#endif
+
+ gen_tx79_sq(ctx, base, rt, offset);
+}
+
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@@ -25720,7 +25767,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special2_legacy(env, ctx);
break;
case OPC_SPECIAL3:
- decode_opc_special3(env, ctx);
+ if (ctx->insn_flags & INSN_R5900) {
+ decode_tx79_sq(env, ctx); /* TX79_SQ */
+ } else {
+ decode_opc_special3(env, ctx);
+ }
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (9 preceding siblings ...)
2018-10-21 15:35 ` [Qemu-devel] [PATCH v8 10/38] target/mips: Placeholder for R5900 MMI SQ, handle user mode RDHWR Fredrik Noring
@ 2018-10-21 15:35 ` Fredrik Noring
2018-10-21 15:36 ` [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class Fredrik Noring
` (27 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:35 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19a8abad54..2318116d31 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,11 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
+{
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_LQ */
+}
+
static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */
@@ -26425,8 +26430,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_MSA: /* OPC_MDMX */
- /* MDMX: Not implemented. */
- gen_msa(env, ctx);
+ if (ctx->insn_flags & INSN_R5900) {
+ decode_tx79_lq(env, ctx); /* TX79_LQ */
+ } else {
+ /* MDMX: Not implemented. */
+ gen_msa(env, ctx);
+ }
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS32R6);
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (10 preceding siblings ...)
2018-10-21 15:35 ` [Qemu-devel] [PATCH v8 11/38] target/mips: Placeholder for R5900 MMI LQ Fredrik Noring
@ 2018-10-21 15:36 ` Fredrik Noring
2018-10-21 15:36 ` [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass Fredrik Noring
` (26 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:36 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2318116d31..3b100f2d17 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,45 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
+ case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
+ case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
+ case TX79_MMI_CLASS_MMI0: /* TODO: TX79_MMI_CLASS_MMI0 */
+ case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
+ case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
+ case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
+ case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
+ case TX79_MMI_MTLO1: /* TODO: TX79_MMI_MTLO1 */
+ case TX79_MMI_MULT1: /* TODO: TX79_MMI_MULT1 */
+ case TX79_MMI_MULTU1: /* TODO: TX79_MMI_MULTU1 */
+ case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */
+ case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
+ case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
+ case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
+ case TX79_MMI_CLASS_MMI1: /* TODO: TX79_MMI_CLASS_MMI1 */
+ case TX79_MMI_CLASS_MMI3: /* TODO: TX79_MMI_CLASS_MMI3 */
+ case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
+ case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
+ case TX79_MMI_PSLLH: /* TODO: TX79_MMI_PSLLH */
+ case TX79_MMI_PSRLH: /* TODO: TX79_MMI_PSRLH */
+ case TX79_MMI_PSRAH: /* TODO: TX79_MMI_PSRAH */
+ case TX79_MMI_PSLLW: /* TODO: TX79_MMI_PSLLW */
+ case TX79_MMI_PSRLW: /* TODO: TX79_MMI_PSRLW */
+ case TX79_MMI_PSRAW: /* TODO: TX79_MMI_PSRAW */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_CLASS_MMI */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_LQ */
@@ -25769,7 +25808,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
- decode_opc_special2_legacy(env, ctx);
+ if (ctx->insn_flags & INSN_R5900) {
+ decode_tx79_mmi(env, ctx);
+ } else {
+ decode_opc_special2_legacy(env, ctx);
+ }
break;
case OPC_SPECIAL3:
if (ctx->insn_flags & INSN_R5900) {
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (11 preceding siblings ...)
2018-10-21 15:36 ` [Qemu-devel] [PATCH v8 12/38] target/mips: Placeholder for R5900 MMI instruction class Fredrik Noring
@ 2018-10-21 15:36 ` Fredrik Noring
2018-10-21 15:36 ` [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 " Fredrik Noring
` (25 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:36 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3b100f2d17..c8080844f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,15 +24420,56 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI0(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI0_PADDW: /* TODO: TX79_MMI0_PADDW */
+ case TX79_MMI0_PSUBW: /* TODO: TX79_MMI0_PSUBW */
+ case TX79_MMI0_PCGTW: /* TODO: TX79_MMI0_PCGTW */
+ case TX79_MMI0_PMAXW: /* TODO: TX79_MMI0_PMAXW */
+ case TX79_MMI0_PADDH: /* TODO: TX79_MMI0_PADDH */
+ case TX79_MMI0_PSUBH: /* TODO: TX79_MMI0_PSUBH */
+ case TX79_MMI0_PCGTH: /* TODO: TX79_MMI0_PCGTH */
+ case TX79_MMI0_PMAXH: /* TODO: TX79_MMI0_PMAXH */
+ case TX79_MMI0_PADDB: /* TODO: TX79_MMI0_PADDB */
+ case TX79_MMI0_PSUBB: /* TODO: TX79_MMI0_PSUBB */
+ case TX79_MMI0_PCGTB: /* TODO: TX79_MMI0_PCGTB */
+ case TX79_MMI0_PADDSW: /* TODO: TX79_MMI0_PADDSW */
+ case TX79_MMI0_PSUBSW: /* TODO: TX79_MMI0_PSUBSW */
+ case TX79_MMI0_PEXTLW: /* TODO: TX79_MMI0_PEXTLW */
+ case TX79_MMI0_PPACW: /* TODO: TX79_MMI0_PPACW */
+ case TX79_MMI0_PADDSH: /* TODO: TX79_MMI0_PADDSH */
+ case TX79_MMI0_PSUBSH: /* TODO: TX79_MMI0_PSUBSH */
+ case TX79_MMI0_PEXTLH: /* TODO: TX79_MMI0_PEXTLH */
+ case TX79_MMI0_PPACH: /* TODO: TX79_MMI0_PPACH */
+ case TX79_MMI0_PADDSB: /* TODO: TX79_MMI0_PADDSB */
+ case TX79_MMI0_PSUBSB: /* TODO: TX79_MMI0_PSUBSB */
+ case TX79_MMI0_PEXTLB: /* TODO: TX79_MMI0_PEXTLB */
+ case TX79_MMI0_PPACB: /* TODO: TX79_MMI0_PPACB */
+ case TX79_MMI0_PEXT5: /* TODO: TX79_MMI0_PEXT5 */
+ case TX79_MMI0_PPAC5: /* TODO: TX79_MMI0_PPAC5 */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI0 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI0");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
switch (opc) {
+ case TX79_MMI_CLASS_MMI0:
+ decode_tx79_mmi0(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_CLASS_MMI0: /* TODO: TX79_MMI_CLASS_MMI0 */
case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 instruction subclass
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (12 preceding siblings ...)
2018-10-21 15:36 ` [Qemu-devel] [PATCH v8 13/38] target/mips: Placeholder for R5900 MMI0 instruction subclass Fredrik Noring
@ 2018-10-21 15:36 ` Fredrik Noring
2018-10-21 15:37 ` [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 " Fredrik Noring
` (24 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:36 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 36 +++++++++++++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c8080844f1..28137cdaf4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24459,6 +24459,38 @@ static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI1(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI1_PABSW: /* TODO: TX79_MMI1_PABSW */
+ case TX79_MMI1_PCEQW: /* TODO: TX79_MMI1_PCEQW */
+ case TX79_MMI1_PMINW: /* TODO: TX79_MMI1_PMINW */
+ case TX79_MMI1_PADSBH: /* TODO: TX79_MMI1_PADSBH */
+ case TX79_MMI1_PABSH: /* TODO: TX79_MMI1_PABSH */
+ case TX79_MMI1_PCEQH: /* TODO: TX79_MMI1_PCEQH */
+ case TX79_MMI1_PMINH: /* TODO: TX79_MMI1_PMINH */
+ case TX79_MMI1_PCEQB: /* TODO: TX79_MMI1_PCEQB */
+ case TX79_MMI1_PADDUW: /* TODO: TX79_MMI1_PADDUW */
+ case TX79_MMI1_PSUBUW: /* TODO: TX79_MMI1_PSUBUW */
+ case TX79_MMI1_PEXTUW: /* TODO: TX79_MMI1_PEXTUW */
+ case TX79_MMI1_PADDUH: /* TODO: TX79_MMI1_PADDUH */
+ case TX79_MMI1_PSUBUH: /* TODO: TX79_MMI1_PSUBUH */
+ case TX79_MMI1_PEXTUH: /* TODO: TX79_MMI1_PEXTUH */
+ case TX79_MMI1_PADDUB: /* TODO: TX79_MMI1_PADDUB */
+ case TX79_MMI1_PSUBUB: /* TODO: TX79_MMI1_PSUBUB */
+ case TX79_MMI1_PEXTUB: /* TODO: TX79_MMI1_PEXTUB */
+ case TX79_MMI1_QFSRV: /* TODO: TX79_MMI1_QFSRV */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI1 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI1");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
@@ -24467,6 +24499,9 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_CLASS_MMI0:
decode_tx79_mmi0(env, ctx);
break;
+ case TX79_MMI_CLASS_MMI1:
+ decode_tx79_mmi1(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
@@ -24481,7 +24516,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
- case TX79_MMI_CLASS_MMI1: /* TODO: TX79_MMI_CLASS_MMI1 */
case TX79_MMI_CLASS_MMI3: /* TODO: TX79_MMI_CLASS_MMI3 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 instruction subclass
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (13 preceding siblings ...)
2018-10-21 15:36 ` [Qemu-devel] [PATCH v8 14/38] target/mips: Placeholder for R5900 MMI1 " Fredrik Noring
@ 2018-10-21 15:37 ` Fredrik Noring
2018-10-21 15:37 ` [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 " Fredrik Noring
` (23 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:37 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 28137cdaf4..e5ac9f17e0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24491,6 +24491,42 @@ static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI2(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI2_PMADDW: /* TODO: TX79_MMI2_PMADDW */
+ case TX79_MMI2_PSLLVW: /* TODO: TX79_MMI2_PSLLVW */
+ case TX79_MMI2_PSRLVW: /* TODO: TX79_MMI2_PSRLVW */
+ case TX79_MMI2_PMSUBW: /* TODO: TX79_MMI2_PMSUBW */
+ case TX79_MMI2_PMFHI: /* TODO: TX79_MMI2_PMFHI */
+ case TX79_MMI2_PMFLO: /* TODO: TX79_MMI2_PMFLO */
+ case TX79_MMI2_PINTH: /* TODO: TX79_MMI2_PINTH */
+ case TX79_MMI2_PMULTW: /* TODO: TX79_MMI2_PMULTW */
+ case TX79_MMI2_PDIVW: /* TODO: TX79_MMI2_PDIVW */
+ case TX79_MMI2_PCPYLD: /* TODO: TX79_MMI2_PCPYLD */
+ case TX79_MMI2_PMADDH: /* TODO: TX79_MMI2_PMADDH */
+ case TX79_MMI2_PHMADH: /* TODO: TX79_MMI2_PHMADH */
+ case TX79_MMI2_PAND: /* TODO: TX79_MMI2_PAND */
+ case TX79_MMI2_PXOR: /* TODO: TX79_MMI2_PXOR */
+ case TX79_MMI2_PMSUBH: /* TODO: TX79_MMI2_PMSUBH */
+ case TX79_MMI2_PHMSBH: /* TODO: TX79_MMI2_PHMSBH */
+ case TX79_MMI2_PEXEH: /* TODO: TX79_MMI2_PEXEH */
+ case TX79_MMI2_PREVH: /* TODO: TX79_MMI2_PREVH */
+ case TX79_MMI2_PMULTH: /* TODO: TX79_MMI2_PMULTH */
+ case TX79_MMI2_PDIVBW: /* TODO: TX79_MMI2_PDIVBW */
+ case TX79_MMI2_PEXEW: /* TODO: TX79_MMI2_PEXEW */
+ case TX79_MMI2_PROT3W: /* TODO: TX79_MMI2_PROT3W */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI2 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI2");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
@@ -24502,10 +24538,12 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_CLASS_MMI1:
decode_tx79_mmi1(env, ctx);
break;
+ case TX79_MMI_CLASS_MMI2:
+ decode_tx79_mmi2(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 instruction subclass
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (14 preceding siblings ...)
2018-10-21 15:37 ` [Qemu-devel] [PATCH v8 15/38] target/mips: Placeholder for R5900 MMI2 " Fredrik Noring
@ 2018-10-21 15:37 ` Fredrik Noring
2018-10-21 15:38 ` [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU Fredrik Noring
` (22 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:37 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e5ac9f17e0..6d837082a9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24527,6 +24527,33 @@ static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
}
}
+static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI3(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI3_PMADDUW: /* TODO: TX79_MMI3_PMADDUW */
+ case TX79_MMI3_PSRAVW: /* TODO: TX79_MMI3_PSRAVW */
+ case TX79_MMI3_PMTHI: /* TODO: TX79_MMI3_PMTHI */
+ case TX79_MMI3_PMTLO: /* TODO: TX79_MMI3_PMTLO */
+ case TX79_MMI3_PINTEH: /* TODO: TX79_MMI3_PINTEH */
+ case TX79_MMI3_PMULTUW: /* TODO: TX79_MMI3_PMULTUW */
+ case TX79_MMI3_PDIVUW: /* TODO: TX79_MMI3_PDIVUW */
+ case TX79_MMI3_PCPYUD: /* TODO: TX79_MMI3_PCPYUD */
+ case TX79_MMI3_POR: /* TODO: TX79_MMI3_POR */
+ case TX79_MMI3_PNOR: /* TODO: TX79_MMI3_PNOR */
+ case TX79_MMI3_PEXCH: /* TODO: TX79_MMI3_PEXCH */
+ case TX79_MMI3_PCPYH: /* TODO: TX79_MMI3_PCPYH */
+ case TX79_MMI3_PEXCW: /* TODO: TX79_MMI3_PEXCW */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI3 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI3");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
@@ -24541,6 +24568,9 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_CLASS_MMI2:
decode_tx79_mmi2(env, ctx);
break;
+ case TX79_MMI_CLASS_MMI3:
+ decode_tx79_mmi3(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
@@ -24554,7 +24584,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
- case TX79_MMI_CLASS_MMI3: /* TODO: TX79_MMI_CLASS_MMI3 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
case TX79_MMI_PSLLH: /* TODO: TX79_MMI_PSLLH */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (15 preceding siblings ...)
2018-10-21 15:37 ` [Qemu-devel] [PATCH v8 16/38] target/mips: Placeholder for R5900 MMI3 " Fredrik Noring
@ 2018-10-21 15:38 ` Fredrik Noring
2018-10-21 15:38 ` [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1 Fredrik Noring
` (21 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:38 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
The three-operand MULT and MULTU are the only R5900-specific
instructions emitted by GCC 7.3. The R5900 also implements the three-
operand MADD and MADDU instructions, but they are omitted in QEMU for
now since they are absent in programs compiled by current GCC versions.
Likewise, the R5900-specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1
are omitted here as well.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6d837082a9..eb7437cc09 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4766,6 +4766,78 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
+/*
+ * These MULT and MULTU instructions implemented in for example the
+ * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * architectures are special three-operand variants with the syntax
+ *
+ * MULT[U] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- rs * rt
+ *
+ * where the low-order 32-bits of the result is placed into both the
+ * GPR rd and the special register LO. The high-order 32-bits of the
+ * result is placed into the special register HI.
+ *
+ * If the GPR rd is omitted in assembly language, it is taken to be 0,
+ * which is the zero register that always reads as 0.
+ */
+static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
+ int rd, int rs, int rt)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ int acc = 0;
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ switch (opc) {
+ case OPC_MULT:
+ {
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_muls2_i32(t2, t3, t2, t3);
+ if (rd) {
+ tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
+ }
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
+ case OPC_MULTU:
+ {
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_mulu2_i32(t2, t3, t2, t3);
+ if (rd) {
+ tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
+ }
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
+ default:
+ MIPS_INVAL("mul TXx9");
+ generate_exception_end(ctx, EXCP_RI);
+ goto out;
+ }
+
+ out:
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
@@ -23490,6 +23562,8 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, INSN_VR54XX);
op1 = MASK_MUL_VR54XX(ctx->opcode);
gen_mul_vr54xx(ctx, op1, rd, rs, rt);
+ } else if (ctx->insn_flags & INSN_R5900) {
+ gen_mul_txx9(ctx, op1, rd, rs, rt);
} else {
gen_muldiv(ctx, op1, rd & 3, rs, rt);
}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (16 preceding siblings ...)
2018-10-21 15:38 ` [Qemu-devel] [PATCH v8 17/38] target/mips: Support R5900 three-operand MULT and MULTU Fredrik Noring
@ 2018-10-21 15:38 ` Fredrik Noring
2018-10-21 15:38 ` [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 Fredrik Noring
` (20 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:38 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
target/mips/translate.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index eb7437cc09..df69fa0e9f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4771,7 +4771,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
* Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
* architectures are special three-operand variants with the syntax
*
- * MULT[U] rd, rs, rt
+ * MULT[U][1] rd, rs, rt
*
* such that
*
@@ -4795,6 +4795,9 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
switch (opc) {
+ case TX79_MMI_MULT1:
+ acc = 1;
+ /* Fall through */
case OPC_MULT:
{
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -4811,6 +4814,9 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free_i32(t3);
}
break;
+ case TX79_MMI_MULTU1:
+ acc = 1;
+ /* Fall through */
case OPC_MULTU:
{
TCGv_i32 t2 = tcg_temp_new_i32();
@@ -24631,6 +24637,9 @@ static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
+ int rs = extract32(ctx->opcode, 21, 5);
+ int rt = extract32(ctx->opcode, 16, 5);
+ int rd = extract32(ctx->opcode, 11, 5);
switch (opc) {
case TX79_MMI_CLASS_MMI0:
@@ -24645,6 +24654,10 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_CLASS_MMI3:
decode_tx79_mmi3(env, ctx);
break;
+ case TX79_MMI_MULT1:
+ case TX79_MMI_MULTU1:
+ gen_mul_txx9(ctx, opc, rd, rs, rt);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
@@ -24652,8 +24665,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
case TX79_MMI_MTLO1: /* TODO: TX79_MMI_MTLO1 */
- case TX79_MMI_MULT1: /* TODO: TX79_MMI_MULT1 */
- case TX79_MMI_MULTU1: /* TODO: TX79_MMI_MULTU1 */
case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */
case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (17 preceding siblings ...)
2018-10-21 15:38 ` [Qemu-devel] [PATCH v8 18/38] target/mips: Support R5900 three-operand MULT1 and MULTU1 Fredrik Noring
@ 2018-10-21 15:38 ` Fredrik Noring
2018-10-21 15:39 ` [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1 Fredrik Noring
` (19 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:38 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
disas/mips.c | 4 ++++
target/mips/translate.c | 23 +++++++++++++++++------
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index ae72059c46..e86a2b8764 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2594,8 +2594,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
+{"mfhi1", "d", 0x70000010, 0xffff07ff, WR_d|RD_HI, 0, EE },
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
+{"mflo1", "d", 0x70000012, 0xffff07ff, WR_d|RD_LO, 0, EE },
{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
@@ -2661,8 +2663,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
+{"mthi1", "s", 0x70000011, 0xfc1fffff, RD_s|WR_HI, 0, EE },
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
+{"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_s|WR_LO, 0, EE },
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
diff --git a/target/mips/translate.c b/target/mips/translate.c
index df69fa0e9f..2cff740bac 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4229,17 +4229,21 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
{
- if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
+ if (reg == 0 && (opc == OPC_MFHI || opc == TX79_MMI_MFHI1 ||
+ opc == OPC_MFLO || opc == TX79_MMI_MFLO1)) {
/* Treat as NOP. */
return;
}
if (acc != 0) {
- check_dsp(ctx);
+ if (!(ctx->insn_flags & INSN_R5900)) {
+ check_dsp(ctx);
+ }
}
switch (opc) {
case OPC_MFHI:
+ case TX79_MMI_MFHI1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
@@ -4250,6 +4254,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MFLO:
+ case TX79_MMI_MFLO1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
@@ -4260,6 +4265,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MTHI:
+ case TX79_MMI_MTHI1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@@ -4274,6 +4280,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
}
break;
case OPC_MTLO:
+ case TX79_MMI_MTLO1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@@ -24658,13 +24665,17 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MULTU1:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
+ case TX79_MMI_MTLO1:
+ case TX79_MMI_MTHI1:
+ gen_HILO(ctx, opc, 1, rs);
+ break;
+ case TX79_MMI_MFLO1:
+ case TX79_MMI_MFHI1:
+ gen_HILO(ctx, opc, 1, rd);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
- case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
- case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
- case TX79_MMI_MTLO1: /* TODO: TX79_MMI_MTLO1 */
case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */
case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (18 preceding siblings ...)
2018-10-21 15:38 ` [Qemu-devel] [PATCH v8 19/38] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 Fredrik Noring
@ 2018-10-21 15:39 ` Fredrik Noring
2018-10-21 15:39 ` [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV Fredrik Noring
` (18 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:39 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
disas/mips.c | 4 ++++
target/mips/translate.c | 12 +++++++++---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index e86a2b8764..79bd119c51 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2323,6 +2323,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
+{"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE, },
+{"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, EE, },
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
@@ -2331,6 +2333,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
+{"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, EE },
+{"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_s|WR_HILO, 0, EE, },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2cff740bac..e2ac401d42 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4593,11 +4593,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
gen_load_gpr(t1, rt);
if (acc != 0) {
- check_dsp(ctx);
+ if (!(ctx->insn_flags & INSN_R5900)) {
+ check_dsp(ctx);
+ }
}
switch (opc) {
case OPC_DIV:
+ case TX79_MMI_DIV1:
{
TCGv t2 = tcg_temp_new();
TCGv t3 = tcg_temp_new();
@@ -4619,6 +4622,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
break;
case OPC_DIVU:
+ case TX79_MMI_DIVU1:
{
TCGv t2 = tcg_const_tl(0);
TCGv t3 = tcg_const_tl(1);
@@ -24665,6 +24669,10 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MULTU1:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
+ case TX79_MMI_DIV1:
+ case TX79_MMI_DIVU1:
+ gen_muldiv(ctx, opc, 1, rs, rt);
+ break;
case TX79_MMI_MTLO1:
case TX79_MMI_MTHI1:
gen_HILO(ctx, opc, 1, rs);
@@ -24676,8 +24684,6 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_DIV1: /* TODO: TX79_MMI_DIV1 */
- case TX79_MMI_DIVU1: /* TODO: TX79_MMI_DIVU1 */
case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (19 preceding siblings ...)
2018-10-21 15:39 ` [Qemu-devel] [PATCH v8 20/38] target/mips: Support R5900 DIV1 and DIVU1 Fredrik Noring
@ 2018-10-21 15:39 ` Fredrik Noring
2018-10-21 15:39 ` [Qemu-devel] [PATCH v8 22/38] target/mips: Support R5900 three-operand MADD and MADD1 Fredrik Noring
` (17 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:39 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e2ac401d42..1f3dc3d406 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23552,7 +23552,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
- INSN_LOONGSON2E | INSN_LOONGSON2F);
+ INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
@@ -26388,7 +26388,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_PREF:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ INSN_R5900);
/* Treat as NOP. */
break;
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 22/38] target/mips: Support R5900 three-operand MADD and MADD1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (20 preceding siblings ...)
2018-10-21 15:39 ` [Qemu-devel] [PATCH v8 21/38] target/mips: Support R5900 MOVN, MOVZ and PREF from MIPS IV Fredrik Noring
@ 2018-10-21 15:39 ` Fredrik Noring
2018-10-21 15:40 ` [Qemu-devel] [PATCH v8 23/38] target/mips: Support R5900 three-operand MADDU and MADDU1 Fredrik Noring
` (16 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:39 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
disas/mips.c | 2 ++
target/mips/translate.c | 38 +++++++++++++++++++++++++++++++++-----
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 79bd119c51..242bf68b9c 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2553,6 +2553,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
+{"madd1", "s,t", 0x70000020, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE },
+{"madd1", "d,s,t", 0x70000020, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE },
{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1f3dc3d406..153b7e869a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4778,8 +4778,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
/*
- * These MULT and MULTU instructions implemented in for example the
- * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * These MULT[U] and MADD instructions implemented in for example
+ * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
* architectures are special three-operand variants with the syntax
*
* MULT[U][1] rd, rs, rt
@@ -4788,6 +4788,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
*
* (rd, LO, HI) <- rs * rt
*
+ * and
+ *
+ * MADD[1] rd, rs, rt
+ *
+ * such that
+ *
+ * (rd, LO, HI) <- (LO, HI) + rs * rt
+ *
* where the low-order 32-bits of the result is placed into both the
* GPR rd and the special register LO. The high-order 32-bits of the
* result is placed into the special register HI.
@@ -4844,8 +4852,28 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free_i32(t3);
}
break;
+ case TX79_MMI_MADD1:
+ acc = 1;
+ /* Fall through */
+ case TX79_MMI_MADD:
+ {
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_muls2_i32(t2, t3, t2, t3);
+ tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
+ if (rd) {
+ tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
+ }
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
default:
- MIPS_INVAL("mul TXx9");
+ MIPS_INVAL("mul/madd TXx9");
generate_exception_end(ctx, EXCP_RI);
goto out;
}
@@ -24667,6 +24695,8 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
break;
case TX79_MMI_MULT1:
case TX79_MMI_MULTU1:
+ case TX79_MMI_MADD:
+ case TX79_MMI_MADD1:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
case TX79_MMI_DIV1:
@@ -24681,10 +24711,8 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MFHI1:
gen_HILO(ctx, opc, 1, rd);
break;
- case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_MADD1: /* TODO: TX79_MMI_MADD1 */
case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 23/38] target/mips: Support R5900 three-operand MADDU and MADDU1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (21 preceding siblings ...)
2018-10-21 15:39 ` [Qemu-devel] [PATCH v8 22/38] target/mips: Support R5900 three-operand MADD and MADD1 Fredrik Noring
@ 2018-10-21 15:40 ` Fredrik Noring
2018-10-21 15:40 ` [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only Fredrik Noring
` (15 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:40 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
disas/mips.c | 2 ++
target/mips/translate.c | 28 ++++++++++++++++++++++++----
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/disas/mips.c b/disas/mips.c
index 242bf68b9c..78c4fb6efa 100644
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2561,6 +2561,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
+{"maddu1", "s,t", 0x70000021, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, EE },
+{"maddu1", "d,s,t", 0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, EE },
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 153b7e869a..3977c57a22 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4778,7 +4778,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
}
/*
- * These MULT[U] and MADD instructions implemented in for example
+ * These MULT[U] and MADD[U] instructions implemented in for example
* the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
* architectures are special three-operand variants with the syntax
*
@@ -4790,7 +4790,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
*
* and
*
- * MADD[1] rd, rs, rt
+ * MADD[U][1] rd, rs, rt
*
* such that
*
@@ -4872,6 +4872,26 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
tcg_temp_free_i32(t3);
}
break;
+ case TX79_MMI_MADDU1:
+ acc = 1;
+ /* Fall through */
+ case TX79_MMI_MADDU:
+ {
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t2, t0);
+ tcg_gen_trunc_tl_i32(t3, t1);
+ tcg_gen_mulu2_i32(t2, t3, t2, t3);
+ tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
+ if (rd) {
+ tcg_gen_ext_i32_tl(cpu_gpr[rd], t2);
+ }
+ tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
+ tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t3);
+ }
+ break;
default:
MIPS_INVAL("mul/madd TXx9");
generate_exception_end(ctx, EXCP_RI);
@@ -24697,6 +24717,8 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MULTU1:
case TX79_MMI_MADD:
case TX79_MMI_MADD1:
+ case TX79_MMI_MADDU:
+ case TX79_MMI_MADDU1:
gen_mul_txx9(ctx, opc, rd, rs, rt);
break;
case TX79_MMI_DIV1:
@@ -24711,9 +24733,7 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
case TX79_MMI_MFHI1:
gen_HILO(ctx, opc, 1, rd);
break;
- case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_MADDU1: /* TODO: TX79_MMI_MADDU1 */
case TX79_MMI_PMFHL: /* TODO: TX79_MMI_PMFHL */
case TX79_MMI_PMTHL: /* TODO: TX79_MMI_PMTHL */
case TX79_MMI_PSLLH: /* TODO: TX79_MMI_PSLLH */
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (22 preceding siblings ...)
2018-10-21 15:40 ` [Qemu-devel] [PATCH v8 23/38] target/mips: Support R5900 three-operand MADDU and MADDU1 Fredrik Noring
@ 2018-10-21 15:40 ` Fredrik Noring
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 25/38] tests/tcg/mips: Test R5900 three-operand MULT Fredrik Noring
` (14 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:40 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
The Linux kernel traps certain reserved instruction exceptions to
emulate the corresponding instructions. QEMU is the kernel in user
mode, so those traps are emulated by accepting the instructions.
This change adds the function check_insn_opc_user_only to signal a
reserved instruction exception for flagged CPUs in QEMU system mode.
The MIPS III instructions DMULT[U], DDIV[U], LL[D] and SC[D] are not
implemented in R5900 hardware. They are trapped and emulated by the
Linux kernel and, accordingly, therefore QEMU user only instructions.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3977c57a22..066119c3e1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2872,6 +2872,21 @@ static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
}
}
+/*
+ * The Linux kernel traps certain reserved instruction exceptions to
+ * emulate the corresponding instructions. QEMU is the kernel in user
+ * mode, so those traps are emulated by accepting the instructions.
+ *
+ * A reserved instruction exception is generated for flagged CPUs if
+ * QEMU runs in system mode.
+ */
+static inline void check_insn_opc_user_only(DisasContext *ctx, uint64_t flags)
+{
+#ifndef CONFIG_USER_ONLY
+ check_insn_opc_removed(ctx, flags);
+#endif
+}
+
/* This code generates a "reserved instruction" exception if the
CPU does not support 64-bit paired-single (PS) floating point data type */
static inline void check_ps(DisasContext *ctx)
@@ -23643,6 +23658,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_DDIV:
case OPC_DDIVU:
check_insn(ctx, ISA_MIPS3);
+ check_insn_opc_user_only(ctx, INSN_R5900);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
break;
@@ -26398,6 +26414,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_LL: /* Load and stores */
check_insn(ctx, ISA_MIPS2);
+ check_insn_opc_user_only(ctx, INSN_R5900);
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
@@ -26423,6 +26440,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_user_only(ctx, INSN_R5900);
gen_st_cond(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
@@ -26689,9 +26707,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
+ case OPC_LLD:
+ check_insn_opc_user_only(ctx, INSN_R5900);
+ /* fall through */
case OPC_LDL:
case OPC_LDR:
- case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
case OPC_LWU:
@@ -26712,6 +26732,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_SCD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS3);
+ check_insn_opc_user_only(ctx, INSN_R5900);
check_mips_64(ctx);
gen_st_cond(ctx, op, rt, rs, imm);
break;
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 25/38] tests/tcg/mips: Test R5900 three-operand MULT
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (23 preceding siblings ...)
2018-10-21 15:40 ` [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only Fredrik Noring
@ 2018-10-21 15:41 ` Fredrik Noring
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 26/38] tests/tcg/mips: Test R5900 three-operand MULTU Fredrik Noring
` (13 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:41 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 25 ++++++++++++++++
tests/tcg/mips/mipsr5900/mult.c | 47 +++++++++++++++++++++++++++++++
2 files changed, 72 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/Makefile
create mode 100644 tests/tcg/mips/mipsr5900/mult.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
new file mode 100644
index 0000000000..6757168fc9
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -0,0 +1,25 @@
+-include ../../config-host.mak
+
+CROSS=mipsr5900el-unknown-linux-gnu-
+
+SIM=qemu-mipsel
+SIM_FLAGS=-cpu R5900
+
+CC = $(CROSS)gcc
+CFLAGS = -Wall -mabi=32 -march=r5900 -static
+
+TESTCASES = mult.tst
+
+all: $(TESTCASES)
+
+%.tst: %.c
+ $(CC) $(CFLAGS) $< -o $@
+
+check: $(TESTCASES)
+ @for case in $(TESTCASES); do \
+ echo $(SIM) $(SIM_FLAGS) ./$$case;\
+ $(SIM) $(SIM_FLAGS) ./$$case; \
+ done
+
+clean:
+ $(RM) -rf $(TESTCASES)
diff --git a/tests/tcg/mips/mipsr5900/mult.c b/tests/tcg/mips/mipsr5900/mult.c
new file mode 100644
index 0000000000..2c0c16d232
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/mult.c
@@ -0,0 +1,47 @@
+/*
+ * Test R5900-specific three-operand MULT.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+static int64_t mult(int32_t rs, int32_t rt)
+{
+ int32_t rd, lo, hi;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mult %0, %3, %4\n"
+ " mflo %1\n"
+ " mfhi %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert((int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static void verify_mult_negations(int32_t rs, int32_t rt, int64_t expected)
+{
+ assert(mult(rs, rt) == expected);
+ assert(mult(-rs, rt) == -expected);
+ assert(mult(rs, -rt) == -expected);
+ assert(mult(-rs, -rt) == expected);
+}
+
+int main()
+{
+ verify_mult_negations(17, 19, 323);
+ verify_mult_negations(77773, 99991, 7776600043);
+ verify_mult_negations(12207031, 305175781, 3725290219116211);
+
+ assert(mult(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
+ assert(mult(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
+ assert(mult(-0x80000000, -0x80000000) == 0x4000000000000000);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 26/38] tests/tcg/mips: Test R5900 three-operand MULTU
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (24 preceding siblings ...)
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 25/38] tests/tcg/mips: Test R5900 three-operand MULT Fredrik Noring
@ 2018-10-21 15:41 ` Fredrik Noring
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 27/38] tests/tcg/mips: Test R5900 three-operand MULT1 Fredrik Noring
` (12 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:41 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/multu.c | 39 +++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/multu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index 6757168fc9..b3ddb9a7bf 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -9,6 +9,7 @@ CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
TESTCASES = mult.tst
+TESTCASES += multu.tst
all: $(TESTCASES)
diff --git a/tests/tcg/mips/mipsr5900/multu.c b/tests/tcg/mips/mipsr5900/multu.c
new file mode 100644
index 0000000000..3a59675395
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/multu.c
@@ -0,0 +1,39 @@
+/*
+ * Test R5900-specific three-operand MULTU.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+static uint64_t multu(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd, lo, hi;
+ uint64_t r;
+
+ __asm__ __volatile__ (
+ " multu %0, %3, %4\n"
+ " mflo %1\n"
+ " mfhi %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+ r = ((uint64_t)hi << 32) | (uint32_t)lo;
+
+ assert((uint64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+int main()
+{
+ assert(multu(17, 19) == 323);
+ assert(multu(77773, 99991) == 7776600043);
+ assert(multu(12207031, 305175781) == 3725290219116211);
+
+ assert(multu(0x80000000U, 0x7FFFFFFF) == 0x3FFFFFFF80000000);
+ assert(multu(0x80000000U, 0x80000000U) == 0x4000000000000000);
+ assert(multu(0xFFFFFFFFU, 0xFFFFFFFFU) == 0xFFFFFFFE00000001U);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 27/38] tests/tcg/mips: Test R5900 three-operand MULT1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (25 preceding siblings ...)
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 26/38] tests/tcg/mips: Test R5900 three-operand MULTU Fredrik Noring
@ 2018-10-21 15:41 ` Fredrik Noring
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 28/38] tests/tcg/mips: Test R5900 three-operand MULTU1 Fredrik Noring
` (11 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:41 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/mult.c | 45 +++++++++++++++++++++++++++------
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/mult.c b/tests/tcg/mips/mipsr5900/mult.c
index 2c0c16d232..5710b395e6 100644
--- a/tests/tcg/mips/mipsr5900/mult.c
+++ b/tests/tcg/mips/mipsr5900/mult.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MULT.
+ * Test R5900-specific three-operand MULT and MULT1.
*/
#include <stdio.h>
@@ -25,12 +25,41 @@ static int64_t mult(int32_t rs, int32_t rt)
return r;
}
+static int64_t mult1(int32_t rs, int32_t rt)
+{
+ int32_t rd, lo, hi;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mult1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert((int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static int64_t mult_variants(int32_t rs, int32_t rt)
+{
+ int64_t rd = mult(rs, rt);
+ int64_t rd1 = mult1(rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
static void verify_mult_negations(int32_t rs, int32_t rt, int64_t expected)
{
- assert(mult(rs, rt) == expected);
- assert(mult(-rs, rt) == -expected);
- assert(mult(rs, -rt) == -expected);
- assert(mult(-rs, -rt) == expected);
+ assert(mult_variants(rs, rt) == expected);
+ assert(mult_variants(-rs, rt) == -expected);
+ assert(mult_variants(rs, -rt) == -expected);
+ assert(mult_variants(-rs, -rt) == expected);
}
int main()
@@ -39,9 +68,9 @@ int main()
verify_mult_negations(77773, 99991, 7776600043);
verify_mult_negations(12207031, 305175781, 3725290219116211);
- assert(mult(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
- assert(mult(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
- assert(mult(-0x80000000, -0x80000000) == 0x4000000000000000);
+ assert(mult_variants(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
+ assert(mult_variants(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
+ assert(mult_variants(-0x80000000, -0x80000000) == 0x4000000000000000);
return 0;
}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 28/38] tests/tcg/mips: Test R5900 three-operand MULTU1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (26 preceding siblings ...)
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 27/38] tests/tcg/mips: Test R5900 three-operand MULT1 Fredrik Noring
@ 2018-10-21 15:41 ` Fredrik Noring
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 29/38] tests/tcg/mips: Test R5900 MFLO1 and MFHI1 Fredrik Noring
` (10 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:41 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/multu.c | 43 ++++++++++++++++++++++++++------
1 file changed, 36 insertions(+), 7 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/multu.c b/tests/tcg/mips/mipsr5900/multu.c
index 3a59675395..f043904d69 100644
--- a/tests/tcg/mips/mipsr5900/multu.c
+++ b/tests/tcg/mips/mipsr5900/multu.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MULTU.
+ * Test R5900-specific three-operand MULTU and MULTU1.
*/
#include <stdio.h>
@@ -25,15 +25,44 @@ static uint64_t multu(uint32_t rs, uint32_t rt)
return r;
}
+static uint64_t multu1(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd, lo, hi;
+ uint64_t r;
+
+ __asm__ __volatile__ (
+ " multu1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+ r = ((uint64_t)hi << 32) | (uint32_t)lo;
+
+ assert((uint64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static uint64_t multu_variants(uint32_t rs, uint32_t rt)
+{
+ uint64_t rd = multu(rs, rt);
+ uint64_t rd1 = multu1(rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
int main()
{
- assert(multu(17, 19) == 323);
- assert(multu(77773, 99991) == 7776600043);
- assert(multu(12207031, 305175781) == 3725290219116211);
+ assert(multu_variants(17, 19) == 323);
+ assert(multu_variants(77773, 99991) == 7776600043);
+ assert(multu_variants(12207031, 305175781) == 3725290219116211);
- assert(multu(0x80000000U, 0x7FFFFFFF) == 0x3FFFFFFF80000000);
- assert(multu(0x80000000U, 0x80000000U) == 0x4000000000000000);
- assert(multu(0xFFFFFFFFU, 0xFFFFFFFFU) == 0xFFFFFFFE00000001U);
+ assert(multu_variants(0x80000000U, 0x7FFFFFFF) == 0x3FFFFFFF80000000);
+ assert(multu_variants(0x80000000U, 0x80000000U) == 0x4000000000000000);
+ assert(multu_variants(0xFFFFFFFFU, 0xFFFFFFFFU) == 0xFFFFFFFE00000001U);
return 0;
}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 29/38] tests/tcg/mips: Test R5900 MFLO1 and MFHI1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (27 preceding siblings ...)
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 28/38] tests/tcg/mips: Test R5900 three-operand MULTU1 Fredrik Noring
@ 2018-10-21 15:41 ` Fredrik Noring
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 30/38] tests/tcg/mips: Test R5900 MTLO1 and MTHI1 Fredrik Noring
` (9 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:41 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 3 ++-
tests/tcg/mips/mipsr5900/mflohi1.c | 35 ++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsr5900/mflohi1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index b3ddb9a7bf..fd8ee6b0e3 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -8,7 +8,8 @@ SIM_FLAGS=-cpu R5900
CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
-TESTCASES = mult.tst
+TESTCASES = mflohi1.tst
+TESTCASES += mult.tst
TESTCASES += multu.tst
all: $(TESTCASES)
diff --git a/tests/tcg/mips/mipsr5900/mflohi1.c b/tests/tcg/mips/mipsr5900/mflohi1.c
new file mode 100644
index 0000000000..eed3683dc5
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/mflohi1.c
@@ -0,0 +1,35 @@
+/*
+ * Test R5900-specific MFLO1 and MFHI1.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+int main()
+{
+ int32_t rs = 12207031, rt = 305175781;
+ int32_t rs1 = 32452867, rt1 = 49979687;
+ int64_t lo, hi, lo1, hi1;
+ int64_t r, r1;
+
+ /* Test both LO/HI and LO1/HI1 to verify separation. */
+ __asm__ __volatile__ (
+ " mult $0, %4, %5\n"
+ " mult1 $0, %6, %7\n"
+ " mflo %0\n"
+ " mfhi %1\n"
+ " mflo1 %2\n"
+ " mfhi1 %3\n"
+ : "=r" (lo), "=r" (hi),
+ "=r" (lo1), "=r" (hi1)
+ : "r" (rs), "r" (rt),
+ "r" (rs1), "r" (rt1));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+ r1 = ((int64_t)hi1 << 32) | (uint32_t)lo1;
+
+ assert(r == 3725290219116211);
+ assert(r1 == 1621984134912629);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 30/38] tests/tcg/mips: Test R5900 MTLO1 and MTHI1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (28 preceding siblings ...)
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 29/38] tests/tcg/mips: Test R5900 MFLO1 and MFHI1 Fredrik Noring
@ 2018-10-21 15:41 ` Fredrik Noring
2018-10-21 15:42 ` [Qemu-devel] [PATCH v8 31/38] tests/tcg/mips: Test R5900 DIV1 Fredrik Noring
` (8 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:41 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/mtlohi1.c | 40 ++++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/mtlohi1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index fd8ee6b0e3..287c248f6d 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -9,6 +9,7 @@ CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
TESTCASES = mflohi1.tst
+TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
TESTCASES += multu.tst
diff --git a/tests/tcg/mips/mipsr5900/mtlohi1.c b/tests/tcg/mips/mipsr5900/mtlohi1.c
new file mode 100644
index 0000000000..7f3e72835a
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/mtlohi1.c
@@ -0,0 +1,40 @@
+/*
+ * Test R5900-specific MTLO1 and MTHI1.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+int main()
+{
+ int32_t tlo = 12207031, thi = 305175781;
+ int32_t tlo1 = 32452867, thi1 = 49979687;
+ int32_t flo, fhi, flo1, fhi1;
+
+ /* Test both LO/HI and LO1/HI1 to verify separation. */
+ __asm__ __volatile__ (
+ " mtlo %4\n"
+ " mthi %5\n"
+ " mtlo1 %6\n"
+ " mthi1 %7\n"
+ " move %0, $0\n"
+ " move %1, $0\n"
+ " move %2, $0\n"
+ " move %3, $0\n"
+ " mflo %0\n"
+ " mfhi %1\n"
+ " mflo1 %2\n"
+ " mfhi1 %3\n"
+ : "=r" (flo), "=r" (fhi),
+ "=r" (flo1), "=r" (fhi1)
+ : "r" (tlo), "r" (thi),
+ "r" (tlo1), "r" (thi1));
+
+ assert(flo == 12207031);
+ assert(fhi == 305175781);
+ assert(flo1 == 32452867);
+ assert(fhi1 == 49979687);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 31/38] tests/tcg/mips: Test R5900 DIV1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (29 preceding siblings ...)
2018-10-21 15:41 ` [Qemu-devel] [PATCH v8 30/38] tests/tcg/mips: Test R5900 MTLO1 and MTHI1 Fredrik Noring
@ 2018-10-21 15:42 ` Fredrik Noring
2018-10-21 15:42 ` [Qemu-devel] [PATCH v8 32/38] tests/tcg/mips: Test R5900 DIVU1 Fredrik Noring
` (7 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:42 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 3 +-
tests/tcg/mips/mipsr5900/div1.c | 73 +++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/mips/mipsr5900/div1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index 287c248f6d..757eb83862 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -8,7 +8,8 @@ SIM_FLAGS=-cpu R5900
CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
-TESTCASES = mflohi1.tst
+TESTCASES = div1.tst
+TESTCASES += mflohi1.tst
TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
TESTCASES += multu.tst
diff --git a/tests/tcg/mips/mipsr5900/div1.c b/tests/tcg/mips/mipsr5900/div1.c
new file mode 100644
index 0000000000..83dafa018b
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/div1.c
@@ -0,0 +1,73 @@
+/*
+ * Test R5900-specific DIV1.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+struct quotient_remainder { int32_t quotient, remainder; };
+
+static struct quotient_remainder div1(int32_t rs, int32_t rt)
+{
+ int32_t lo, hi;
+
+ __asm__ __volatile__ (
+ " div1 $0, %2, %3\n"
+ " mflo1 %0\n"
+ " mfhi1 %1\n"
+ : "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+
+ assert(rs / rt == lo);
+ assert(rs % rt == hi);
+
+ return (struct quotient_remainder) { .quotient = lo, .remainder = hi };
+}
+
+static void verify_div1(int32_t rs, int32_t rt,
+ int32_t expected_quotient,
+ int32_t expected_remainder)
+{
+ struct quotient_remainder qr = div1(rs, rt);
+
+ assert(qr.quotient == expected_quotient);
+ assert(qr.remainder == expected_remainder);
+}
+
+static void verify_div1_negations(int32_t rs, int32_t rt,
+ int32_t expected_quotient,
+ int32_t expected_remainder)
+{
+ verify_div1(rs, rt, expected_quotient, expected_remainder);
+ verify_div1(rs, -rt, -expected_quotient, expected_remainder);
+ verify_div1(-rs, rt, -expected_quotient, -expected_remainder);
+ verify_div1(-rs, -rt, expected_quotient, -expected_remainder);
+}
+
+int main()
+{
+ verify_div1_negations(0, 1, 0, 0);
+ verify_div1_negations(1, 1, 1, 0);
+ verify_div1_negations(1, 2, 0, 1);
+ verify_div1_negations(17, 19, 0, 17);
+ verify_div1_negations(19, 17, 1, 2);
+ verify_div1_negations(77773, 101, 770, 3);
+
+ verify_div1(-0x80000000, 1, -0x80000000, 0);
+
+ /*
+ * Supplementary explanation from the Toshiba TX System RISC TX79 Core
+ * Architecture manual, A-38 and B-7, https://wiki.qemu.org/File:C790.pdf
+ *
+ * Normally, when 0x80000000 (-2147483648) the signed minimum value is
+ * divided by 0xFFFFFFFF (-1), the operation will result in an overflow.
+ * However, in this instruction an overflow exception doesn't occur and
+ * the result will be as follows:
+ *
+ * Quotient is 0x80000000 (-2147483648), and remainder is 0x00000000 (0).
+ */
+ verify_div1(-0x80000000, -1, -0x80000000, 0);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 32/38] tests/tcg/mips: Test R5900 DIVU1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (30 preceding siblings ...)
2018-10-21 15:42 ` [Qemu-devel] [PATCH v8 31/38] tests/tcg/mips: Test R5900 DIV1 Fredrik Noring
@ 2018-10-21 15:42 ` Fredrik Noring
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 33/38] tests/tcg/mips: Test R5900 three-operand MADD Fredrik Noring
` (6 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:42 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/divu1.c | 48 +++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/divu1.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index 757eb83862..a1c388bc3c 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -9,6 +9,7 @@ CC = $(CROSS)gcc
CFLAGS = -Wall -mabi=32 -march=r5900 -static
TESTCASES = div1.tst
+TESTCASES += divu1.tst
TESTCASES += mflohi1.tst
TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
diff --git a/tests/tcg/mips/mipsr5900/divu1.c b/tests/tcg/mips/mipsr5900/divu1.c
new file mode 100644
index 0000000000..72aeed31de
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/divu1.c
@@ -0,0 +1,48 @@
+/*
+ * Test R5900-specific DIVU1.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+struct quotient_remainder { uint32_t quotient, remainder; };
+
+static struct quotient_remainder divu1(uint32_t rs, uint32_t rt)
+{
+ uint32_t lo, hi;
+
+ __asm__ __volatile__ (
+ " divu1 $0, %2, %3\n"
+ " mflo1 %0\n"
+ " mfhi1 %1\n"
+ : "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt));
+
+ assert(rs / rt == lo);
+ assert(rs % rt == hi);
+
+ return (struct quotient_remainder) { .quotient = lo, .remainder = hi };
+}
+
+static void verify_divu1(uint32_t rs, uint32_t rt,
+ uint32_t expected_quotient,
+ uint32_t expected_remainder)
+{
+ struct quotient_remainder qr = divu1(rs, rt);
+
+ assert(qr.quotient == expected_quotient);
+ assert(qr.remainder == expected_remainder);
+}
+
+int main()
+{
+ verify_divu1(0, 1, 0, 0);
+ verify_divu1(1, 1, 1, 0);
+ verify_divu1(1, 2, 0, 1);
+ verify_divu1(17, 19, 0, 17);
+ verify_divu1(19, 17, 1, 2);
+ verify_divu1(77773, 101, 770, 3);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 33/38] tests/tcg/mips: Test R5900 three-operand MADD
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (31 preceding siblings ...)
2018-10-21 15:42 ` [Qemu-devel] [PATCH v8 32/38] tests/tcg/mips: Test R5900 DIVU1 Fredrik Noring
@ 2018-10-21 15:43 ` Fredrik Noring
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 34/38] tests/tcg/mips: Test R5900 three-operand MADD1 Fredrik Noring
` (5 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:43 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/madd.c | 45 +++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/madd.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index a1c388bc3c..97ca2a671c 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -10,6 +10,7 @@ CFLAGS = -Wall -mabi=32 -march=r5900 -static
TESTCASES = div1.tst
TESTCASES += divu1.tst
+TESTCASES += madd.tst
TESTCASES += mflohi1.tst
TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
new file mode 100644
index 0000000000..9ad2ea6dbb
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/madd.c
@@ -0,0 +1,45 @@
+/*
+ * Test R5900-specific three-operand MADD.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+int64_t madd(int64_t a, int32_t rs, int32_t rt)
+{
+ int32_t lo = a;
+ int32_t hi = a >> 32;
+ int32_t rd;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mtlo %5\n"
+ " mthi %6\n"
+ " madd %0, %3, %4\n"
+ " mflo %1\n"
+ " mfhi %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt), "r" (lo), "r" (hi));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert(a + (int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static void verify_madd(int64_t a, int32_t rs, int32_t rt, int64_t expected)
+{
+ assert(madd(a, rs, rt) == expected);
+ assert(madd(a, -rs, rt) == a + a - expected);
+ assert(madd(a, rs, -rt) == a + a - expected);
+ assert(madd(a, -rs, -rt) == expected);
+}
+
+int main()
+{
+ verify_madd(13, 17, 19, 336);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 34/38] tests/tcg/mips: Test R5900 three-operand MADD1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (32 preceding siblings ...)
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 33/38] tests/tcg/mips: Test R5900 three-operand MADD Fredrik Noring
@ 2018-10-21 15:43 ` Fredrik Noring
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 35/38] tests/tcg/mips: Test R5900 three-operand MADDU Fredrik Noring
` (4 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:43 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/madd.c | 43 +++++++++++++++++++++++++++++----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips/mipsr5900/madd.c
+++ b/tests/tcg/mips/mipsr5900/madd.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MADD.
+ * Test R5900-specific three-operand MADD and MADD1.
*/
#include <stdio.h>
@@ -29,12 +29,45 @@ int64_t madd(int64_t a, int32_t rs, int32_t rt)
return r;
}
+int64_t madd1(int64_t a, int32_t rs, int32_t rt)
+{
+ int32_t lo = a;
+ int32_t hi = a >> 32;
+ int32_t rd;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mtlo1 %5\n"
+ " mthi1 %6\n"
+ " madd1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt), "r" (lo), "r" (hi));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert(a + (int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static int64_t madd_variants(int64_t a, int32_t rs, int32_t rt)
+{
+ int64_t rd = madd(a, rs, rt);
+ int64_t rd1 = madd1(a, rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
static void verify_madd(int64_t a, int32_t rs, int32_t rt, int64_t expected)
{
- assert(madd(a, rs, rt) == expected);
- assert(madd(a, -rs, rt) == a + a - expected);
- assert(madd(a, rs, -rt) == a + a - expected);
- assert(madd(a, -rs, -rt) == expected);
+ assert(madd_variants(a, rs, rt) == expected);
+ assert(madd_variants(a, -rs, rt) == a + a - expected);
+ assert(madd_variants(a, rs, -rt) == a + a - expected);
+ assert(madd_variants(a, -rs, -rt) == expected);
}
int main()
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 35/38] tests/tcg/mips: Test R5900 three-operand MADDU
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (33 preceding siblings ...)
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 34/38] tests/tcg/mips: Test R5900 three-operand MADD1 Fredrik Noring
@ 2018-10-21 15:43 ` Fredrik Noring
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 36/38] tests/tcg/mips: Test R5900 three-operand MADDU1 Fredrik Noring
` (3 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:43 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/Makefile | 1 +
tests/tcg/mips/mipsr5900/maddu.c | 37 +++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile
index 97ca2a671c..27ee5d5f54 100644
--- a/tests/tcg/mips/mipsr5900/Makefile
+++ b/tests/tcg/mips/mipsr5900/Makefile
@@ -11,6 +11,7 @@ CFLAGS = -Wall -mabi=32 -march=r5900 -static
TESTCASES = div1.tst
TESTCASES += divu1.tst
TESTCASES += madd.tst
+TESTCASES += maddu.tst
TESTCASES += mflohi1.tst
TESTCASES += mtlohi1.tst
TESTCASES += mult.tst
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
new file mode 100644
index 0000000000..e4e552102d
--- /dev/null
+++ b/tests/tcg/mips/mipsr5900/maddu.c
@@ -0,0 +1,37 @@
+/*
+ * Test R5900-specific three-operand MADDU.
+ */
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+
+uint64_t maddu(uint64_t a, uint32_t rs, uint32_t rt)
+{
+ uint32_t lo = a;
+ uint32_t hi = a >> 32;
+ uint32_t rd;
+ uint64_t r;
+
+ __asm__ __volatile__ (
+ " mtlo %5\n"
+ " mthi %6\n"
+ " maddu %0, %3, %4\n"
+ " mflo %1\n"
+ " mfhi %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt), "r" (lo), "r" (hi));
+ r = ((uint64_t)hi << 32) | (uint32_t)lo;
+
+ assert(a + (uint64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+int main()
+{
+ assert(maddu(13, 17, 19) == 336);
+
+ return 0;
+}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 36/38] tests/tcg/mips: Test R5900 three-operand MADDU1
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (34 preceding siblings ...)
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 35/38] tests/tcg/mips: Test R5900 three-operand MADDU Fredrik Noring
@ 2018-10-21 15:43 ` Fredrik Noring
2018-10-21 15:44 ` [Qemu-devel] [PATCH v8 37/38] target/mips: Define the R5900 CPU Fredrik Noring
` (2 subsequent siblings)
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:43 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Signed-off-by: Fredrik Noring <noring@nocrew.org>
---
tests/tcg/mips/mipsr5900/maddu.c | 37 ++++++++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c
index e4e552102d..30936fb2b4 100644
--- a/tests/tcg/mips/mipsr5900/maddu.c
+++ b/tests/tcg/mips/mipsr5900/maddu.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MADDU.
+ * Test R5900-specific three-operand MADDU and MADDU1.
*/
#include <stdio.h>
@@ -29,9 +29,42 @@ uint64_t maddu(uint64_t a, uint32_t rs, uint32_t rt)
return r;
}
+uint64_t maddu1(uint64_t a, uint32_t rs, uint32_t rt)
+{
+ uint32_t lo = a;
+ uint32_t hi = a >> 32;
+ uint32_t rd;
+ uint64_t r;
+
+ __asm__ __volatile__ (
+ " mtlo1 %5\n"
+ " mthi1 %6\n"
+ " maddu1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt), "r" (lo), "r" (hi));
+ r = ((uint64_t)hi << 32) | (uint32_t)lo;
+
+ assert(a + (uint64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static int64_t maddu_variants(int64_t a, int32_t rs, int32_t rt)
+{
+ int64_t rd = maddu(a, rs, rt);
+ int64_t rd1 = maddu1(a, rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
int main()
{
- assert(maddu(13, 17, 19) == 336);
+ assert(maddu_variants(13, 17, 19) == 336);
return 0;
}
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 37/38] target/mips: Define the R5900 CPU
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (35 preceding siblings ...)
2018-10-21 15:43 ` [Qemu-devel] [PATCH v8 36/38] tests/tcg/mips: Test R5900 three-operand MADDU1 Fredrik Noring
@ 2018-10-21 15:44 ` Fredrik Noring
2018-10-21 15:44 ` [Qemu-devel] [PATCH v8 38/38] linux-user/mips: Recognise the R5900 CPU model Fredrik Noring
2018-10-22 13:03 ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Aleksandar Markovic
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:44 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
The primary purpose of this change is to support programs compiled by
GCC for the R5900 target and thereby run R5900 Linux distributions, for
example Gentoo.
GCC in version 7.3, by itself, by inspection of the GCC source code
and inspection of the generated machine code, for the R5900 target,
only emits two instructions that are specific to the R5900: the three-
operand MULT and MULTU. GCC and libc also emit certain MIPS III
instructions that are not part of the R5900 ISA. They are normally
trapped and emulated by the Linux kernel, and therefore need to be
treated accordingly by QEMU.
A program compiled by GCC is taken to mean source code compiled by GCC
under the restrictions above. One can, with the apparent limitations,
with a bit of effort obtain a fully functioning operating system such
as R5900 Gentoo. Strictly speaking, programs need not be compiled by
GCC to make use of this change.
Instructions and other facilities of the R5900 not implemented by this
change are intended to signal provisional exceptions. One such example
is the FPU that is not compliant with IEEE 754-1985 in system mode. It
is therefore provisionally disabled. In user space the FPU is trapped
and emulated by IEEE 754-1985 compliant software in the kernel, and
this is handled accordingly by QEMU. Another example is the 93
multimedia instructions specific to the R5900 that generate provisional
reserved instruction exception signals.
One of the benefits of running a Linux distribution under QEMU is that
programs can be compiled with a native compiler, where the host and
target are the same, as opposed to a cross-compiler, where they are
not the same. This is especially important in cases where the target
hardware does not have the resources to run a native compiler.
Problems with cross-compilation are often related to host and target
differences in integer sizes, pointer sizes, endianness, machine code,
ABI, etc. Sometimes cross-compilation is not even supported by the
build script for a given package. One effective way to avoid those
problems is to replace the cross-compiler with a native compiler. This
change of compilation methods does not resolve the inherent problems
with cross-compilation.
The native compiler naturally replaces the cross-compiler, because one
typically uses one or the other, and preferably the native compiler
when the circumstances admit this. The native compiler is also a good
test case for the R5900 QEMU user mode. Additionally, Gentoo is well-
known for compiling and installing its packages from sources.
This change has been tested with Gentoo compiled for R5900, including
native compilation of several packages under QEMU.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate_init.inc.c | 59 ++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index acab097820..07a6c81e68 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -410,6 +410,65 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R5 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ /*
+ * The Toshiba TX System RISC TX79 Core Architecture manual
+ *
+ * https://wiki.qemu.org/File:C790.pdf
+ *
+ * describes the C790 processor that is a follow-up to the R5900.
+ * There are a few notable differences in that the R5900 FPU
+ *
+ * - is not IEEE 754-1985 compliant,
+ * - does not implement double format, and
+ * - its machine code is nonstandard.
+ */
+ .name = "R5900",
+ .CP0_PRid = 0x00002E00,
+ /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */
+ .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),
+ .CP0_Status_rw_bitmask = 0xF4C79C1F,
+#ifdef CONFIG_USER_ONLY
+ /*
+ * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC
+ * emulation. For user only, QEMU is the kernel, so we emulate the traps
+ * by simply emulating the instructions directly.
+ *
+ * Note: Config1 is only used internally, the R5900 has only Config0.
+ */
+ .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+ .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
+ .CP0_LLAddr_shift = 4,
+ .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0x0183FFFF,
+#else
+ /*
+ * The R5900 COP1 FPU implements single-precision floating-point
+ * operations but is not entirely IEEE 754-1985 compatible. In
+ * particular,
+ *
+ * - NaN (not a number) and +/- infinities are not supported;
+ * - exception mechanisms are not fully supported;
+ * - denormalized numbers are not supported;
+ * - rounding towards nearest and +/- infinities are not supported;
+ * - computed results usually differs in the least significant bit;
+ * - saturations can differ more than the least significant bit.
+ *
+ * Since only rounding towards zero is supported, the two least
+ * significant bits of FCR31 are hardwired to 01.
+ *
+ * FPU emulation is disabled here until it is implemented.
+ *
+ * Note: Config1 is only used internally, the R5900 has only Config0.
+ */
+ .CP0_Config1 = (47 << CP0C1_MMU),
+#endif /* !CONFIG_USER_ONLY */
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_R5900,
+ .mmu_type = MMU_TYPE_R4000,
+ },
{
/* A generic CPU supporting MIPS32 Release 6 ISA.
FIXME: Support IEEE 754-2008 FP.
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [PATCH v8 38/38] linux-user/mips: Recognise the R5900 CPU model
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (36 preceding siblings ...)
2018-10-21 15:44 ` [Qemu-devel] [PATCH v8 37/38] target/mips: Define the R5900 CPU Fredrik Noring
@ 2018-10-21 15:44 ` Fredrik Noring
2018-10-22 13:03 ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Aleksandar Markovic
38 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-21 15:44 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
This kind of ELF for the R5900 relies on an IEEE 754-1985 compliant FPU.
The R5900 FPU hardware is noncompliant and it is therefore emulated in
software by the Linux kernel. QEMU emulates a compliant FPU accordingly.
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
linux-user/mips/target_elf.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips/target_elf.h b/linux-user/mips/target_elf.h
index fa5d30bf99..a98c9bd6ad 100644
--- a/linux-user/mips/target_elf.h
+++ b/linux-user/mips/target_elf.h
@@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags)
if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {
return "mips32r6-generic";
}
+ if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {
+ return "R5900";
+ }
return "24Kf";
}
#endif
--
2.18.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-21 15:30 [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Fredrik Noring
` (37 preceding siblings ...)
2018-10-21 15:44 ` [Qemu-devel] [PATCH v8 38/38] linux-user/mips: Recognise the R5900 CPU model Fredrik Noring
@ 2018-10-22 13:03 ` Aleksandar Markovic
2018-10-22 17:23 ` Fredrik Noring
` (2 more replies)
38 siblings, 3 replies; 59+ messages in thread
From: Aleksandar Markovic @ 2018-10-22 13:03 UTC (permalink / raw)
To: Fredrik Noring, Maciej W. Rozycki, Philippe Mathieu-Daudé
Cc: Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
> From: Fredrik Noring <noring@nocrew.org>
> Subject: [PATCH v8 00/38] target/mips: Limited support for the R5900
>
Hi, Fredrik.
The series looks good.
I added ASE_MMI flag along with INSN_R5900, I think this fits better in the overall MIPS for QEMU design.
I made a couple of other minor changes.
I experienced some build errors (see the end of this mail), so I had to exclude some patches, but all others are fine, and had my "Reviewed-by". 32 patches will be included in the next MIPS queue.
Thanks for all efforts!
Aleksandar
/home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c: In function ‘gen_mul_txx9’:
/home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:4888:38: error: passing argument 3 of ‘tcg_gen_add2_i32’ from incompatible pointer type [-Werror=incompatible-pointer-types]
tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
^~~~~~
In file included from /home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:29:0:
/home/rtrk/Build/qemu-pull-request-oct-22/tcg/tcg-op.h:314:6: note: expected ‘TCGv_i32 {aka struct TCGv_i32_d *}’ but argument is of type ‘TCGv_i64 {aka struct TCGv_i64_d *}’
void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
^~~~~~~~~~~~~~~~
/home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:4888:51: error: passing argument 4 of ‘tcg_gen_add2_i32’ from incompatible pointer type [-Werror=incompatible-pointer-types]
tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
^~~~~~
In file included from /home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:29:0:
/home/rtrk/Build/qemu-pull-request-oct-22/tcg/tcg-op.h:314:6: note: expected ‘TCGv_i32 {aka struct TCGv_i32_d *}’ but argument is of type ‘TCGv_i64 {aka struct TCGv_i64_d *}’
void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
^~~~~~~~~~~~~~~~
/home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:4908:38: error: passing argument 3 of ‘tcg_gen_add2_i32’ from incompatible pointer type [-Werror=incompatible-pointer-types]
tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
^~~~~~
In file included from /home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:29:0:
/home/rtrk/Build/qemu-pull-request-oct-22/tcg/tcg-op.h:314:6: note: expected ‘TCGv_i32 {aka struct TCGv_i32_d *}’ but argument is of type ‘TCGv_i64 {aka struct TCGv_i64_d *}’
void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
^~~~~~~~~~~~~~~~
/home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:4908:51: error: passing argument 4 of ‘tcg_gen_add2_i32’ from incompatible pointer type [-Werror=incompatible-pointer-types]
tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
^~~~~~
In file included from /home/rtrk/Build/qemu-pull-request-oct-22/target/mips/translate.c:29:0:
/home/rtrk/Build/qemu-pull-request-oct-22/tcg/tcg-op.h:314:6: note: expected ‘TCGv_i32 {aka struct TCGv_i32_d *}’ but argument is of type ‘TCGv_i64 {aka struct TCGv_i64_d *}’
void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
^~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
/home/rtrk/Build/qemu-pull-request-oct-22/rules.mak:69: recipe for target 'target/mips/translate.o' failed
make[1]: *** [target/mips/translate.o] Error 1
Makefile:483: recipe for target 'subdir-mips64-softmmu' failed
make: *** [subdir-mips64-softmmu] Error 2
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 13:03 ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Aleksandar Markovic
@ 2018-10-22 17:23 ` Fredrik Noring
2018-10-22 18:10 ` Aleksandar Markovic
2018-10-22 18:31 ` Maciej W. Rozycki
2018-10-22 23:35 ` Philippe Mathieu-Daudé
2018-10-23 19:25 ` Fredrik Noring
2 siblings, 2 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-22 17:23 UTC (permalink / raw)
To: Aleksandar Markovic, Maciej W. Rozycki
Cc: Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Many thanks, Aleksandar,
> I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> the overall MIPS for QEMU design.
Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
even if it is a vendor-specific architecture extension that normally
isn't counted as an ASE? QEMU simply calls these "vendor specific ASEs".
Aleksandar -- please or ASE_MMI to insn_flags here:
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -466,7 +466,7 @@ const mips_def_t mips_defs[] =
#endif /* !CONFIG_USER_ONLY */
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_R5900,
+ .insn_flags = CPU_R5900 | ASE_MMI,
.mmu_type = MMU_TYPE_R4000,
},
{
Strictly speaking, MADD, MADDU, MULT, MULTU, MULT1, MULTU1, DIV1, DIVU1,
MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are not part of what the
Toshiba TX System RISC TX79 Core Architecture manual specifies as
"Multimedia Instructions", section B.3.2, on page B-3, even though
their opcodes are covered by TX79_CLASS_MMI and the decode_tx79_mmi
function. Can we adjust ASE_MMI for QEMU accordingly?
Also, doesn't it make sense to cover LQ and SQ with ASE_MMI as well, as
those two really are MMIs?
Finally, as far as I know, the MMIs cannot be disabled on R5900 hardware.
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26099,7 +26099,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_SPECIAL3:
- if (ctx->insn_flags & INSN_R5900) {
+ if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_tx79_sq(env, ctx); /* TX79_SQ */
} else {
decode_opc_special3(env, ctx);
@@ -26763,7 +26763,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_MSA: /* OPC_MDMX */
- if (ctx->insn_flags & INSN_R5900) {
+ if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_tx79_lq(env, ctx); /* TX79_LQ */
} else {
/* MDMX: Not implemented. */
> I experienced some build errors (see the end of this mail), so I had to
> exclude some patches, but all others are fine, and had my "Reviewed-by".
> 32 patches will be included in the next MIPS queue.
Ah, I didn't test the 64-bit build on the MADD[U][1] instructions. I will
look into them and post updated patches.
Regarding the R5900 FPU: It appears reasonable to introduce an ELF ABI
variant for the nonstandard R5900 FPU. A testsuite covering the anomalies
seems to be needed as well. Careful verification on hardware is needed.
I think it's probably best to keep the R5900 FPU disabled in QEMU until
these things have been sorted out.
I discovered that I lost the disassembly of MULT1 and MULTU1 in v8, as
shown in the attached patch below. This small change belongs to commit
bebf09ef3977 ("target/mips: Support R5900 three-operand MULT1 and MULTU1
instructions") in your tags/mips-queue-oct-2018-part-2. Please apply:
--- a/disas/mips.c
+++ b/disas/mips.c
@@ -2736,10 +2736,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
+{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE },
+{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO | IS_M, 0, EE },
{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
+{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE },
+{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO | IS_M, 0, EE },
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
Fredrik
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 17:23 ` Fredrik Noring
@ 2018-10-22 18:10 ` Aleksandar Markovic
2018-10-22 19:00 ` Fredrik Noring
2018-10-22 18:31 ` Maciej W. Rozycki
1 sibling, 1 reply; 59+ messages in thread
From: Aleksandar Markovic @ 2018-10-22 18:10 UTC (permalink / raw)
To: Fredrik Noring, Maciej W. Rozycki
Cc: Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
> From: Fredrik Noring <noring@nocrew.org>
>
> Subject: Re: [PATCH v8 00/38] target/mips: Limited support for the R5900
>
> Many thanks, Aleksandar,
>
> > I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> > the overall MIPS for QEMU design.
>
> Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
> even if it is a vendor-specific architecture extension that normally
> isn't counted as an ASE? QEMU simply calls these "vendor specific ASEs".
>
> Aleksandar -- please or ASE_MMI to insn_flags here:
>
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -466,7 +466,7 @@ const mips_def_t mips_defs[] =
> #endif /* !CONFIG_USER_ONLY */
> .SEGBITS = 32,
> .PABITS = 32,
> - .insn_flags = CPU_R5900,
> + .insn_flags = CPU_R5900 | ASE_MMI,
> .mmu_type = MMU_TYPE_R4000,
> },
> {
>
Hi, Fredrik.
I understood what you said about ASE_MMI and other changes you want to be included.
Pull request with 32 patches from this series is already sent, and I would like to avoid sending v2 of that request. Let's wait for some time until the pull request is hopefully accepted. There will be most likely another one at the beginning of the next week.
We are appoaching QEMU 3.1 soft freeze (Oct 30), and at this point we would like to stabilize the code, and to integrate only crucial patches. I suggest that you create a new series "target/mips: Amend R5900 support". It should be based on the code submitted in the pull request. Place the most crucial patches as the first ones, at the beginning of the series. Less important at the end. FPU changes are too risky at this stage od 3.1 development cycle, and I would leave them for QEMU 3.2+.
Regards and thanks again,
Aleksandar
> Strictly speaking, MADD, MADDU, MULT, MULTU, MULT1, MULTU1, DIV1, DIVU1,
> MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are not part of what the
> Toshiba TX System RISC TX79 Core Architecture manual specifies as
> "Multimedia Instructions", section B.3.2, on page B-3, even though
> their opcodes are covered by TX79_CLASS_MMI and the decode_tx79_mmi
> function. Can we adjust ASE_MMI for QEMU accordingly?
>
> Also, doesn't it make sense to cover LQ and SQ with ASE_MMI as well, as
> those two really are MMIs?
>
> Finally, as far as I know, the MMIs cannot be disabled on R5900 hardware.
>
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -26099,7 +26099,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> }
> break;
> case OPC_SPECIAL3:
> - if (ctx->insn_flags & INSN_R5900) {
> + if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
> decode_tx79_sq(env, ctx); /* TX79_SQ */
> } else {
> decode_opc_special3(env, ctx);
> @@ -26763,7 +26763,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
> }
> break;
> case OPC_MSA: /* OPC_MDMX */
> - if (ctx->insn_flags & INSN_R5900) {
> + if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
> decode_tx79_lq(env, ctx); /* TX79_LQ */
> } else {
> /* MDMX: Not implemented. */
>
> > I experienced some build errors (see the end of this mail), so I had to
> > exclude some patches, but all others are fine, and had my "Reviewed-by".
> > 32 patches will be included in the next MIPS queue.
>
> Ah, I didn't test the 64-bit build on the MADD[U][1] instructions. I will
> look into them and post updated patches.
>
> Regarding the R5900 FPU: It appears reasonable to introduce an ELF ABI
> variant for the nonstandard R5900 FPU. A testsuite covering the anomalies
> seems to be needed as well. Careful verification on hardware is needed.
> I think it's probably best to keep the R5900 FPU disabled in QEMU until
> these things have been sorted out.
>
> I discovered that I lost the disassembly of MULT1 and MULTU1 in v8, as
> shown in the attached patch below. This small change belongs to commit
> bebf09ef3977 ("target/mips: Support R5900 three-operand MULT1 and MULTU1
> instructions") in your tags/mips-queue-oct-2018-part-2. Please apply:
>
> --- a/disas/mips.c
> +++ b/disas/mips.c
> @@ -2736,10 +2736,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
> {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, > I1 },
> {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, > D33 },
> {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, > 0, G1 },
> +{"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE },
> +{"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO | IS_M, 0, > EE },
> {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, > SMT },
> {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, > I1 },
> {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, > D33 },
> {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, > 0, G1 },
> +{"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_s | RD_t | WR_HILO | IS_M, 0, EE },
> +{"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_d | RD_s | RD_t | WR_HILO | IS_M, 0, > EE },
> {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, > N5 },
> {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, > I1 }, /* sub 0 */
> {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, > I1 }, /* subu 0 */
>
> Fredrik
>
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 18:10 ` Aleksandar Markovic
@ 2018-10-22 19:00 ` Fredrik Noring
0 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-22 19:00 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Maciej W. Rozycki, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Aleksandar,
> Pull request with 32 patches from this series is already sent, and I would
> like to avoid sending v2 of that request. Let's wait for some time until
> the pull request is hopefully accepted. There will be most likely another
> one at the beginning of the next week.
>
> We are appoaching QEMU 3.1 soft freeze (Oct 30), and at this point we
> would like to stabilize the code, and to integrate only crucial patches.
> I suggest that you create a new series "target/mips: Amend R5900 support".
> It should be based on the code submitted in the pull request. Place the
> most crucial patches as the first ones, at the beginning of the series.
The R5900 testsuite in tests/tcg/mips/mipsr5900 fails unless ASE_MMI is
part of insn_flags for the R5900:
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -466,7 +466,7 @@ const mips_def_t mips_defs[] =
#endif /* !CONFIG_USER_ONLY */
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_R5900,
+ .insn_flags = CPU_R5900 | ASE_MMI,
.mmu_type = MMU_TYPE_R4000,
},
{
Perhaps that is the only (somewhat) crucial problem, depending on how the
testsuites are used, of course.
The other ASE_MMI changes and the disassembly of MULT1 and MULTU1 can wait,
as can R5900 support for MADD, MADDU, MADD1 and MADDU1, in my opinion.
> FPU changes are too risky at this stage od 3.1 development cycle, and I
> would leave them for QEMU 3.2+.
Agreed! As Maciej just noted, there are also toolchain issues that need
to be addressed for the R5900 FPU.
Fredrik
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 17:23 ` Fredrik Noring
2018-10-22 18:10 ` Aleksandar Markovic
@ 2018-10-22 18:31 ` Maciej W. Rozycki
2018-10-22 18:40 ` Maciej W. Rozycki
2018-10-23 19:10 ` Fredrik Noring
1 sibling, 2 replies; 59+ messages in thread
From: Maciej W. Rozycki @ 2018-10-22 18:31 UTC (permalink / raw)
To: Fredrik Noring
Cc: Aleksandar Markovic, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Maciej,
> > I added ASE_MMI flag along with INSN_R5900, I think this fits better in
> > the overall MIPS for QEMU design.
>
> Maciej -- can we add "MMI" under "ASEs implemented" in the kernel too,
> even if it is a vendor-specific architecture extension that normally
> isn't counted as an ASE? QEMU simply calls these "vendor specific ASEs".
I have no authority to approve such a change for the kernel, but it looks
reasonable to me and I will support you with it, with one reservation
however. As this is an ISA extension in the vendor-specific space, I
think it belongs to a vendor-specific namespace, so as to make it clear it
is not a generic architectural feature and also to avoid name clashes.
So it has to be called Toshiba MMI or suchlike, similarly to how I
requested that for the Longsoon MMI feature in a recent binutils review
(cf <https://sourceware.org/ml/binutils/2018-07/msg00201.html> and
binutils commit 8095d2f70e1a ("MIPS/GAS: Split Loongson MMI Instructions
from loongson2f/3a")), with all the consequences throughout.
> Aleksandar -- please or ASE_MMI to insn_flags here:
>
> --- a/target/mips/translate_init.inc.c
> +++ b/target/mips/translate_init.inc.c
> @@ -466,7 +466,7 @@ const mips_def_t mips_defs[] =
> #endif /* !CONFIG_USER_ONLY */
> .SEGBITS = 32,
> .PABITS = 32,
> - .insn_flags = CPU_R5900,
> + .insn_flags = CPU_R5900 | ASE_MMI,
> .mmu_type = MMU_TYPE_R4000,
> },
> {
So I think it better be called ASE_TOSHIBA_MMI here.
> Strictly speaking, MADD, MADDU, MULT, MULTU, MULT1, MULTU1, DIV1, DIVU1,
> MADD1, MADDU1, MFHI1, MFLO1, MTHI1 and MTLO1 are not part of what the
> Toshiba TX System RISC TX79 Core Architecture manual specifies as
> "Multimedia Instructions", section B.3.2, on page B-3, even though
> their opcodes are covered by TX79_CLASS_MMI and the decode_tx79_mmi
> function. Can we adjust ASE_MMI for QEMU accordingly?
NB all but pipeline 1 instructions of these are also implemented by other
members of the TXx9 family. They seem to be referred to as just "multiply
and multiply-add instructions" in the TX79 manual (cf Section B.3.1).
> Also, doesn't it make sense to cover LQ and SQ with ASE_MMI as well, as
> those two really are MMIs?
And they're certainly listed as such in the TX79 manual (cf Section
B.3.2).
> Regarding the R5900 FPU: It appears reasonable to introduce an ELF ABI
> variant for the nonstandard R5900 FPU.
Indeed and in particular given that the R5900 does not produce any FPU
exceptions it should be quite straightforward for the Linux kernel to
recognise this specific ABI annotation with ELF binaries and switch its FP
environment between R5900 native float and IEEE 754 emulated float
accordingly. We could then make QEMU run in the user emulation mode do
the same.
Of course all the pieces of the toolchain as well as the dynamic loader
in use would have to taught to prevent incompatible pieces of hard float
code from being used together.
Maciej
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 18:31 ` Maciej W. Rozycki
@ 2018-10-22 18:40 ` Maciej W. Rozycki
2018-10-22 23:16 ` Philippe Mathieu-Daudé
2018-10-23 19:10 ` Fredrik Noring
1 sibling, 1 reply; 59+ messages in thread
From: Maciej W. Rozycki @ 2018-10-22 18:40 UTC (permalink / raw)
To: Fredrik Noring
Cc: Aleksandar Markovic, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
On Mon, 22 Oct 2018, Maciej W. Rozycki wrote:
> Hi Maciej,
What an odd copy & paste thinko! I can't believe I addressed myself in
the opening of my e-mail. :)
Maciej
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 18:40 ` Maciej W. Rozycki
@ 2018-10-22 23:16 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 59+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-22 23:16 UTC (permalink / raw)
To: Maciej W. Rozycki, Fredrik Noring
Cc: Peter Maydell, Richard Henderson, Philippe Mathieu-Daudé,
qemu-devel, Aleksandar Markovic, Jürgen Urban,
Petar Jovanovic, Aurelien Jarno
On 22/10/18 20:40, Maciej W. Rozycki wrote:
> On Mon, 22 Oct 2018, Maciej W. Rozycki wrote:
>
>> Hi Maciej,
>
> What an odd copy & paste thinko! I can't believe I addressed myself in
> the opening of my e-mail. :)
Haha when I saw your mail I thought "weird, there is another Maciej
involved in this MIPS specific thread!?"
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 18:31 ` Maciej W. Rozycki
2018-10-22 18:40 ` Maciej W. Rozycki
@ 2018-10-23 19:10 ` Fredrik Noring
2018-10-25 17:38 ` Maciej W. Rozycki
1 sibling, 1 reply; 59+ messages in thread
From: Fredrik Noring @ 2018-10-23 19:10 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Aleksandar Markovic, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Maciej,
> I have no authority to approve such a change for the kernel, but it looks
> reasonable to me and I will support you with it, with one reservation
> however. As this is an ISA extension in the vendor-specific space, I
> think it belongs to a vendor-specific namespace, so as to make it clear it
> is not a generic architectural feature and also to avoid name clashes.
>
> So it has to be called Toshiba MMI or suchlike, similarly to how I
> requested that for the Longsoon MMI feature in a recent binutils review
> (cf <https://sourceware.org/ml/binutils/2018-07/msg00201.html> and
> binutils commit 8095d2f70e1a ("MIPS/GAS: Split Loongson MMI Instructions
> from loongson2f/3a")), with all the consequences throughout.
Vendor ASE namespaces makes sense to me. I can prepare a patch for it.
> NB all but pipeline 1 instructions of these are also implemented by other
> members of the TXx9 family. They seem to be referred to as just "multiply
> and multiply-add instructions" in the TX79 manual (cf Section B.3.1).
Would
ASE_TOSHIBA_MMI -- TX79 128-bit multimedia instructions
ASE_TOSHIBA_MAC -- TXx9 multiply and multiply-add instructions (MADD etc.)
ASE_TOSHIBA_MAC1 -- TX79 pipeline 1 variant of ASE_TOSHIBA_MAC
ASE_TOSHIBA_FMA -- R5900 FPU extensions (MADD.s etc.)
be acceptable for the currently known Toshiba extensions? (Please propose
better names.) One complication is that it seems only 8 bits are available
for all vendor ASEs, and Toshiba would then scoop up half of those.
Fredrik
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-23 19:10 ` Fredrik Noring
@ 2018-10-25 17:38 ` Maciej W. Rozycki
2018-10-26 13:42 ` Fredrik Noring
0 siblings, 1 reply; 59+ messages in thread
From: Maciej W. Rozycki @ 2018-10-25 17:38 UTC (permalink / raw)
To: Fredrik Noring
Cc: Aleksandar Markovic, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Fredrik,
> > NB all but pipeline 1 instructions of these are also implemented by other
> > members of the TXx9 family. They seem to be referred to as just "multiply
> > and multiply-add instructions" in the TX79 manual (cf Section B.3.1).
>
> Would
>
> ASE_TOSHIBA_MMI -- TX79 128-bit multimedia instructions
> ASE_TOSHIBA_MAC -- TXx9 multiply and multiply-add instructions (MADD etc.)
> ASE_TOSHIBA_MAC1 -- TX79 pipeline 1 variant of ASE_TOSHIBA_MAC
> ASE_TOSHIBA_FMA -- R5900 FPU extensions (MADD.s etc.)
>
> be acceptable for the currently known Toshiba extensions? (Please propose
> better names.) One complication is that it seems only 8 bits are available
> for all vendor ASEs, and Toshiba would then scoop up half of those.
I'm not sure if every single random vendor-specific instruction (or a
bunch of) deserves its own ASE designation, be it internal or externally
exposed. I think the MMI set being a substantial architectural feature
makes sense to be shown in /proc/cpuinfo (in Linux), but I don't think
there's much more about it. It's limited to 2 implementations only, so
internally I think it can well be handled with a macro or static inline
function (as appropriate) which boil down to (CPU_R5900 || CPU_TX79).
And if you run out of bits for ASEs regardless, then I suggest just to
expand the field in question. In QEMU you can rely on the presence of the
`uint64_t' data type, so with only 8 bits exhausted you're far from
getting into trouble.
Maciej
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-25 17:38 ` Maciej W. Rozycki
@ 2018-10-26 13:42 ` Fredrik Noring
0 siblings, 0 replies; 59+ messages in thread
From: Fredrik Noring @ 2018-10-26 13:42 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: Aleksandar Markovic, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Maciej,
> I'm not sure if every single random vendor-specific instruction (or a
> bunch of) deserves its own ASE designation, be it internal or externally
> exposed. I think the MMI set being a substantial architectural feature
> makes sense to be shown in /proc/cpuinfo (in Linux), but I don't think
> there's much more about it. It's limited to 2 implementations only, so
> internally I think it can well be handled with a macro or static inline
> function (as appropriate) which boil down to (CPU_R5900 || CPU_TX79).
Are there benefits in leaving out features? Their utility, such as
in choosing compiler options, may not correlate with their (lack of)
architectural weight.
A random pc, for instance, comes fully dressed flying the flags of
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm
pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts
rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni
pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16
xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer
aes xsave avx lahf_lm epb kaiser tpr_shadow vnmi flexpriority
ept vpid xsaveopt dtherm ida arat pln pts
in its /proc/cpuinfo. It also has a bugs field with
cpu_meltdown spectre_v1 spectre_v2
where the R5900 could have an entry for its short loop bug.
> And if you run out of bits for ASEs regardless, then I suggest just to
> expand the field in question. In QEMU you can rely on the presence of the
> `uint64_t' data type, so with only 8 bits exhausted you're far from
> getting into trouble.
DisasContext::insn_flags is already uint64_t, where bits 63..56 are
reserved for vendor-specific ASEs. Of course, one could organise them
differently, especially since they may be mutually exclusive, or one
could use a new ASE-specific field for them.
Fredrik
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 13:03 ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Aleksandar Markovic
2018-10-22 17:23 ` Fredrik Noring
@ 2018-10-22 23:35 ` Philippe Mathieu-Daudé
2018-10-23 19:25 ` Fredrik Noring
2 siblings, 0 replies; 59+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-22 23:35 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Fredrik Noring, Maciej W. Rozycki, Peter Maydell,
Richard Henderson, qemu-devel@nongnu.org Developers,
Jürgen Urban, Petar Jovanovic, Aurelien Jarno
On Mon, Oct 22, 2018 at 3:34 PM Aleksandar Markovic
<amarkovic@wavecomp.com> wrote:
> > From: Fredrik Noring <noring@nocrew.org>
> > Subject: [PATCH v8 00/38] target/mips: Limited support for the R5900
> >
> I experienced some build errors (see the end of this mail), so I had to exclude some patches, but all others are fine, and had my "Reviewed-by". 32 patches will be included in the next MIPS queue.
Thank you a lot Aleksandar for taking this series!
I appreciate a lot, being backed by a company, you also care about
hobbyist contributions.
This is not always an easy task for maintainers, and from the hobbyist
point of view, this means a lot to me.
Regards,
Phil.
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-22 13:03 ` [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900 Aleksandar Markovic
2018-10-22 17:23 ` Fredrik Noring
2018-10-22 23:35 ` Philippe Mathieu-Daudé
@ 2018-10-23 19:25 ` Fredrik Noring
2018-10-23 22:04 ` Maciej W. Rozycki
2 siblings, 1 reply; 59+ messages in thread
From: Fredrik Noring @ 2018-10-23 19:25 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Maciej W. Rozycki, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Maciej,
> target/mips/translate.c:4888:38: error: passing argument 3 of
> ‘tcg_gen_add2_i32’ from incompatible pointer type
> [-Werror=incompatible-pointer-types]
> tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
> ^~~~~~
Would you know if any MIPS ISA have LO and HI registers that are not
32-bit? In QEMU they can obviously be either 32-bit or 64-bit, which
causes the compilation error here.
Fredrik
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900
2018-10-23 19:25 ` Fredrik Noring
@ 2018-10-23 22:04 ` Maciej W. Rozycki
0 siblings, 0 replies; 59+ messages in thread
From: Maciej W. Rozycki @ 2018-10-23 22:04 UTC (permalink / raw)
To: Fredrik Noring
Cc: Aleksandar Markovic, Philippe Mathieu-Daudé,
Richard Henderson, Aurelien Jarno, Petar Jovanovic,
Peter Maydell, Jürgen Urban, qemu-devel
Hi Fredrik,
> > target/mips/translate.c:4888:38: error: passing argument 3 of
> > ‘tcg_gen_add2_i32’ from incompatible pointer type
> > [-Werror=incompatible-pointer-types]
> > tcg_gen_add2_i32(t2, t3, cpu_LO[acc], cpu_HI[acc], t2, t3);
> > ^~~~~~
>
> Would you know if any MIPS ISA have LO and HI registers that are not
> 32-bit? In QEMU they can obviously be either 32-bit or 64-bit, which
> causes the compilation error here.
Actually with all 64-bit MIPS ISAs HI/LO are a pair of 64-bit registers,
that is with MIPS III, MIPS IV, and then MIPS64 R1 to R5 ISAs (base R6 ISA
removed the MD accumulator, although it has been retained along with the 3
other ones in the DSP ASE).
The R5900 CPU is an oddball here, having no 64-bit multiply or divide
instructions, however documentation indicates these registers are still
64-bit as far as the base instruction set is concerned, i.e. it says you
can actually write the upper halves with any bit patterns explicitly with
the MTHI and MTLO instructions. And then they're really 128-bit as far as
the full instruction set of the R5900 is concerned, for all the pipeline 1
MD instructions operate on bits 95:64 and some MMI instructions operate on
the full 128-bit width of the accumulator.
Interestingly enough architecturally trying to use HI/LO values that are
not properly sign-extended 32-bit numbers does not make the operation of
32-bit multiply-accumulate instructions unpredictable, as they are
specified to simply ignore the upper 32 bits of a 64-bit value contained
there, and the the TX79 manual follows.
This is unlike with the GPR inputs to all MD instructions, which
architecturally have to be sign-extended. Contrariwise, the TX79 manual
says that GPR inputs to the unsigned variants of MD instructions have to
be zero-extended, and I do hope this is just an editorial mistake and
hardware does not follow (especially as the description of MULTU on page
A-87 disagress in this regard with one on page B-25, and all the relevant
pseudocode operation specifications consistently use NotWordValue as the
input validation condition, although that has been nowhere actually
formally defined). Otherwise lots of software would break and you'd have
to use a DSLL32/DSRL32 instruction pair every time before feeding the
result of other 32-bit calculations to those instructions.
BTW, notice that the pseudocode operation specification of the TX79 MD
instructions does clearly indicate the sign-extension of output HI/LO
contents, e.g. for MULTU we have:
prod <- (0 || GPR[rs]31..0) * (0 || GPR[rt]31..0)
LO63..0 <- (prod 31)32 || prod31..0
HI63..0 <- (prod 63)32 || prod63..32
GPR[rd]63..0 <- (prod 31)32 || prod31..0
HTH,
Maciej
^ permalink raw reply [flat|nested] 59+ messages in thread