* [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018
@ 2018-10-11 11:22 Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
` (22 more replies)
0 siblings, 23 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Aleksandar Markovic <amarkovic@wavecomp.com>
This series contains support for MIPS ABI flags in elf.h, hardware
page table walker, DSP R3 availability control, and emulation of
nanoMIPS EVA instructions. It also contains support for WatchHi,
MemoryMapID, SAARI, and SAAR registers, ITU updates, implementation
of DRAM, and I6500 core configuration.
MIPS ABI flags will be used in near future for linux user mode
support for certain MIPS-specific parts of prctl() system call.
All patches were developed a while ago, but were not submitted to
this list for various reasons.
v3->v4:
- added hardware page table walker (five patches)
- added separate patch on MemoryMapID
- added patch on updating mips32r6-generic
- added patch on updating MIPS64R2-generic
- added patch on improving DSP R2/R3-related naming
- added patch on SELEQZ.<D|S> SELNEZ.<D|S> fixing
v2->v3:
- added patch on extending WatchHi registers
- added patch on MemoryMapID, SAARI, and SAAR registers
- added patch on ITU updates wrt SAAR
- added patch on Data Scratch Pad RAM
- added patch on I6500 core configuration
- corrected the patch on nanoMIPS EVA opcodes
v1->v2:
- added three patches on MIPS-specifics in elf.h
Dimitrije Nikolic (2):
target/mips: Add opcodes for nanoMIPS EVA instructions
target/mips: Implement emulation of nanoMIPS EVA instructions
Matthew Fortune (1):
target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S>
Stefan Markovic (6):
elf: Fix PT_MIPS_XXX constants
elf: Add MIPS_ABI_FP_XXX constants
elf: Add Mips_elf_abiflags_v0 structure
target/mips: Add bit definitions for DSP R3 ASE
target/mips: Add availability control for DSP R3 ASE
target/mips: Improve DSP R2/R3-related naming
Yongbok Kim (13):
target/mips: Add CPO PWBase register
target/mips: Add CPO PWField register
target/mips: Add CPO PWSize register
target/mips: Add CPO PWCtl register
target/mips: Implement hardware page table walker
target/mips: Extend WatchHi registers
target/mips: Add CPO MemoryMapID register
target/mips: Add CP0 SAARI and SAAR registers
hw/mips: Update ITU to utilise SAARI/SAAR registers
hw/mips: Add Data Scratch Pad RAM
target/mips: Add DEC feature to mips32r6-generic CPU
target/mips: Add MSA ASE to MIPS64R2-generic CPU
target/mips: Add I6500 core configuration
default-configs/mips-softmmu-common.mak | 1 +
hw/mips/cps.c | 9 +
hw/mips/mips_malta.c | 31 ++
hw/misc/Makefile.objs | 1 +
hw/misc/mips_itu.c | 72 ++++-
include/elf.h | 30 +-
include/hw/mips/cps.h | 2 +
include/hw/misc/mips_itu.h | 7 +
target/mips/cpu.h | 40 ++-
target/mips/helper.c | 369 +++++++++++++++++++++-
target/mips/helper.h | 12 +
target/mips/internal.h | 15 +-
target/mips/machine.c | 12 +-
target/mips/mips-defs.h | 3 +-
target/mips/op_helper.c | 158 +++++++++-
target/mips/translate.c | 524 +++++++++++++++++++++++++-------
target/mips/translate_init.inc.c | 60 +++-
17 files changed, 1218 insertions(+), 128 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:19 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
` (21 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Fix existing and add missing PT_MIPS_XXX constants in elf.h.
This is copied from kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 312f68a..decf210 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -28,8 +28,11 @@ typedef int64_t Elf64_Sxword;
#define PT_PHDR 6
#define PT_LOPROC 0x70000000
#define PT_HIPROC 0x7fffffff
-#define PT_MIPS_REGINFO 0x70000000
-#define PT_MIPS_OPTIONS 0x70000001
+
+#define PT_MIPS_REGINFO 0x70000000
+#define PT_MIPS_RTPROC 0x70000001
+#define PT_MIPS_OPTIONS 0x70000002
+#define PT_MIPS_ABIFLAGS 0x70000003
/* Flags in the e_flags field of the header */
/* MIPS architecture level. */
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:19 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
` (20 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add MIPS_ABI_FP_XXX constants to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index decf210..eb5958d 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -87,6 +87,14 @@ typedef int64_t Elf64_Sxword;
#define EF_MIPS_MACH_LS3A 0x00a20000 /* ST Microelectronics Loongson 3A */
#define EF_MIPS_MACH 0x00ff0000 /* EF_MIPS_MACH_xxx selection mask */
+#define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */
+#define MIPS_ABI_FP_DOUBLE 0x1 /* -mdouble-float */
+#define MIPS_ABI_FP_SINGLE 0x2 /* -msingle-float */
+#define MIPS_ABI_FP_SOFT 0x3 /* -msoft-float */
+#define MIPS_ABI_FP_OLD_64 0x4 /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_XX 0x5 /* -mfpxx */
+#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
+#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
/* These constants define the different elf file types */
#define ET_NONE 0
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:20 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register Aleksandar Markovic
` (19 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add Mips_elf_abiflags_v0 structure to elf.h. The source of information
is kernel header arch/mips/include/asm/elf.h.
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
include/elf.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index eb5958d..75c60cc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -96,6 +96,21 @@ typedef int64_t Elf64_Sxword;
#define MIPS_ABI_FP_64 0x6 /* -mips32r2 -mfp64 */
#define MIPS_ABI_FP_64A 0x7 /* -mips32r2 -mfp64 -mno-odd-spreg */
+typedef struct mips_elf_abiflags_v0 {
+ uint16_t version; /* Version of flags structure */
+ uint8_t isa_level; /* The level of the ISA: 1-5, 32, 64 */
+ uint8_t isa_rev; /* The revision of ISA: 0 for MIPS V and below,*/
+ /* 1-n otherwise */
+ uint8_t gpr_size; /* The size of general purpose registers */
+ uint8_t cpr1_size; /* The size of co-processor 1 registers */
+ uint8_t cpr2_size; /* The size of co-processor 2 registers */
+ uint8_t fp_abi; /* The floating-point ABI */
+ uint32_t isa_ext; /* Mask of processor-specific extensions */
+ uint32_t ases; /* Mask of ASEs used */
+ uint32_t flags1; /* Mask of general flags */
+ uint32_t flags2;
+} Mips_elf_abiflags_v0;
+
/* These constants define the different elf file types */
#define ET_NONE 0
#define ET_REL 1
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (2 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:27 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register Aleksandar Markovic
` (18 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add PWBase register (CP0 Register 5, Select 5).
The PWBase register contains the Page Table Base virtual address.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 1 +
target/mips/translate.c | 31 +++++++++++++++++++++++++++++++
3 files changed, 33 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d1..c8999a8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -289,6 +289,7 @@ struct CPUMIPSState {
#define CP0SC2_XR 56
#define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
#define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
+ target_ulong CP0_PWBase;
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 5ba78ac..86702c6 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -256,6 +256,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
+ VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..7af9a21 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1929,6 +1929,17 @@ static inline void check_xnp(DisasContext *ctx)
/*
* This code generates a "reserved instruction" exception if the
+ * Config3 PW bit is NOT set.
+ */
+static inline void check_pw(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
+/*
+ * This code generates a "reserved instruction" exception if the
* Config3 MT bit is NOT set.
*/
static inline void check_mt(DisasContext *ctx)
@@ -5537,6 +5548,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ext32s_tl(arg, arg);
rn = "SegCtl2";
break;
+ case 5:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
+ rn = "PWBase";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6238,6 +6254,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_segctl2(cpu_env, arg);
rn = "SegCtl2";
break;
+ case 5:
+ check_pw(ctx);
+ gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
+ rn = "PWBase";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6948,6 +6969,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
rn = "SegCtl2";
break;
+ case 5:
+ check_pw(ctx);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
+ rn = "PWBase";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7631,6 +7657,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_segctl2(cpu_env, arg);
rn = "SegCtl2";
break;
+ case 5:
+ check_pw(ctx);
+ tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
+ rn = "PWBase";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (3 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:28 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register Aleksandar Markovic
` (17 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add PWField register (CP0 Register 5, Select 6).
The PWField register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
GDI (29..24) - Global Directory index
UDI (23..18) - Upper Directory index
MDI (17..12) - Middle Directory index
PTI (11..6 ) - Page Table index
PTEI ( 5..0 ) - Page Table Entry shift
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 6 ++++++
target/mips/helper.h | 1 +
target/mips/machine.c | 1 +
target/mips/op_helper.c | 34 ++++++++++++++++++++++++++++++++++
target/mips/translate.c | 20 ++++++++++++++++++++
5 files changed, 62 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index c8999a8..01cd65c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -290,6 +290,12 @@ struct CPUMIPSState {
#define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
#define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
target_ulong CP0_PWBase;
+ target_ulong CP0_PWField;
+#define CP0PF_GDI 24 /* 29..24 */
+#define CP0PF_UDI 18 /* 23..18 */
+#define CP0PF_MDI 12 /* 17..12 */
+#define CP0PF_PTI 6 /* 11..6 */
+#define CP0PF_PTEI 0 /* 5..0 */
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index b2a780a..6366f9b 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -120,6 +120,7 @@ DEF_HELPER_2(mtc0_pagegrain, void, env, tl)
DEF_HELPER_2(mtc0_segctl0, void, env, tl)
DEF_HELPER_2(mtc0_segctl1, void, env, tl)
DEF_HELPER_2(mtc0_segctl2, void, env, tl)
+DEF_HELPER_2(mtc0_pwfield, void, env, tl)
DEF_HELPER_2(mtc0_wired, void, env, tl)
DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
DEF_HELPER_2(mtc0_srsconf1, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 86702c6..aa6ef56 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -257,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
+ VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index c148b31..bc506de 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1445,6 +1445,40 @@ void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
tlb_flush(cs);
}
+void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
+{
+#ifdef TARGET_MIPS64
+ env->CP0_PWField = arg1 & 0x3F3FFFFFFFULL;
+#else
+ uint32_t mask = 0x3FFFFFFF;
+ uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3F;
+ uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3F;
+
+ if ((env->insn_flags & ISA_MIPS32R6)) {
+ if (((arg1 >> CP0PF_GDI) & 0x3F) < 12) {
+ mask &= ~(0x3F << CP0PF_GDI);
+ }
+ if (((arg1 >> CP0PF_UDI) & 0x3F) < 12) {
+ mask &= ~(0x3F << CP0PF_UDI);
+ }
+ if (((arg1 >> CP0PF_MDI) & 0x3F) < 12) {
+ mask &= ~(0x3F << CP0PF_MDI);
+ }
+ if (((arg1 >> CP0PF_PTI) & 0x3F) < 12) {
+ mask &= ~(0x3F << CP0PF_PTI);
+ }
+ }
+ env->CP0_PWField = arg1 & mask;
+
+ if ((new_ptei >= 32) ||
+ ((env->insn_flags & ISA_MIPS32R6) &&
+ (new_ptei == 0 || new_ptei == 1))) {
+ env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
+ (old_ptei << CP0PF_PTEI);
+ }
+#endif
+}
+
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
{
if (env->insn_flags & ISA_MIPS32R6) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7af9a21..882a765 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5553,6 +5553,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
rn = "PWBase";
break;
+ case 6:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
+ rn = "PWField";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6259,6 +6264,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
rn = "PWBase";
break;
+ case 6:
+ check_pw(ctx);
+ gen_helper_mtc0_pwfield(cpu_env, arg);
+ rn = "PWField";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6974,6 +6984,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
rn = "PWBase";
break;
+ case 6:
+ check_pw(ctx);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
+ rn = "PWField";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7662,6 +7677,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
rn = "PWBase";
break;
+ case 6:
+ check_pw(ctx);
+ gen_helper_mtc0_pwfield(cpu_env, arg);
+ rn = "PWField";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (4 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:29 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register Aleksandar Markovic
` (16 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add PWSize register (CP0 Register 5, Select 7).
The PWSize register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
GDW (29..24) Global Directory index width
UDW (23..18) Upper Directory index width
MDW (17..12) Middle Directory index width
PTW (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 7 +++++++
target/mips/helper.h | 1 +
target/mips/machine.c | 1 +
target/mips/op_helper.c | 9 +++++++++
target/mips/translate.c | 20 ++++++++++++++++++++
5 files changed, 38 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 01cd65c..a6abd1f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -296,6 +296,13 @@ struct CPUMIPSState {
#define CP0PF_MDI 12 /* 17..12 */
#define CP0PF_PTI 6 /* 11..6 */
#define CP0PF_PTEI 0 /* 5..0 */
+ target_ulong CP0_PWSize;
+#define CP0PS_PS 30
+#define CP0PS_GDW 24 /* 29..24 */
+#define CP0PS_UDW 18 /* 23..18 */
+#define CP0PS_MDW 12 /* 17..12 */
+#define CP0PS_PTW 6 /* 11..6 */
+#define CP0PS_PTEW 0 /* 5..0 */
int32_t CP0_Wired;
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 6366f9b..169890a 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl)
DEF_HELPER_2(mtc0_segctl1, void, env, tl)
DEF_HELPER_2(mtc0_segctl2, void, env, tl)
DEF_HELPER_2(mtc0_pwfield, void, env, tl)
+DEF_HELPER_2(mtc0_pwsize, void, env, tl)
DEF_HELPER_2(mtc0_wired, void, env, tl)
DEF_HELPER_2(mtc0_srsconf0, void, env, tl)
DEF_HELPER_2(mtc0_srsconf1, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index aa6ef56..31e3d95 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -258,6 +258,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
+ VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index bc506de..0986baf 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1479,6 +1479,15 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
#endif
}
+void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
+{
+#ifdef TARGET_MIPS64
+ env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
+#else
+ env->CP0_PWSize = arg1 & 0x3FFFFFFF;
+#endif
+}
+
void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
{
if (env->insn_flags & ISA_MIPS32R6) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 882a765..ef38be9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5558,6 +5558,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
rn = "PWField";
break;
+ case 7:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
+ rn = "PWSize";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6269,6 +6274,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_pwfield(cpu_env, arg);
rn = "PWField";
break;
+ case 7:
+ check_pw(ctx);
+ gen_helper_mtc0_pwsize(cpu_env, arg);
+ rn = "PWSize";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6989,6 +6999,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
rn = "PWField";
break;
+ case 7:
+ check_pw(ctx);
+ tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
+ rn = "PWSize";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7682,6 +7697,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_pwfield(cpu_env, arg);
rn = "PWField";
break;
+ case 7:
+ check_pw(ctx);
+ gen_helper_mtc0_pwsize(cpu_env, arg);
+ rn = "PWSize";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (5 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:29 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker Aleksandar Markovic
` (15 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add PWCtl register (CP0 Register 5, Select 6).
The PWCtl register configures hardware page table walking for TLB
refills.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:
PWEn (31) - Hardware Page Table walker enable
DPH (7) - Dual Page format of Huge Page support
HugePg (6) - Huge Page PTE supported in Directory levels
PSn (5..0) - Bit position of PTEvld in Huge Page PTE
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 5 +++++
target/mips/helper.h | 1 +
target/mips/machine.c | 1 +
target/mips/op_helper.c | 10 ++++++++++
target/mips/translate.c | 20 ++++++++++++++++++++
5 files changed, 37 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a6abd1f..5e45e97 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -304,6 +304,11 @@ struct CPUMIPSState {
#define CP0PS_PTW 6 /* 11..6 */
#define CP0PS_PTEW 0 /* 5..0 */
int32_t CP0_Wired;
+ int32_t CP0_PWCtl;
+#define CP0PC_PWEN 31
+#define CP0PC_DPH 7
+#define CP0PC_HUGEPG 6
+#define CP0PC_PSN 0 /* 5..0 */
int32_t CP0_SRSConf0_rw_bitmask;
int32_t CP0_SRSConf0;
#define CP0SRSC0_M 31
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 169890a..c23e4e5 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -129,6 +129,7 @@ DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
+DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 31e3d95..67a85a0 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -260,6 +260,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
+ VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0986baf..e649bd0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1524,6 +1524,16 @@ void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
}
+void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
+{
+#ifdef TARGET_MIPS64
+ /* PWEn = 0. Hardware page table walking is not implemented. */
+ env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
+#else
+ env->CP0_PWCtl = (arg1 & 0x800000FF);
+#endif
+}
+
void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
{
uint32_t mask = 0x0000000F;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ef38be9..f669d48 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5598,6 +5598,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6314,6 +6319,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_srsconf4(cpu_env, arg);
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_helper_mtc0_pwctl(cpu_env, arg);
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7039,6 +7049,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7737,6 +7752,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_srsconf4(cpu_env, arg);
rn = "SRSConf4";
break;
+ case 6:
+ check_pw(ctx);
+ gen_helper_mtc0_pwctl(cpu_env, arg);
+ rn = "PWCtl";
+ break;
default:
goto cp0_unimplemented;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (6 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:31 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers Aleksandar Markovic
` (14 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Implement hardware page table walker.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.c | 369 +++++++++++++++++++++++++++++++++++++++++++++++-
target/mips/internal.h | 1 +
target/mips/op_helper.c | 7 +-
3 files changed, 374 insertions(+), 3 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index f0c268b..2b166cc 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -537,6 +537,346 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
#endif
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(TARGET_MIPS64)
+
+/* Perform hardware page table walk
+*
+* Memory accesses are performed using the KERNEL privilege level.
+* Synchronous exceptions detected on memory accesses cause a silent exit
+* from page table walking, resulting in a TLB or XTLB Refill exception.
+*
+* Implementations are not required to support page table walk memory
+* accesses from mapped memory regions. When an unsupported access is
+* attempted, a silent exit is taken, resulting in a TLB or XTLB Refill
+* exception.
+*
+* Note that if an exception is caused by AddressTranslation or LoadMemory
+* functions, the exception is not taken, a silent exit is taken,
+* resulting in a TLB or XTLB Refill exception.
+*/
+
+static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size,
+ uint64_t *pte)
+{
+ if ((vaddr & ((entry_size >> 3) - 1)) != 0) {
+ return false;
+ }
+ if (entry_size == 64) {
+ *pte = cpu_ldq_code(env, vaddr);
+ } else {
+ *pte = cpu_ldl_code(env, vaddr);
+ }
+ return true;
+}
+
+static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry,
+ int entry_size, int ptei)
+{
+ uint64_t result = entry;
+ uint64_t rixi;
+ if (ptei > entry_size) {
+ ptei -= 32;
+ }
+ result >>= (ptei - 2);
+ rixi = result & 3;
+ result >>= 2;
+ result |= rixi << CP0EnLo_XI;
+ return result;
+}
+
+static int walk_directory(CPUMIPSState *env, uint64_t *vaddr,
+ int directory_index, bool *huge_page, bool *hgpg_directory_hit,
+ uint64_t *pw_entrylo0, uint64_t *pw_entrylo1)
+{
+ int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1;
+ int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F;
+ int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
+ int ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3F;
+ int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
+ int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
+ int directory_shift = (ptew > 1) ? -1 :
+ (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
+ int leaf_shift = (ptew > 1) ? -1 :
+ (ptew == 1) ? native_shift + 1 : native_shift;
+ uint32_t direntry_size = 1 << (directory_shift + 3);
+ uint32_t leafentry_size = 1 << (leaf_shift + 3);
+
+ uint64_t entry;
+ uint64_t paddr;
+ int prot;
+ uint64_t lsb = 0;
+ uint64_t w = 0;
+
+ if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD,
+ ACCESS_INT, cpu_mmu_index(env, false))
+ != TLBRET_MATCH) {
+ /* wrong base address */
+ return 0;
+ }
+ if (!get_pte(env, *vaddr, direntry_size, &entry)) {
+ return 0;
+ }
+
+ if ((entry & (1 << psn)) && hugepg) {
+ *huge_page = true;
+ *hgpg_directory_hit = true;
+ entry = get_tlb_entry_layout(env, entry, leafentry_size,
+ ptei);
+ w = directory_index - 1;
+ if (directory_index & 0x1) {
+ /* generate adjacent page from same PTE for odd TLB page */
+ lsb = (1 << w) >> 6;
+ *pw_entrylo0 = entry & ~lsb; /* even page */
+ *pw_entrylo1 = entry | lsb; /* odd page */
+ } else if (dph) {
+ int oddpagebit = 1 << leaf_shift;
+ uint64_t vaddr2 = *vaddr ^ oddpagebit;
+ if (*vaddr & oddpagebit) {
+ *pw_entrylo1 = entry;
+ } else {
+ *pw_entrylo0 = entry;
+ }
+ if (get_physical_address(env, &paddr, &prot, vaddr2,
+ MMU_DATA_LOAD, ACCESS_INT,
+ cpu_mmu_index(env, false))
+ != TLBRET_MATCH) {
+ return 0;
+ }
+ if (!get_pte(env, vaddr2, leafentry_size, &entry)) {
+ return 0;
+ }
+ entry = get_tlb_entry_layout(env, entry,
+ leafentry_size, ptei);
+ if (*vaddr & oddpagebit) {
+ *pw_entrylo0 = entry;
+ } else {
+ *pw_entrylo1 = entry;
+ }
+ } else {
+ return 0;
+ }
+ return 1;
+ } else {
+ *vaddr = entry;
+ return 2;
+ }
+}
+
+static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw,
+ int mmu_idx)
+{
+ int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3f;
+ int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3f;
+ int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3f;
+ int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F;
+
+ /* Initial values */
+ bool huge_page = false;
+ bool hgpg_bdhit = false;
+ bool hgpg_gdhit = false;
+ bool hgpg_udhit = false;
+ bool hgpg_mdhit = false;
+
+ int32_t pw_pagemask = 0;
+ target_ulong pw_entryhi = 0;
+ uint64_t pw_entrylo0 = 0;
+ uint64_t pw_entrylo1 = 0;
+
+ /* Native pointer size */
+ /*For the 32-bit architectures, this bit is fixed to 0.*/
+ int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3;
+
+ /* Indices from PWField */
+ int gdi = (env->CP0_PWField >> CP0PF_GDI) & 0x3F;
+ int udi = (env->CP0_PWField >> CP0PF_UDI) & 0x3F;
+ int mdi = (env->CP0_PWField >> CP0PF_MDI) & 0x3F;
+ int pti = (env->CP0_PWField >> CP0PF_PTI) & 0x3F;
+ int ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3F;
+ int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F;
+
+ /* Indices computed from faulting address */
+ int gindex = (address >> gdi) & ((1 << gdw) - 1);
+ int uindex = (address >> udi) & ((1 << udw) - 1);
+ int mindex = (address >> mdi) & ((1 << mdw) - 1);
+ int ptindex = (address >> pti) & ((1 << ptw) - 1);
+
+ /* Other HTW configs */
+ int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1;
+
+ /* HTW Shift values (depend on entry size) */
+ int directory_shift = (ptew > 1) ? -1 :
+ (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift;
+ int leaf_shift = (ptew > 1) ? -1 :
+ (ptew == 1) ? native_shift + 1 : native_shift;
+
+ /* Offsets into tables */
+ int goffset = gindex << directory_shift;
+ int uoffset = uindex << directory_shift;
+ int moffset = mindex << directory_shift;
+ int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1);
+ int ptoffset1 = ptoffset0 | (1 << (leaf_shift));
+
+ uint32_t leafentry_size = 1 << (leaf_shift + 3);
+
+ /* Starting address - Page Table Base */
+ uint64_t vaddr = env->CP0_PWBase;
+
+ uint64_t dir_entry;
+ uint64_t paddr;
+ int prot;
+ int m;
+
+ if (!(env->CP0_Config3 & (1 << CP0C3_PW))) {
+ /* walker is unimplemented */
+ return false;
+ }
+ if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) {
+ /* walker is disabled */
+ return false;
+ }
+ if (!(gdw > 0 || udw > 0 || mdw > 0)) {
+ /* no structure to walk */
+ return false;
+ }
+ if ((directory_shift == -1) || (leaf_shift == -1)) {
+ return false;
+ }
+
+ /* Global Directory */
+ if (gdw > 0) {
+ vaddr |= goffset;
+ switch (walk_directory(env, &vaddr,
+ gdi, &huge_page, &hgpg_gdhit,
+ &pw_entrylo0, &pw_entrylo1)) {
+ case 0:
+ return false;
+ case 1:
+ goto refill;
+ case 2:
+ default:
+ break;
+ }
+ }
+
+ /* Upper directory */
+ if (udw > 0) {
+ vaddr |= uoffset;
+ switch (walk_directory(env, &vaddr,
+ udi, &huge_page, &hgpg_udhit,
+ &pw_entrylo0, &pw_entrylo1)) {
+ case 0:
+ return false;
+ case 1:
+ goto refill;
+ case 2:
+ default:
+ break;
+ }
+ }
+
+ /* Middle directory */
+ if (mdw > 0) {
+ vaddr |= moffset;
+ switch (walk_directory(env, &vaddr,
+ mdi, &huge_page, &hgpg_mdhit,
+ &pw_entrylo0, &pw_entrylo1)) {
+ case 0:
+ return false;
+ case 1:
+ goto refill;
+ case 2:
+ default:
+ break;
+ }
+ }
+
+ /* Leaf Level Page Table - First half of PTE pair */
+ vaddr |= ptoffset0;
+ if (get_physical_address(env, &paddr, &prot, vaddr,
+ MMU_DATA_LOAD, ACCESS_INT,
+ cpu_mmu_index(env, false))
+ != TLBRET_MATCH) {
+ return false;
+ }
+ if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
+ return false;
+ }
+ dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, ptei);
+ pw_entrylo0 = dir_entry;
+
+ /* Leaf Level Page Table - Second half of PTE pair */
+ vaddr |= ptoffset1;
+ if (get_physical_address(env, &paddr, &prot, vaddr,
+ MMU_DATA_LOAD, ACCESS_INT,
+ cpu_mmu_index(env, false)) != TLBRET_MATCH) {
+ return false;
+ }
+ if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) {
+ return false;
+ }
+ dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, ptei);
+ pw_entrylo1 = dir_entry;
+
+refill:
+ m = (1 << pti) - 1;
+
+ if (huge_page) {
+ switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 |
+ hgpg_mdhit) {
+ case 4:
+ m = (1 << gdi) - 1;
+ if (gdi & 1) {
+ m >>= 1;
+ }
+ break;
+ case 2:
+ m = (1 << udi) - 1;
+ if (udi & 1) {
+ m >>= 1;
+ }
+ break;
+ case 1:
+ m = (1 << mdi) - 1;
+ if (mdi & 1) {
+ m >>= 1;
+ }
+ break;
+ }
+ }
+
+ pw_pagemask = m >> 12;
+ update_pagemask(env, pw_pagemask << 13, &pw_pagemask);
+ pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF);
+
+ {
+ target_ulong tmp_entryhi = env->CP0_EntryHi;
+ int32_t tmp_pagemask = env->CP0_PageMask;
+ uint64_t tmp_entrylo0 = env->CP0_EntryLo0;
+ uint64_t tmp_entrylo1 = env->CP0_EntryLo1;
+
+ env->CP0_EntryHi = pw_entryhi;
+ env->CP0_PageMask = pw_pagemask;
+ env->CP0_EntryLo0 = pw_entrylo0;
+ env->CP0_EntryLo1 = pw_entrylo1;
+
+ /*
+ * The hardware page walker inserts a page into the TLB in a manner
+ * identical to a TLBWR instruction as executed by the software refill
+ * handler.
+ */
+ r4k_helper_tlbwr(env);
+
+ env->CP0_EntryHi = tmp_entryhi;
+ env->CP0_PageMask = tmp_pagemask;
+ env->CP0_EntryLo0 = tmp_entrylo0;
+ env->CP0_EntryLo1 = tmp_entrylo1;
+ }
+ return true;
+}
+#endif
+#endif
+
int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
int mmu_idx)
{
@@ -558,8 +898,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
/* data access */
#if !defined(CONFIG_USER_ONLY)
- /* XXX: put correct access by using cpu_restore_state()
- correctly */
+ /* XXX: put correct access by using cpu_restore_state() correctly */
access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type, mmu_idx);
@@ -583,6 +922,32 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
} else if (ret < 0)
#endif
{
+#if !defined(CONFIG_USER_ONLY)
+#if !defined(TARGET_MIPS64)
+ if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) {
+ /*
+ * Memory reads during hardware page table walking are performed
+ * as if they were kernel-mode load instructions.
+ */
+ int mode = (env->hflags & MIPS_HFLAG_KSU);
+ bool ret_walker;
+ env->hflags &= ~MIPS_HFLAG_KSU;
+ ret_walker = page_table_walk_refill(env, address, rw, mmu_idx);
+ env->hflags |= mode;
+ if (ret_walker) {
+ ret = get_physical_address(env, &physical, &prot,
+ address, rw, access_type, mmu_idx);
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+ mmu_idx, TARGET_PAGE_SIZE);
+ ret = 0;
+ return ret;
+ }
+ }
+ }
+#endif
+#endif
raise_mmu_exception(env, address, rw, ret);
ret = 1;
}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f..2898bfc 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -211,6 +211,7 @@ uint64_t float_class_d(uint64_t arg, float_status *fst);
extern unsigned int ieee_rm[];
int ieee_ex_to_mips(int xcpt);
+void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
static inline void restore_rounding_mode(CPUMIPSState *env)
{
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index e649bd0..af130f6 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1400,7 +1400,7 @@ void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
}
-void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
+void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
{
uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
@@ -1411,6 +1411,11 @@ void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
}
}
+void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
+{
+ update_pagemask(env, arg1, &env->CP0_PageMask);
+}
+
void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
{
/* SmartMIPS not implemented */
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (7 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register Aleksandar Markovic
` (13 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
WatchHi is extended by the field MemoryMapID with the GINVT
instruction. The field is accessible by MTHC0/MFHC0 in 32-bit
architectures and DMTC0/DMFC0 in 64-bit architectures.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 2 +-
target/mips/helper.h | 3 +++
target/mips/machine.c | 2 +-
target/mips/op_helper.c | 23 +++++++++++++++++++++--
target/mips/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
5 files changed, 65 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5e45e97..10c3813 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -531,7 +531,7 @@ struct CPUMIPSState {
uint64_t CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
target_ulong CP0_WatchLo[8];
- int32_t CP0_WatchHi[8];
+ uint64_t CP0_WatchHi[8];
#define CP0WH_ASID 16
target_ulong CP0_XContext;
int32_t CP0_Framemask;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index c23e4e5..0ec500a 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -76,6 +76,7 @@ DEF_HELPER_1(mfc0_maar, tl, env)
DEF_HELPER_1(mfhc0_maar, tl, env)
DEF_HELPER_2(mfc0_watchlo, tl, env, i32)
DEF_HELPER_2(mfc0_watchhi, tl, env, i32)
+DEF_HELPER_2(mfhc0_watchhi, tl, env, i32)
DEF_HELPER_1(mfc0_debug, tl, env)
DEF_HELPER_1(mftc0_debug, tl, env)
#ifdef TARGET_MIPS64
@@ -87,6 +88,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env)
DEF_HELPER_1(dmfc0_lladdr, tl, env)
DEF_HELPER_1(dmfc0_maar, tl, env)
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
+DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
#endif /* TARGET_MIPS64 */
DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -153,6 +155,7 @@ DEF_HELPER_2(mthc0_maar, void, env, tl)
DEF_HELPER_2(mtc0_maari, void, env, tl)
DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32)
DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32)
+DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32)
DEF_HELPER_2(mtc0_xcontext, void, env, tl)
DEF_HELPER_2(mtc0_framemask, void, env, tl)
DEF_HELPER_2(mtc0_debug, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 67a85a0..0ef9b71 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -292,7 +292,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
VMSTATE_UINT64(env.lladdr, MIPSCPU),
VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
- VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
+ VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index af130f6..3d86c60 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -991,7 +991,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
{
- return env->CP0_WatchHi[sel];
+ return (int32_t) env->CP0_WatchHi[sel];
+}
+
+target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
+{
+ return env->CP0_WatchHi[sel] >> 32;
}
target_ulong helper_mfc0_debug(CPUMIPSState *env)
@@ -1059,6 +1064,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
{
return env->CP0_WatchLo[sel];
}
+
+target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
+{
+ return env->CP0_WatchHi[sel];
+}
#endif /* TARGET_MIPS64 */
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
@@ -1818,11 +1828,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
- int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
+ mask |= 0xFFFFFFFF00000000ULL; /* MMID */
+ }
env->CP0_WatchHi[sel] = arg1 & mask;
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}
+void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
+{
+ env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
+ (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
+}
+
void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
{
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f669d48..8bff0e1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5223,6 +5223,25 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case 19:
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ /* upper 32 bits are only available when Config5MI != 0 */
+ /* CP0_CHECK(ctx->mi); */
+ gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_WatchHi[sel]), 0);
+ rn = "WatchHi";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
+ break;
case 28:
switch (sel) {
case 0:
@@ -5295,6 +5314,25 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case 19:
+ switch (sel) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ /* upper 32 bits are only available when Config5MI != 0 */
+ /* CP0_CHECK(ctx->mi); */
+ gen_helper_0e1i(mthc0_watchhi, arg, sel);
+ rn = "WatchHi";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
+ break;
case 28:
switch (sel) {
case 0:
@@ -7293,7 +7331,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
- gen_helper_1e0i(mfc0_watchhi, arg, sel);
+ gen_helper_1e0i(dmfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
default:
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (8 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers Aleksandar Markovic
` (12 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add CPO MemoryMapID register. It is used by Global TLB Invalidate
instruction (GINVT).
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/internal.h | 1 +
target/mips/machine.c | 4 ++++
3 files changed, 6 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 10c3813..77c6355 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -252,6 +252,7 @@ struct CPUMIPSState {
#define CP0GN_VPId 0
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+ int32_t CP0_MemoryMapID;
int32_t CP0_PageMask;
int32_t CP0_PageGrain_rw_bitmask;
int32_t CP0_PageGrain;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 2898bfc..6888a06 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -91,6 +91,7 @@ struct r4k_tlb_t {
target_ulong VPN;
uint32_t PageMask;
uint16_t ASID;
+ uint32_t MMID;
unsigned int G:1;
unsigned int C0:3;
unsigned int C1:3;
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 0ef9b71..8e34b8c 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -136,6 +136,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field)
qemu_get_betls(f, &v->VPN);
qemu_get_be32s(f, &v->PageMask);
qemu_get_be16s(f, &v->ASID);
+ qemu_get_be32s(f, &v->MMID);
qemu_get_be16s(f, &flags);
v->G = (flags >> 10) & 1;
v->C0 = (flags >> 7) & 3;
@@ -161,6 +162,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field,
r4k_tlb_t *v = pv;
uint16_t asid = v->ASID;
+ uint32_t mmid = v->MMID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
@@ -177,6 +179,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field,
qemu_put_betls(f, &v->VPN);
qemu_put_be32s(f, &v->PageMask);
qemu_put_be16s(f, &asid);
+ qemu_put_be32s(f, &mmid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
@@ -251,6 +254,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
+ VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (9 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
` (11 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
SAARI (Special Address Access Register Index) provides an index
into the SAAR register to indicate whether the ITU or other block
is being accessed. SAAR (Special Address Access Register) stores
the base address where the ITU will be located, as well as the
block size.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 7 +++++
target/mips/helper.h | 6 +++++
target/mips/internal.h | 1 +
target/mips/machine.c | 2 ++
target/mips/op_helper.c | 51 +++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++---
6 files changed, 131 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 77c6355..dc0122d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -345,6 +345,12 @@ struct CPUMIPSState {
uint32_t CP0_BadInstrP;
uint32_t CP0_BadInstrX;
int32_t CP0_Count;
+#define CP0SAARI_IDX 0
+ uint32_t CP0_SAARI;
+#define CP0SAAR_BASE 12
+#define CP0SAAR_SIZE 1
+#define CP0SAAR_EN 0
+ uint64_t CP0_SAAR[2];
target_ulong CP0_EntryHi;
#define CP0EnHi_EHINV 10
target_ulong CP0_EntryHi_ASID_mask;
@@ -635,6 +641,7 @@ struct CPUMIPSState {
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
+ int saarp;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 0ec500a..ba4a872 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env)
DEF_HELPER_1(mfc0_tcschefback, tl, env)
DEF_HELPER_1(mftc0_tcschefback, tl, env)
DEF_HELPER_1(mfc0_count, tl, env)
+DEF_HELPER_1(mfc0_saar, tl, env)
+DEF_HELPER_1(mfhc0_saar, tl, env)
DEF_HELPER_1(mftc0_entryhi, tl, env)
DEF_HELPER_1(mftc0_status, tl, env)
DEF_HELPER_1(mftc0_cause, tl, env)
@@ -89,6 +91,7 @@ DEF_HELPER_1(dmfc0_lladdr, tl, env)
DEF_HELPER_1(dmfc0_maar, tl, env)
DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
DEF_HELPER_2(dmfc0_watchhi, tl, env, i32)
+DEF_HELPER_1(dmfc0_saar, tl, env)
#endif /* TARGET_MIPS64 */
DEF_HELPER_2(mtc0_index, void, env, tl)
@@ -133,6 +136,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
DEF_HELPER_2(mtc0_hwrena, void, env, tl)
DEF_HELPER_2(mtc0_pwctl, void, env, tl)
DEF_HELPER_2(mtc0_count, void, env, tl)
+DEF_HELPER_2(mtc0_saari, void, env, tl)
+DEF_HELPER_2(mtc0_saar, void, env, tl)
+DEF_HELPER_2(mthc0_saar, void, env, tl)
DEF_HELPER_2(mtc0_entryhi, void, env, tl)
DEF_HELPER_2(mttc0_entryhi, void, env, tl)
DEF_HELPER_2(mtc0_compare, void, env, tl)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 6888a06..54bf39f 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -61,6 +61,7 @@ struct mips_def_t {
target_ulong CP0_EBaseWG_rw_bitmask;
int insn_flags;
enum mips_mmu_types mmu_type;
+ int32_t SAARP;
};
extern const struct mips_def_t mips_defs[];
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 8e34b8c..41d0bbc 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -276,6 +276,8 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
+ VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 3d86c60..1fae357 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -938,6 +938,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env)
return count;
}
+target_ulong helper_mfc0_saar(CPUMIPSState *env)
+{
+ if ((env->CP0_SAARI & 0x3f) < 2) {
+ return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
+ }
+ return 0;
+}
+
+target_ulong helper_mfhc0_saar(CPUMIPSState *env)
+{
+ if ((env->CP0_SAARI & 0x3f) < 2) {
+ return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
+ }
+ return 0;
+}
+
target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
{
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
@@ -1069,6 +1085,15 @@ target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
{
return env->CP0_WatchHi[sel];
}
+
+target_ulong helper_dmfc0_saar(CPUMIPSState *env)
+{
+ if ((env->CP0_SAARI & 0x3f) < 2) {
+ return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
+ }
+ return 0;
+}
+
#endif /* TARGET_MIPS64 */
void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
@@ -1580,6 +1605,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
qemu_mutex_unlock_iothread();
}
+void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
+{
+ uint32_t target = arg1 & 0x3f;
+ if (target <= 1) {
+ env->CP0_SAARI = target;
+ }
+}
+
+void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
+{
+ uint32_t target = env->CP0_SAARI & 0x3f;
+ if (target < 2) {
+ env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
+ }
+}
+
+void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
+{
+ uint32_t target = env->CP0_SAARI & 0x3f;
+ if (target < 2) {
+ env->CP0_SAAR[target] =
+ (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
+ (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
+ }
+}
+
void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
{
target_ulong old, val, mask;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8bff0e1..5f561d2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1473,6 +1473,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+ bool saar;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -5207,6 +5208,17 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case 9:
+ switch (sel) {
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mfhc0_saar(arg, cpu_env);
+ rn = "SAAR";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
+ break;
case 17:
switch (sel) {
case 0:
@@ -5296,6 +5308,16 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
goto cp0_unimplemented;
}
break;
+ case 9:
+ switch (sel) {
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mthc0_saar(cpu_env, arg);
+ rn = "SAAR";
+ break;
+ default:
+ goto cp0_unimplemented;
+ }
case 17:
switch (sel) {
case 0:
@@ -5701,7 +5723,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mfc0_saar(arg, cpu_env);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -6406,7 +6437,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saari(cpu_env, arg);
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saar(cpu_env, arg);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7151,7 +7191,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_dmfc0_saar(arg, cpu_env);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -7839,7 +7888,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_helper_mtc0_count(cpu_env, arg);
rn = "Count";
break;
- /* 6,7 are implementation dependent */
+ case 6:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saari(cpu_env, arg);
+ rn = "SAARI";
+ break;
+ case 7:
+ CP0_CHECK(ctx->saar);
+ gen_helper_mtc0_saar(cpu_env, arg);
+ rn = "SAAR";
+ break;
default:
goto cp0_unimplemented;
}
@@ -25437,6 +25495,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ ctx->saar = (bool) env->saarp;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
@@ -25802,6 +25861,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31;
env->msair = env->cpu_model->MSAIR;
env->insn_flags = env->cpu_model->insn_flags;
+ env->saarp = env->cpu_model->SAARP;
#if defined(CONFIG_USER_ONLY)
env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (10 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control " Aleksandar Markovic
` (10 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add DSP R3 ASE related bit definition for insn_flags and hflags.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 1 +
target/mips/mips-defs.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index dc0122d..f07b94e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -624,6 +624,7 @@ struct CPUMIPSState {
/* MIPS DSP resources access. */
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
+#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index c8e9979..b27b7ae 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -47,6 +47,7 @@
#define ASE_MDMX 0x00040000
#define ASE_DSP 0x00080000
#define ASE_DSPR2 0x00100000
+#define ASE_DSPR3 0x02000000
#define ASE_MT 0x00200000
#define ASE_SMARTMIPS 0x00400000
#define ASE_MICROMIPS 0x00800000
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control for DSP R3 ASE
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (11 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming Aleksandar Markovic
` (9 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/internal.h | 11 ++++++++---
target/mips/translate.c | 13 ++++++++++++-
target/mips/translate_init.inc.c | 3 ++-
3 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 54bf39f..e367d7e 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -310,8 +310,8 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
- MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
- MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
+ MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
+ MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->hflags |= MIPS_HFLAG_ERL;
}
@@ -358,7 +358,12 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
env->hflags |= MIPS_HFLAG_SBRI;
}
- if (env->insn_flags & ASE_DSPR2) {
+ if (env->insn_flags & ASE_DSPR3) {
+ if (env->CP0_Status & (1 << CP0St_MX)) {
+ env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
+ MIPS_HFLAG_DSPR3;
+ }
+ } else if (env->insn_flags & ASE_DSPR2) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
so enable to access DSPR2 resources. */
if (env->CP0_Status & (1 << CP0St_MX)) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5f561d2..9ce3f87 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1869,6 +1869,17 @@ static inline void check_dspr2(DisasContext *ctx)
}
}
+static inline void check_dspr3(DisasContext *ctx)
+{
+ if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
+ if (ctx->insn_flags & ASE_DSP) {
+ generate_exception_end(ctx, EXCP_DSPDIS);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+ }
+}
+
/* This code generates a "reserved instruction" exception if the
CPU does not support the instruction set corresponding to flags. */
static inline void check_insn(DisasContext *ctx, int flags)
@@ -20285,7 +20296,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break;
case NM_BPOSGE32C:
- check_dspr2(ctx);
+ check_dspr3(ctx);
{
int32_t imm = extract32(ctx->opcode, 1, 13) |
extract32(ctx->opcode, 0, 1) << 13;
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index b3320b9..d7cd4ee 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -485,7 +485,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
+ .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
+ ASE_MT,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (12 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control " Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:32 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S> Aleksandar Markovic
` (8 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Stefan Markovic <smarkovic@wavecomp.com>
Do following replacements:
ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/internal.h | 4 +-
target/mips/mips-defs.h | 4 +-
target/mips/translate.c | 180 +++++++++++++++++++--------------------
target/mips/translate_init.inc.c | 6 +-
4 files changed, 97 insertions(+), 97 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index e367d7e..6cf00d8 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -358,12 +358,12 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
env->hflags |= MIPS_HFLAG_SBRI;
}
- if (env->insn_flags & ASE_DSPR3) {
+ if (env->insn_flags & ASE_DSP_R3) {
if (env->CP0_Status & (1 << CP0St_MX)) {
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_DSPR3;
}
- } else if (env->insn_flags & ASE_DSPR2) {
+ } else if (env->insn_flags & ASE_DSP_R2) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
so enable to access DSPR2 resources. */
if (env->CP0_Status & (1 << CP0St_MX)) {
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b27b7ae..5b985b8 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -46,8 +46,8 @@
#define ASE_MIPS3D 0x00020000
#define ASE_MDMX 0x00040000
#define ASE_DSP 0x00080000
-#define ASE_DSPR2 0x00100000
-#define ASE_DSPR3 0x02000000
+#define ASE_DSP_R2 0x00100000
+#define ASE_DSP_R3 0x02000000
#define ASE_MT 0x00200000
#define ASE_SMARTMIPS 0x00400000
#define ASE_MICROMIPS 0x00800000
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9ce3f87..61989f4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1858,7 +1858,7 @@ static inline void check_dsp(DisasContext *ctx)
}
}
-static inline void check_dspr2(DisasContext *ctx)
+static inline void check_dsp_r2(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
if (ctx->insn_flags & ASE_DSP) {
@@ -1869,7 +1869,7 @@ static inline void check_dspr2(DisasContext *ctx)
}
}
-static inline void check_dspr3(DisasContext *ctx)
+static inline void check_dsp_r3(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
if (ctx->insn_flags & ASE_DSP) {
@@ -17642,7 +17642,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
case NM_POOL32AXF_2_0_7:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpa_w_ph(t0, v1, v0, cpu_env);
break;
case NM_DPAQ_S_W_PH:
@@ -17650,7 +17650,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env);
break;
case NM_DPS_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dps_w_ph(t0, v1, v0, cpu_env);
break;
case NM_DPSQ_S_W_PH:
@@ -17665,7 +17665,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
case NM_POOL32AXF_2_8_15:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpax_w_ph(t0, v0, v1, cpu_env);
break;
case NM_DPAQ_SA_L_W:
@@ -17673,7 +17673,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env);
break;
case NM_DPSX_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env);
break;
case NM_DPSQ_SA_L_W:
@@ -17692,7 +17692,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env);
break;
case NM_DPAQX_S_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env);
break;
case NM_DPSU_H_QBL:
@@ -17700,11 +17700,11 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env);
break;
case NM_DPSQX_S_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env);
break;
case NM_MULSA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
break;
default:
@@ -17719,7 +17719,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env);
break;
case NM_DPAQX_SA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env);
break;
case NM_DPSU_H_QBR:
@@ -17727,7 +17727,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env);
break;
case NM_DPSQX_SA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env);
break;
case NM_MULSAQ_S_W_PH:
@@ -17769,7 +17769,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
break;
case NM_BALIGN:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
if (rt != 0) {
gen_load_gpr(t0, rs);
rd &= 3;
@@ -17999,7 +17999,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_ABSQ_S_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_absq_s_qb(v0_t, v0_t, cpu_env);
gen_store_gpr(v0_t, ret);
break;
@@ -18138,7 +18138,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_SHRA_R_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
tcg_gen_movi_tl(t0, rd >> 2);
switch (extract32(ctx->opcode, 12, 1)) {
case 0:
@@ -18154,7 +18154,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
}
break;
case NM_SHRL_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
tcg_gen_movi_tl(t0, rd >> 1);
gen_helper_shrl_ph(t0, t0, rs_t);
gen_store_gpr(t0, rt);
@@ -19079,19 +19079,19 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(v1_t, ret);
break;
case NM_CMPGDU_EQ_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgu_eq_qb(v1_t, v1_t, v2_t);
tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
gen_store_gpr(v1_t, ret);
break;
case NM_CMPGDU_LT_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgu_lt_qb(v1_t, v1_t, v2_t);
tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
gen_store_gpr(v1_t, ret);
break;
case NM_CMPGDU_LE_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgu_le_qb(v1_t, v1_t, v2_t);
tcg_gen_deposit_tl(cpu_dspctrl, cpu_dspctrl, v1_t, 24, 4);
gen_store_gpr(v1_t, ret);
@@ -19147,7 +19147,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDQH_R_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDQH_PH */
@@ -19162,7 +19162,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDQH_R_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDQH_W */
@@ -19192,7 +19192,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDU_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDU_PH */
@@ -19207,7 +19207,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDUH_R_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDUH_QB */
@@ -19237,7 +19237,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SHRAV_R_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SHRAV_QB */
@@ -19267,7 +19267,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBQH_R_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBQH_PH */
@@ -19282,7 +19282,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBQH_R_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBQH_W */
@@ -19312,7 +19312,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBU_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBU_PH */
@@ -19327,7 +19327,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBUH_R_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBUH_QB */
@@ -19357,7 +19357,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_PRECR_SRA_R_PH_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* PRECR_SRA_PH_W */
@@ -19397,22 +19397,22 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_RS_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env);
gen_store_gpr(v1_t, ret);
break;
case NM_MULQ_S_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env);
gen_store_gpr(v1_t, ret);
break;
case NM_APPEND:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_load_gpr(t0, rs);
if (rd != 0) {
tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], rd, 32 - rd);
@@ -19430,7 +19430,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(v1_t, ret);
break;
case NM_SHRLV_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shrl_ph(v1_t, v1_t, v2_t);
gen_store_gpr(v1_t, ret);
break;
@@ -19472,7 +19472,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(v1_t, ret);
break;
case NM_MUL_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* MUL_PH */
@@ -19487,7 +19487,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_PRECR_QB_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_precr_qb_ph(v1_t, v1_t, v2_t);
gen_store_gpr(v1_t, ret);
break;
@@ -20296,7 +20296,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break;
case NM_BPOSGE32C:
- check_dspr3(ctx);
+ check_dsp_r3(ctx);
{
int32_t imm = extract32(ctx->opcode, 1, 13) |
extract32(ctx->opcode, 0, 1) << 13;
@@ -20805,7 +20805,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op1) {
/* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
case OPC_MULT_G_2E:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (op2) {
case OPC_ADDUH_QB:
gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
@@ -20848,7 +20848,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_ABSQ_S_PH_DSP:
switch (op2) {
case OPC_ABSQ_S_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
break;
case OPC_ABSQ_S_PH:
@@ -20927,11 +20927,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_ADDU_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_ADDU_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_SUBQ_PH:
@@ -20955,11 +20955,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_SUBU_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_SUBU_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_ADDSC:
@@ -20983,7 +20983,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_CMPU_EQ_QB_DSP:
switch (op2) {
case OPC_PRECR_QB_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_PRECRQ_QB_PH:
@@ -20991,7 +20991,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_PRECR_SRA_PH_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
{
TCGv_i32 sa_t = tcg_const_i32(v2);
gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t,
@@ -21000,7 +21000,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
}
case OPC_PRECR_SRA_R_PH_W:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
{
TCGv_i32 sa_t = tcg_const_i32(v2);
gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t,
@@ -21082,7 +21082,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
break;
case OPC_ABSQ_S_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
break;
case OPC_ABSQ_S_PW:
@@ -21126,19 +21126,19 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_SUBU_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_SUBU_S_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_SUBUH_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SUBUH_R_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_ADDQ_PW:
@@ -21166,19 +21166,19 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_ADDU_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_ADDU_S_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_ADDUH_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_ADDUH_R_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
break;
}
@@ -21186,11 +21186,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_CMPU_EQ_OB_DSP:
switch (op2) {
case OPC_PRECR_OB_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_PRECR_SRA_QH_PW:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
{
TCGv_i32 ret_t = tcg_const_i32(ret);
gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t);
@@ -21198,7 +21198,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
}
case OPC_PRECR_SRA_R_QH_PW:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
{
TCGv_i32 sa_v = tcg_const_i32(ret);
gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v);
@@ -21301,27 +21301,27 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRL_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t);
break;
case OPC_SHRLV_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRA_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t);
break;
case OPC_SHRA_R_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t);
break;
case OPC_SHRAV_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRAV_R_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRA_PH:
@@ -21400,19 +21400,19 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env);
break;
case OPC_SHRA_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0);
break;
case OPC_SHRAV_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t);
break;
case OPC_SHRA_R_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0);
break;
case OPC_SHRAV_R_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t);
break;
case OPC_SHRA_PW:
@@ -21456,11 +21456,11 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t);
break;
case OPC_SHRL_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0);
break;
case OPC_SHRLV_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t);
break;
default: /* Invalid */
@@ -21501,7 +21501,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
case OPC_MULT_G_2E:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
switch (op2) {
case OPC_MUL_PH:
gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
@@ -21536,11 +21536,11 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPAX_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPAQ_S_W_PH:
@@ -21548,19 +21548,19 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPAQX_S_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPAQX_SA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPS_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPSX_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPSQ_S_W_PH:
@@ -21568,11 +21568,11 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPSQX_S_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_DPSQX_SA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env);
break;
case OPC_MULSAQ_S_W_PH:
@@ -21604,7 +21604,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env);
break;
case OPC_MULSA_W_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env);
break;
}
@@ -21633,7 +21633,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env);
break;
case OPC_DPA_W_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env);
break;
case OPC_DPAQ_S_W_QH:
@@ -21653,7 +21653,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env);
break;
case OPC_DPS_W_QH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env);
break;
case OPC_DPSQ_S_W_QH:
@@ -21747,7 +21747,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_MULQ_S_PH:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
}
@@ -21971,7 +21971,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_CMPGDU_EQ_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t);
tcg_gen_mov_tl(cpu_gpr[ret], t1);
tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
@@ -21979,7 +21979,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
break;
case OPC_CMPGDU_LT_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t);
tcg_gen_mov_tl(cpu_gpr[ret], t1);
tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
@@ -21987,7 +21987,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1);
break;
case OPC_CMPGDU_LE_QB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgu_le_qb(t1, v1_t, v2_t);
tcg_gen_mov_tl(cpu_gpr[ret], t1);
tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF);
@@ -22048,15 +22048,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env);
break;
case OPC_CMPGDU_EQ_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_CMPGDU_LT_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_CMPGDU_LE_OB:
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env);
break;
case OPC_CMPGU_EQ_OB:
@@ -22114,7 +22114,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
{
TCGv t0;
- check_dspr2(ctx);
+ check_dsp_r2(ctx);
if (rt == 0) {
/* Treat as NOP. */
@@ -22999,7 +22999,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
- if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
+ if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
op2 = MASK_ADDUH_QB(ctx->opcode);
switch (op2) {
case OPC_ADDUH_QB:
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index d7cd4ee..b94a09e 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -320,7 +320,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -485,7 +485,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
+ .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
ASE_MT,
.mmu_type = MMU_TYPE_R4000,
},
@@ -787,7 +787,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
+ .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
.mmu_type = MMU_TYPE_R4000,
},
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S>
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (13 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:34 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
` (7 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Matthew Fortune <matthew.fortune@mips.com>
Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S> instructions.
Their handling was permuted.
Signed-off-by: Matthew Fortune <matthew.fortune@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 61989f4..34c20fc 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -15197,15 +15197,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case 0x38:
/* cmovs */
switch ((ctx->opcode >> 6) & 0x7) {
- case MOVN_FMT: /* SELNEZ_FMT */
+ case MOVN_FMT: /* SELEQZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
- /* SELNEZ_FMT */
+ /* SELEQZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
- gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+ gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
- gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+ gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
@@ -15219,15 +15219,15 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6);
FINSN_3ARG_SDPS(MOVN);
break;
- case MOVZ_FMT: /* SELEQZ_FMT */
+ case MOVZ_FMT: /* SELNEZ_FMT */
if (ctx->insn_flags & ISA_MIPS32R6) {
- /* SELEQZ_FMT */
+ /* SELNEZ_FMT */
switch ((ctx->opcode >> 9) & 0x3) {
case FMT_SDPS_S:
- gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+ gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
break;
case FMT_SDPS_D:
- gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+ gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
break;
default:
goto pool32f_invalid;
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (14 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S> Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of " Aleksandar Markovic
` (6 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 34c20fc..f77becb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16686,6 +16686,40 @@ enum {
NM_P_SC = 0x0b,
};
+/* P.LS.E0 instruction pool */
+enum {
+ NM_LBE = 0x00,
+ NM_SBE = 0x01,
+ NM_LBUE = 0x02,
+ NM_P_PREFE = 0x03,
+ NM_LHE = 0x04,
+ NM_SHE = 0x05,
+ NM_LHUE = 0x06,
+ NM_CACHEE = 0x07,
+ NM_LWE = 0x08,
+ NM_SWE = 0x09,
+ NM_P_LLE = 0x0a,
+ NM_P_SCE = 0x0b,
+};
+
+/* P.PREFE instruction pool */
+enum {
+ NM_SYNCIE = 0x00,
+ NM_PREFE = 0x01,
+};
+
+/* P.LLE instruction pool */
+enum {
+ NM_LLE = 0x00,
+ NM_LLWPE = 0x01,
+};
+
+/* P.SCE instruction pool */
+enum {
+ NM_SCE = 0x00,
+ NM_SCWPE = 0x01,
+};
+
/* P.LS.WM instruction pool */
enum {
NM_LWM = 0x00,
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of nanoMIPS EVA instructions
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (15 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 12:05 ` Philippe Mathieu-Daudé
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 18/22] hw/mips: Update ITU to utilise SAARI/SAAR registers Aleksandar Markovic
` (5 subsequent siblings)
22 siblings, 1 reply; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Dimitrije Nikolic <dnikolic@wavecomp.com>
Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.
Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f77becb..f631930 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1991,6 +1991,17 @@ static inline void check_nms(DisasContext *ctx)
}
}
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 EVA bit is NOT set.
+ */
+static inline void check_eva(DisasContext *ctx)
+{
+ if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
+ generate_exception_end(ctx, EXCP_RI);
+ }
+}
+
/* Define small wrappers for gen_load_fpr* so that we have a uniform
calling interface for 32 and 64-bit FPRs. No sense in changing
@@ -20216,6 +20227,74 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case NM_P_LS_E0:
+ check_eva(ctx);
+ switch (extract32(ctx->opcode, 11, 4)) {
+ case NM_LBE:
+ gen_ld(ctx, OPC_LBE, rt, rs, s);
+ break;
+ case NM_SBE:
+ gen_st(ctx, OPC_SBE, rt, rs, s);
+ break;
+ case NM_LBUE:
+ gen_ld(ctx, OPC_LBUE, rt, rs, s);
+ break;
+ case NM_P_PREFE:
+ if (rt == 31) {
+ /* SYNCIE */
+ /* Break the TB to be able to sync copied instructions
+ immediately */
+ ctx->base.is_jmp = DISAS_STOP;
+ } else {
+ /* PREF */
+ /* Treat as NOP. */
+ }
+ break;
+ case NM_LHE:
+ gen_ld(ctx, OPC_LHE, rt, rs, s);
+ break;
+ case NM_SHE:
+ gen_st(ctx, OPC_SHE, rt, rs, s);
+ break;
+ case NM_LHUE:
+ gen_ld(ctx, OPC_LHUE, rt, rs, s);
+ break;
+ case NM_CACHEE:
+ /* Treat as no-op */
+ if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
+ gen_cache_operation(ctx, rt, rs, s);
+ }
+ break;
+ case NM_LWE:
+ gen_ld(ctx, OPC_LWE, rt, rs, s);
+ break;
+ case NM_SWE:
+ gen_st(ctx, OPC_SWE, rt, rs, s);
+ break;
+ case NM_P_LLE:
+ switch (extract32(ctx->opcode, 2, 2)) {
+ case NM_LL:
+ gen_ld(ctx, OPC_LLE, rt, rs, s);
+ break;
+ case NM_LLWP:
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ case NM_P_SCE:
+ switch (extract32(ctx->opcode, 2, 2)) {
+ case NM_SC:
+ gen_st_cond(ctx, OPC_SCE, rt, rs, s);
+ break;
+ case NM_SCWP:
+ default:
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+ break;
+ }
+ break;
case NM_P_LS_WM:
case NM_P_LS_UAWM:
check_nms(ctx);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 18/22] hw/mips: Update ITU to utilise SAARI/SAAR registers
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (16 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of " Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM Aleksandar Markovic
` (4 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Update the ITU to utilise SAARI/SAAR registers and add new ITU
Control Register (ICR0).
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
hw/mips/cps.c | 8 ++++++
hw/misc/mips_itu.c | 72 +++++++++++++++++++++++++++++++++++++++++-----
include/hw/misc/mips_itu.h | 7 +++++
target/mips/cpu.h | 5 ++++
target/mips/op_helper.c | 14 +++++++++
5 files changed, 99 insertions(+), 7 deletions(-)
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 4285d19..dd68795 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
target_ulong gcr_base;
bool itu_present = false;
+ bool saar_present = false;
for (i = 0; i < s->num_vp; i++) {
cpu = MIPS_CPU(cpu_create(s->cpu_type));
@@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
itu_present = true;
/* Attach ITC Tag to the VP */
env->itc_tag = mips_itu_get_tag_region(&s->itu);
+ env->itu = &s->itu;
}
qemu_register_reset(main_cpu_reset, cpu);
}
cpu = MIPS_CPU(first_cpu);
env = &cpu->env;
+ saar_present = (bool) env->saarp;
/* Inter-Thread Communication Unit */
if (itu_present) {
@@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
+ object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
+ &err);
+ if (saar_present) {
+ qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *) &env->CP0_SAAR);
+ }
object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
index 43bbec4..746e0c2 100644
--- a/hw/misc/mips_itu.c
+++ b/hw/misc/mips_itu.c
@@ -55,9 +55,17 @@ typedef enum ITCView {
ITCVIEW_EF_SYNC = 2,
ITCVIEW_EF_TRY = 3,
ITCVIEW_PV_SYNC = 4,
- ITCVIEW_PV_TRY = 5
+ ITCVIEW_PV_TRY = 5,
+ ITCVIEW_PV_ICR = 15
} ITCView;
+#define ITC_ICR0_CELL_NUM 16
+#define ITC_ICR0_BLK_GRAIN 8
+#define ITC_ICR0_BLK_GRAIN_MASK 0x7
+#define ITC_ICR0_ERR_AXI 2
+#define ITC_ICR0_ERR_PARITY 1
+#define ITC_ICR0_ERR_EXEC 0
+
MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
{
return &itu->tag_io;
@@ -76,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
return tag->ITCAddressMap[index];
}
-static void itc_reconfigure(MIPSITUState *tag)
+void itc_reconfigure(MIPSITUState *tag)
{
uint64_t *am = &tag->ITCAddressMap[0];
MemoryRegion *mr = &tag->storage_io;
@@ -84,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag)
uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
+ if (tag->saar_present) {
+ address = ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4;
+ size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
+ is_enabled = *(uint64_t *) tag->saar & 1;
+ }
+
memory_region_transaction_begin();
if (!(size & (size - 1))) {
memory_region_set_size(mr, size);
@@ -142,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr)
static inline int get_cell_stride_shift(const MIPSITUState *s)
{
/* Minimum interval (for EntryGain = 0) is 128 B */
- return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
+ if (s->saar_present) {
+ return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
+ ITC_ICR0_BLK_GRAIN_MASK);
+ } else {
+ return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
+ }
}
static inline ITCStorageCell *get_cell(MIPSITUState *s,
@@ -356,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c)
view_pv_common_write(c);
}
+static void raise_exception(int excp)
+{
+ current_cpu->exception_index = excp;
+ cpu_loop_exit(current_cpu);
+}
+
static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
{
MIPSITUState *s = (MIPSITUState *)opaque;
@@ -363,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
ITCView view = get_itc_view(addr);
uint64_t ret = -1;
+ switch (size) {
+ case 1:
+ case 2:
+ s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
+ raise_exception(EXCP_DBE);
+ return 0;
+ }
+
switch (view) {
case ITCVIEW_BYPASS:
ret = view_bypass_read(cell);
@@ -382,6 +415,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
case ITCVIEW_PV_TRY:
ret = view_pv_try_read(cell);
break;
+ case ITCVIEW_PV_ICR:
+ ret = s->icr0;
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_read: Bad ITC View %d\n", (int)view);
@@ -398,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
ITCStorageCell *cell = get_cell(s, addr);
ITCView view = get_itc_view(addr);
+ switch (size) {
+ case 1:
+ case 2:
+ s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
+ raise_exception(EXCP_DBE);
+ return;
+ }
+
switch (view) {
case ITCVIEW_BYPASS:
view_bypass_write(cell, data);
@@ -417,6 +461,15 @@ static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
case ITCVIEW_PV_TRY:
view_pv_try_write(cell);
break;
+ case ITCVIEW_PV_ICR:
+ if (data & 0x7) {
+ /* clear ERROR bits */
+ s->icr0 &= ~(data & 0x7);
+ }
+ /* set BLK_GRAIN */
+ s->icr0 &= ~0x700;
+ s->icr0 |= data & 0x700;
+ break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"itc_storage_write: Bad ITC View %d\n", (int)view);
@@ -479,10 +532,15 @@ static void mips_itu_reset(DeviceState *dev)
{
MIPSITUState *s = MIPS_ITU(dev);
- s->ITCAddressMap[0] = 0;
- s->ITCAddressMap[1] =
- ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
- (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
+ if (s->saar_present) {
+ *(uint64_t *) s->saar = 0x11 << 1;
+ s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
+ } else {
+ s->ITCAddressMap[0] = 0;
+ s->ITCAddressMap[1] =
+ ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
+ (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
+ }
itc_reconfigure(s);
itc_reset_cells(s);
diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
index 030eb4a..bb9667a 100644
--- a/include/hw/misc/mips_itu.h
+++ b/include/hw/misc/mips_itu.h
@@ -66,6 +66,13 @@ typedef struct MIPSITUState {
/* ITC Configuration Tags */
uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
MemoryRegion tag_io;
+
+ /* ITU Control Registers */
+ uint64_t icr0;
+
+ /* SAAR */
+ bool saar_present;
+ void *saar;
} MIPSITUState;
/* Get ITC Configuration Tag memory region. */
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index f07b94e..9c57878 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -172,6 +172,7 @@ struct TCState {
float_status msa_fp_status;
};
+struct MIPSITUState;
typedef struct CPUMIPSState CPUMIPSState;
struct CPUMIPSState {
TCState active_tc;
@@ -658,6 +659,7 @@ struct CPUMIPSState {
const mips_def_t *cpu_model;
void *irq[8];
QEMUTimer *timer; /* Internal timer */
+ struct MIPSITUState *itu;
MemoryRegion *itc_tag; /* ITC Configuration Tags */
target_ulong exception_base; /* ExceptionBase input to the core */
};
@@ -800,6 +802,9 @@ void cpu_set_exception_base(int vp_index, target_ulong address);
/* mips_int.c */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
+/* mips_itu.c */
+void itc_reconfigure(struct MIPSITUState *tag);
+
/* helper.c */
target_ulong exception_resume_pc (CPUMIPSState *env);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 1fae357..2ef0134 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1618,6 +1618,13 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
uint32_t target = env->CP0_SAARI & 0x3f;
if (target < 2) {
env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
+ switch (target) {
+ case 0:
+ if (env->itu) {
+ itc_reconfigure(env->itu);
+ }
+ break;
+ }
}
}
@@ -1628,6 +1635,13 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
env->CP0_SAAR[target] =
(((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
(env->CP0_SAAR[target] & 0x00000000ffffffffULL);
+ switch (target) {
+ case 0:
+ if (env->itu) {
+ itc_reconfigure(env->itu);
+ }
+ break;
+ }
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (17 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 18/22] hw/mips: Update ITU to utilise SAARI/SAAR registers Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 20/22] target/mips: Add DEC feature to mips32r6-generic CPU Aleksandar Markovic
` (3 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
The optional Data Scratch Pad RAM (DSPRAM) block provides a
general scratch pad RAM used for temporary storage of data. The
DSPRAM provides a connection to on-chip memory or memory-mapped
registers, which are accessed in parallel with the L1 data
cache to minimize access latency.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
default-configs/mips-softmmu-common.mak | 1 +
hw/mips/cps.c | 3 ++-
hw/mips/mips_malta.c | 31 +++++++++++++++++++++++++++++++
hw/misc/Makefile.objs | 1 +
include/hw/mips/cps.h | 2 ++
target/mips/cpu.h | 5 +++++
target/mips/internal.h | 1 +
target/mips/op_helper.c | 10 ++++++++++
target/mips/translate.c | 7 +++++++
9 files changed, 60 insertions(+), 1 deletion(-)
diff --git a/default-configs/mips-softmmu-common.mak b/default-configs/mips-softmmu-common.mak
index fae2347..45f2cbf 100644
--- a/default-configs/mips-softmmu-common.mak
+++ b/default-configs/mips-softmmu-common.mak
@@ -36,3 +36,4 @@ CONFIG_EMPTY_SLOT=y
CONFIG_MIPS_CPS=y
CONFIG_MIPS_ITU=y
CONFIG_I2C=y
+CONFIG_MIPS_DSPRAM=y
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index dd68795..93d3bea 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -102,7 +102,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
&err);
if (saar_present) {
- qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *) &env->CP0_SAAR);
+ qdev_prop_set_ptr(DEVICE(&s->itu), "saar",
+ (void *) &env->CP0_SAAR[0]);
}
object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
if (err != NULL) {
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 29b90ba..1b1bbd8 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1169,6 +1169,36 @@ static void create_cps(MaltaState *s, const char *cpu_type,
*cbus_irq = NULL;
}
+static void create_dspram(void)
+{
+ MIPSCPU *cpu = MIPS_CPU(first_cpu);
+ CPUMIPSState *env = &cpu->env;
+ bool dspram_present = (bool) env->dspramp;
+ Error *err = NULL;
+
+ env->dspram = g_new0(MIPSDSPRAMState, 1);
+
+ /* DSPRAM */
+ if (dspram_present) {
+ if (!(bool) env->saarp) {
+ error_report("%s: DSPRAM requires SAAR registers", __func__);
+ exit(1);
+ }
+ object_initialize(env->dspram, sizeof(MIPSDSPRAMState),
+ TYPE_MIPS_DSPRAM);
+ qdev_set_parent_bus(DEVICE(env->dspram), sysbus_get_default());
+ qdev_prop_set_ptr(DEVICE(env->dspram), "saar",
+ (void *) &env->CP0_SAAR[1]);
+ object_property_set_bool(OBJECT(env->dspram), true, "realized", &err);
+ if (err != NULL) {
+ error_report("%s: DSPRAM initialisation failed", __func__);
+ exit(1);
+ }
+ memory_region_add_subregion(get_system_memory(), 0,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(env->dspram), 0));
+ }
+}
+
static void mips_create_cpu(MaltaState *s, const char *cpu_type,
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
{
@@ -1177,6 +1207,7 @@ static void mips_create_cpu(MaltaState *s, const char *cpu_type,
} else {
create_cpu_without_cps(cpu_type, cbus_irq, i8259_irq);
}
+ create_dspram();
}
static
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 6d50b03..37a1b41 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
obj-$(CONFIG_MIPS_ITU) += mips_itu.o
+obj-$(CONFIG_MIPS_DSPRAM) += mips_dspram.o
obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index aab1af9..a637036 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -25,6 +25,7 @@
#include "hw/intc/mips_gic.h"
#include "hw/misc/mips_cpc.h"
#include "hw/misc/mips_itu.h"
+#include "hw/misc/mips_dspram.h"
#define TYPE_MIPS_CPS "mips-cps"
#define MIPS_CPS(obj) OBJECT_CHECK(MIPSCPSState, (obj), TYPE_MIPS_CPS)
@@ -41,6 +42,7 @@ typedef struct MIPSCPSState {
MIPSGICState gic;
MIPSCPCState cpc;
MIPSITUState itu;
+ MIPSDSPRAMState dspram;
} MIPSCPSState;
qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 9c57878..a2aca3f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -644,6 +644,7 @@ struct CPUMIPSState {
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
int saarp;
+ int dspramp;
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@@ -661,6 +662,7 @@ struct CPUMIPSState {
QEMUTimer *timer; /* Internal timer */
struct MIPSITUState *itu;
MemoryRegion *itc_tag; /* ITC Configuration Tags */
+ struct MIPSDSPRAMState *dspram;
target_ulong exception_base; /* ExceptionBase input to the core */
};
@@ -805,6 +807,9 @@ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* mips_itu.c */
void itc_reconfigure(struct MIPSITUState *tag);
+/* mips_dspram.c */
+void dspram_reconfigure(struct MIPSDSPRAMState *dspram);
+
/* helper.c */
target_ulong exception_resume_pc (CPUMIPSState *env);
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 6cf00d8..6aedf70 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -62,6 +62,7 @@ struct mips_def_t {
int insn_flags;
enum mips_mmu_types mmu_type;
int32_t SAARP;
+ int32_t DSPRAMP;
};
extern const struct mips_def_t mips_defs[];
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 2ef0134..31fba8b 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1624,6 +1624,11 @@ void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
itc_reconfigure(env->itu);
}
break;
+ case 1:
+ if (env->dspram) {
+ dspram_reconfigure(env->dspram);
+ }
+ break;
}
}
}
@@ -1641,6 +1646,11 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
itc_reconfigure(env->itu);
}
break;
+ case 1:
+ if (env->dspram) {
+ dspram_reconfigure(env->dspram);
+ }
+ break;
}
}
}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f631930..608b276 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -25986,6 +25986,7 @@ void cpu_state_reset(CPUMIPSState *env)
env->msair = env->cpu_model->MSAIR;
env->insn_flags = env->cpu_model->insn_flags;
env->saarp = env->cpu_model->SAARP;
+ env->dspramp = env->cpu_model->DSPRAMP;
#if defined(CONFIG_USER_ONLY)
env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU);
@@ -26122,6 +26123,12 @@ void cpu_state_reset(CPUMIPSState *env)
msa_reset(env);
}
+ /* DSPRAM */
+ if (env->dspramp) {
+ /* Fixed DSPRAM size with Default Value */
+ env->CP0_SAAR[1] = 0x10 << 1;
+ }
+
compute_hflags(env);
restore_fp_status(env);
restore_pamask(env);
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 20/22] target/mips: Add DEC feature to mips32r6-generic CPU
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (18 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 21/22] target/mips: Add MSA ASE to MIPS64R2-generic CPU Aleksandar Markovic
` (2 subsequent siblings)
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Set Config5.DEC Dual Endian Capability bit of mips32r6-generic CPU.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate_init.inc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index b94a09e..e390205 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -428,7 +428,8 @@ const mips_def_t mips_defs[] =
(1 << CP0C3_RXI) | (1U << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1U << CP0C4_M),
- .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_DEC) |
+ (1 << CP0C5_LLB),
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
(1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 21/22] target/mips: Add MSA ASE to MIPS64R2-generic CPU
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (19 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 20/22] target/mips: Add DEC feature to mips32r6-generic CPU Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 22/22] target/mips: Add I6500 core configuration Aleksandar Markovic
2018-10-12 13:24 ` [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add MSA ASE to MIPS64R2-generic CPU.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate_init.inc.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index e390205..e05bd6f 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -620,7 +620,10 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_MSAP),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
@@ -634,7 +637,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v4 22/22] target/mips: Add I6500 core configuration
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (20 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 21/22] target/mips: Add MSA ASE to MIPS64R2-generic CPU Aleksandar Markovic
@ 2018-10-11 11:22 ` Aleksandar Markovic
2018-10-12 13:24 ` [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 11:22 UTC (permalink / raw)
To: qemu-devel
Cc: aurelien, richard.henderson, amarkovic, smarkovic, pjovanovic,
laurent, riku.voipio
From: Yongbok Kim <yongbok.kim@mips.com>
Add I6500 core configuration. Note that this configuration is
supported only by best-effort due to lack of certain features
in QEMU.
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate_init.inc.c | 43 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index e05bd6f..33f0cb6 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -726,6 +726,49 @@ const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
+ .name = "I6500",
+ .CP0_PRid = 0x1B000,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
+ (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
+ (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
+ (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+ (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
+ (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_ULS) | (1 << CP0C5_CRCP) |
+ (3 << CP0C5_GI) | (0 << CP0C5_XNP) | (1 << CP0C5_VP) |
+ (1 << CP0C5_MVH) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_MI) |
+ (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
+ (1 << CP0C5_UFE),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 0,
+ .SYNCI_Step = 64,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x30D8FFFF,
+ .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
+ (1U << CP0PG_RIE),
+ .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
+ .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
+ (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+ (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
+ .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
+ .CP1_fcr31_rw_bitmask = 0x0103FFFF,
+ .MSAIR = 0x03 << MSAIR_ProcID,
+ .SEGBITS = 48,
+ .PABITS = 48,
+ .insn_flags = CPU_MIPS64R6 | ASE_MSA,
+ .mmu_type = MMU_TYPE_R4000,
+ .SAARP = 1,
+ .DSPRAMP = 1,
+ },
+ {
.name = "Loongson-2E",
.CP0_PRid = 0x6302,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
--
2.7.4
^ permalink raw reply related [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of nanoMIPS EVA instructions
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of " Aleksandar Markovic
@ 2018-10-11 12:05 ` Philippe Mathieu-Daudé
2018-10-11 12:19 ` Aleksandar Markovic
0 siblings, 1 reply; 36+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-11 12:05 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: smarkovic, riku.voipio, richard.henderson, laurent, amarkovic,
pjovanovic, aurelien
Hi Aleksandar,
On 11/10/2018 13:22, Aleksandar Markovic wrote:
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
>
> Implement emulation of nanoMIPS EVA instructions. They are all
> part of P.LS.E0 instruction pool, or one of its subpools.
>
> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>
Thanks for adding Dimitrije's S-o-b.
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index f77becb..f631930 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1991,6 +1991,17 @@ static inline void check_nms(DisasContext *ctx)
> }
> }
>
> +/*
> + * This code generates a "reserved instruction" exception if the
> + * Config5 EVA bit is NOT set.
> + */
> +static inline void check_eva(DisasContext *ctx)
> +{
> + if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
> + generate_exception_end(ctx, EXCP_RI);
> + }
> +}
> +
>
> /* Define small wrappers for gen_load_fpr* so that we have a uniform
> calling interface for 32 and 64-bit FPRs. No sense in changing
> @@ -20216,6 +20227,74 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
> break;
> }
> break;
> + case NM_P_LS_E0:
> + check_eva(ctx);
> + switch (extract32(ctx->opcode, 11, 4)) {
> + case NM_LBE:
> + gen_ld(ctx, OPC_LBE, rt, rs, s);
> + break;
> + case NM_SBE:
> + gen_st(ctx, OPC_SBE, rt, rs, s);
> + break;
> + case NM_LBUE:
> + gen_ld(ctx, OPC_LBUE, rt, rs, s);
> + break;
> + case NM_P_PREFE:
> + if (rt == 31) {
> + /* SYNCIE */
> + /* Break the TB to be able to sync copied instructions
> + immediately */
> + ctx->base.is_jmp = DISAS_STOP;
> + } else {
> + /* PREF */
> + /* Treat as NOP. */
> + }
> + break;
> + case NM_LHE:
> + gen_ld(ctx, OPC_LHE, rt, rs, s);
> + break;
> + case NM_SHE:
> + gen_st(ctx, OPC_SHE, rt, rs, s);
> + break;
> + case NM_LHUE:
> + gen_ld(ctx, OPC_LHUE, rt, rs, s);
> + break;
> + case NM_CACHEE:
I asked a question in your v2
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg01045.html:
What about NMS core without caches? Shouldn't we use:
check_nms(ctx);
Thanks,
Phil.
> + /* Treat as no-op */
> + if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
> + gen_cache_operation(ctx, rt, rs, s);
> + }
> + break;
> + case NM_LWE:
> + gen_ld(ctx, OPC_LWE, rt, rs, s);
> + break;
> + case NM_SWE:
> + gen_st(ctx, OPC_SWE, rt, rs, s);
> + break;
> + case NM_P_LLE:
> + switch (extract32(ctx->opcode, 2, 2)) {
> + case NM_LL:
> + gen_ld(ctx, OPC_LLE, rt, rs, s);
> + break;
> + case NM_LLWP:
> + default:
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + }
> + break;
> + case NM_P_SCE:
> + switch (extract32(ctx->opcode, 2, 2)) {
> + case NM_SC:
> + gen_st_cond(ctx, OPC_SCE, rt, rs, s);
> + break;
> + case NM_SCWP:
> + default:
> + generate_exception_end(ctx, EXCP_RI);
> + break;
> + }
> + break;
> + }
> + break;
> case NM_P_LS_WM:
> case NM_P_LS_UAWM:
> check_nms(ctx);
>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of nanoMIPS EVA instructions
2018-10-11 12:05 ` Philippe Mathieu-Daudé
@ 2018-10-11 12:19 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-11 12:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aleksandar Markovic, qemu-devel
Cc: Stefan Markovic, riku.voipio, richard.henderson, laurent,
Petar Jovanovic, aurelien
> What about NMS core without caches? Shouldn't we use:
>
> check_nms(ctx);
I don't see any support in the nanoMIPS documentation for this.
Thanks,
Aleksandar
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
@ 2018-10-12 13:19 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:19 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Fix existing and add missing PT_MIPS_XXX constants in elf.h.
> This is copied from kernel header arch/mips/include/asm/elf.h.
>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
@ 2018-10-12 13:19 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:19 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Add MIPS_ABI_FP_XXX constants to elf.h. The source of information
> is kernel header arch/mips/include/asm/elf.h.
>
>Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
@ 2018-10-12 13:20 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:20 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Add Mips_elf_abiflags_v0 structure to elf.h. The source of information
> is kernel header arch/mips/include/asm/elf.h.
>
> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
` (21 preceding siblings ...)
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 22/22] target/mips: Add I6500 core configuration Aleksandar Markovic
@ 2018-10-12 13:24 ` Aleksandar Markovic
22 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:24 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel, laurent
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
riku.voipio
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> This series contains support for MIPS ABI flags in elf.h...
>
> Stefan Markovic (6):
> elf: Fix PT_MIPS_XXX constants
> elf: Add MIPS_ABI_FP_XXX constants
> elf: Add Mips_elf_abiflags_v0 structure
Hi, Laurent
The three patches above are fairly trivial MIPS-specific additions, and they
have my "Reviewed-by"s. I think I can rightfully include them in my next
MIPS pull request. Please let me know if you have any objections about
that.
Thanks,
Aleksandar
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register Aleksandar Markovic
@ 2018-10-12 13:27 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:27 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Add PWBase register (CP0 Register 5, Select 5).
>
> The PWBase register contains the Page Table Base virtual address.
>
> This register is required for the hardware page walker feature. It
> exists only if Config3 PW bit is set to 1.
>
> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
The only problem with this and subsequent register-related patches is that
they do not bump version_id and minimum_version_id of vmstate_mips_cpu
in machine.c, and they should.
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register Aleksandar Markovic
@ 2018-10-12 13:28 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:28 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Add PWField register (CP0 Register 5, Select 6).
>
Please bump version_id and minimum_version_id of vmstate_mips_cpu in machine.c.
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register Aleksandar Markovic
@ 2018-10-12 13:29 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:29 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Add PWSize register (CP0 Register 5, Select 7).
Please bump version_id and minimum_version_id of vmstate_mips_cpu in machine.c.
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register Aleksandar Markovic
@ 2018-10-12 13:29 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:29 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Add PWCtl register (CP0 Register 5, Select 6).
Please bump version_id and minimum_version_id of vmstate_mips_cpu in machine.c.
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker Aleksandar Markovic
@ 2018-10-12 13:31 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:31 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Yongbok Kim <yongbok.kim@mips.com>
>
> Implement hardware page table walker.
What is missing is initialization of PWField and PWsize register.
This initialization is very well documented, and it should be straightforward.
Probably the best dobne in a separate patch.
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming Aleksandar Markovic
@ 2018-10-12 13:32 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:32 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Stefan Markovic <smarkovic@wavecomp.com>
>
> Do following replacements:
>
> ASE_DSPR2 -> ASE_DSP_R2
> ASE_DSPR3 -> ASE_DSP_R3
> check_dspr2() -> check_dsp_r2()
> check_dspr3() -> check_dsp_r3()
There may be a couple of other similar cases. They should be included in this patch.
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S>
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S> Aleksandar Markovic
@ 2018-10-12 13:34 ` Aleksandar Markovic
0 siblings, 0 replies; 36+ messages in thread
From: Aleksandar Markovic @ 2018-10-12 13:34 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel
Cc: aurelien, richard.henderson, Stefan Markovic, Petar Jovanovic,
laurent, riku.voipio
> From: Matthew Fortune <matthew.fortune@mips.com>
>
> Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S> instructions.
> Their handling was permuted.
"<SELEQZ|SELNEZ>.<D|S>" can be used in the title and commit message..
Other than this:
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2018-10-12 13:35 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-11 11:22 [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 01/22] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
2018-10-12 13:19 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 02/22] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
2018-10-12 13:19 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 03/22] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
2018-10-12 13:20 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 04/22] target/mips: Add CPO PWBase register Aleksandar Markovic
2018-10-12 13:27 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 05/22] target/mips: Add CPO PWField register Aleksandar Markovic
2018-10-12 13:28 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 06/22] target/mips: Add CPO PWSize register Aleksandar Markovic
2018-10-12 13:29 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 07/22] target/mips: Add CPO PWCtl register Aleksandar Markovic
2018-10-12 13:29 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 08/22] target/mips: Implement hardware page table walker Aleksandar Markovic
2018-10-12 13:31 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 09/22] target/mips: Extend WatchHi registers Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 10/22] target/mips: Add CPO MemoryMapID register Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 11/22] target/mips: Add CP0 SAARI and SAAR registers Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 12/22] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 13/22] target/mips: Add availability control " Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 14/22] target/mips: Improve DSP R2/R3-related naming Aleksandar Markovic
2018-10-12 13:32 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 15/22] target/mips: Fix emulation of microMIPS R6 SELEQZ.<D|S> SELNEZ.<D|S> Aleksandar Markovic
2018-10-12 13:34 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 16/22] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 17/22] target/mips: Implement emulation of " Aleksandar Markovic
2018-10-11 12:05 ` Philippe Mathieu-Daudé
2018-10-11 12:19 ` Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 18/22] hw/mips: Update ITU to utilise SAARI/SAAR registers Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 19/22] hw/mips: Add Data Scratch Pad RAM Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 20/22] target/mips: Add DEC feature to mips32r6-generic CPU Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 21/22] target/mips: Add MSA ASE to MIPS64R2-generic CPU Aleksandar Markovic
2018-10-11 11:22 ` [Qemu-devel] [PATCH v4 22/22] target/mips: Add I6500 core configuration Aleksandar Markovic
2018-10-12 13:24 ` [Qemu-devel] [PATCH v4 00/22] Misc MIPS fixes and improvements for October 2018 Aleksandar Markovic
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