RE: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core

From: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@amd.com>
To: Mark Brown <broonie@kernel.org>
Cc: "tudor.ambarus@linaro.org" <tudor.ambarus@linaro.org>,
	"pratyush@kernel.org" <pratyush@kernel.org>,
	"miquel.raynal@bootlin.com" <miquel.raynal@bootlin.com>,
	"richard@nod.at" <richard@nod.at>,
	"vigneshr@ti.com" <vigneshr@ti.com>,
	"sbinding@opensource.cirrus.com" <sbinding@opensource.cirrus.com>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"michael@walle.cc" <michael@walle.cc>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"nicolas.ferre@microchip.com" <nicolas.ferre@microchip.com>,
	"alexandre.belloni@bootlin.com" <alexandre.belloni@bootlin.com>,
	"claudiu.beznea@tuxon.dev" <claudiu.beznea@tuxon.dev>,
	"Simek, Michal" <michal.simek@amd.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"git (AMD-Xilinx)" <git@amd.com>,
	"amitrkcian2002@gmail.com" <amitrkcian2002@gmail.com>
Subject: RE: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
Date: Tue, 21 Nov 2023 07:18:15 +0000	[thread overview]
Message-ID: <BN7PR12MB28020429F4221F79E6D654DBDCBBA@BN7PR12MB2802.namprd12.prod.outlook.com> (raw)
In-Reply-To: <281c9708-f965-4bb1-821e-3e6cfe26ba5d@sirena.org.uk>

Hello Mark,

> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: Monday, November 20, 2023 7:33 PM
> To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@amd.com>
> Cc: tudor.ambarus@linaro.org; pratyush@kernel.org;
> miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com;
> sbinding@opensource.cirrus.com; linux-spi@vger.kernel.org; linux-
> kernel@vger.kernel.org; michael@walle.cc; linux-mtd@lists.infradead.org;
> nicolas.ferre@microchip.com; alexandre.belloni@bootlin.com;
> claudiu.beznea@tuxon.dev; Simek, Michal <michal.simek@amd.com>; linux-
> arm-kernel@lists.infradead.org; git (AMD-Xilinx) <git@amd.com>;
> amitrkcian2002@gmail.com
> Subject: Re: [PATCH v10 1/8] spi: Add multi-cs memories support in SPI core
> 
> On Sat, Nov 18, 2023 at 07:24:39PM +0530, Amit Kumar Mahapatra wrote:
> > AMD-Xilinx GQSPI controller has two advanced mode that allows the
> > controller to consider two flashes as one single device.
> 
> This breaks an x86 allmodconfig build:

The cause of this failure are the following patches, which neglects to 
utilize spi_get_chipselect() for retrieving the CS value. Instead, 
it directly accesses spi->chip_select.

https://lore.kernel.org/all/20230525150659.25409-14-rf@opensource.cirrus.com/
https://lore.kernel.org/all/20230216114410.183489-3-jpanis@baylibre.com/

In my upcoming series, I will address these issues.

Regards,
Amit
> 
> /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c: In function
> ‘cs35l56_hda_spi
> _probe’:
> /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:32:52: error: passing
> argumen t 2 of ‘cs35l56_hda_common_probe’ makes integer from pointer
> without a cast [-We rror=int-conversion]
>    32 |         ret = cs35l56_hda_common_probe(cs35l56, spi->chip_select);
>       |                                                 ~~~^~~~~~~~~~~~~
>       |                                                    |
>       |                                                    u8 * {aka unsigned ch
> ar *}
> In file included from /build/stage/linux/sound/pci/hda/cs35l56_hda_spi.c:12:
> /build/stage/linux/sound/pci/hda/cs35l56_hda.h:45:63: note: expected ‘int’
> but a rgument is of type ‘u8 *’ {aka ‘unsigned char *’}
>    45 | int cs35l56_hda_common_probe(struct cs35l56_hda *cs35l56, int id);
>       |                                                           ~~~~^~