* [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL @ 2022-04-19 7:52 Tianfei Zhang 2022-04-25 8:20 ` Xu Yilun 0 siblings, 1 reply; 5+ messages in thread From: Tianfei Zhang @ 2022-04-19 7:52 UTC (permalink / raw) To: hao.wu, trix, mdf, yilun.xu, linux-fpga; +Cc: Matthew Gerlach, Tianfei Zhang From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device), PORT DFLs are connected to FME DFL directly, so we don't need to search PORT DFLs via PORTn_OFFSET again. If BAR value of PORTn_OFFSET is 0x7 (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for that port. If BAR value is invalid, return -EINVAL. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> --- v2: return -EINVAL if bar number invalid. --- drivers/fpga/dfl-pci.c | 11 +++++++++++ drivers/fpga/dfl.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index 86ed9e4223d3..5bd6ef231ccc 100644 --- a/drivers/fpga/dfl-pci.c +++ b/drivers/fpga/dfl-pci.c @@ -263,6 +263,17 @@ static int find_dfls_by_default(struct pci_dev *pcidev, */ bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); + if (bar == FME_PORT_OFST_BAR_SKIP) { + dev_dbg(&pcidev->dev, "skipping search DFL for port %d on BAR %d\n", + i, bar); + continue; + } else if (bar >= PCI_STD_NUM_BARS) { + dev_err(&pcidev->dev, "bad BAR %d for port %d\n", + bar, i); + ret = -EINVAL; + break; + } + start = pci_resource_start(pcidev, bar) + offset; len = pci_resource_len(pcidev, bar) - offset; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 53572c7aced0..e0f0abfbeb8c 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -91,6 +91,7 @@ #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) #define FME_HDR_BITSTREAM_ID 0x60 #define FME_HDR_BITSTREAM_MD 0x68 +#define FME_PORT_OFST_BAR_SKIP 7 /* FME Fab Capability Register Bitfield */ #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ -- 2.26.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL 2022-04-19 7:52 [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL Tianfei Zhang @ 2022-04-25 8:20 ` Xu Yilun 2022-04-25 11:26 ` Zhang, Tianfei 2022-04-26 2:23 ` Wu, Hao 0 siblings, 2 replies; 5+ messages in thread From: Xu Yilun @ 2022-04-25 8:20 UTC (permalink / raw) To: Tianfei Zhang; +Cc: hao.wu, trix, mdf, linux-fpga, Matthew Gerlach On Tue, Apr 19, 2022 at 03:52:24AM -0400, Tianfei Zhang wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not > connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device), > PORT DFLs are connected to FME DFL directly, so we don't need to search > PORT DFLs via PORTn_OFFSET again. If BAR value of PORTn_OFFSET is 0x7 > (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for that > port. If BAR value is invalid, return -EINVAL. > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > --- > v2: return -EINVAL if bar number invalid. > --- > drivers/fpga/dfl-pci.c | 11 +++++++++++ > drivers/fpga/dfl.h | 1 + > 2 files changed, 12 insertions(+) > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c > index 86ed9e4223d3..5bd6ef231ccc 100644 > --- a/drivers/fpga/dfl-pci.c > +++ b/drivers/fpga/dfl-pci.c > @@ -263,6 +263,17 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > */ > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > + if (bar == FME_PORT_OFST_BAR_SKIP) { > + dev_dbg(&pcidev->dev, "skipping search DFL for port %d on BAR %d\n", > + i, bar); I suggest we remove the dev_dbg, it's a normal case in DFL walking. > + continue; > + } else if (bar >= PCI_STD_NUM_BARS) { > + dev_err(&pcidev->dev, "bad BAR %d for port %d\n", > + bar, i); > + ret = -EINVAL; > + break; The code is workable, but I suggest we use goto instead of break for error out. Thanks, Yilun > + } > + > start = pci_resource_start(pcidev, bar) + offset; > len = pci_resource_len(pcidev, bar) - offset; > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h > index 53572c7aced0..e0f0abfbeb8c 100644 > --- a/drivers/fpga/dfl.h > +++ b/drivers/fpga/dfl.h > @@ -91,6 +91,7 @@ > #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) > #define FME_HDR_BITSTREAM_ID 0x60 > #define FME_HDR_BITSTREAM_MD 0x68 > +#define FME_PORT_OFST_BAR_SKIP 7 > > /* FME Fab Capability Register Bitfield */ > #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ > -- > 2.26.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL 2022-04-25 8:20 ` Xu Yilun @ 2022-04-25 11:26 ` Zhang, Tianfei 2022-04-26 2:23 ` Wu, Hao 1 sibling, 0 replies; 5+ messages in thread From: Zhang, Tianfei @ 2022-04-25 11:26 UTC (permalink / raw) To: Xu, Yilun; +Cc: Wu, Hao, trix, mdf, linux-fpga, Matthew Gerlach > -----Original Message----- > From: Xu, Yilun <yilun.xu@intel.com> > Sent: Monday, April 25, 2022 4:20 PM > To: Zhang, Tianfei <tianfei.zhang@intel.com> > Cc: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; linux- > fpga@vger.kernel.org; Matthew Gerlach <matthew.gerlach@linux.intel.com> > Subject: Re: [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL > > On Tue, Apr 19, 2022 at 03:52:24AM -0400, Tianfei Zhang wrote: > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > > Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are > > not connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack > > device), PORT DFLs are connected to FME DFL directly, so we don't need > > to search PORT DFLs via PORTn_OFFSET again. If BAR value of > > PORTn_OFFSET is 0x7 > > (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for > > that port. If BAR value is invalid, return -EINVAL. > > > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > > --- > > v2: return -EINVAL if bar number invalid. > > --- > > drivers/fpga/dfl-pci.c | 11 +++++++++++ > > drivers/fpga/dfl.h | 1 + > > 2 files changed, 12 insertions(+) > > > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index > > 86ed9e4223d3..5bd6ef231ccc 100644 > > --- a/drivers/fpga/dfl-pci.c > > +++ b/drivers/fpga/dfl-pci.c > > @@ -263,6 +263,17 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > > */ > > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > > + if (bar == FME_PORT_OFST_BAR_SKIP) { > > + dev_dbg(&pcidev->dev, "skipping search DFL > for port %d on BAR %d\n", > > + i, bar); > > I suggest we remove the dev_dbg, it's a normal case in DFL walking. I agree. > > > + continue; > > + } else if (bar >= PCI_STD_NUM_BARS) { > > + dev_err(&pcidev->dev, "bad BAR %d for port > %d\n", > > + bar, i); > > + ret = -EINVAL; > > + break; > > The code is workable, but I suggest we use goto instead of break for error out. Ok, use goto is fine, I will change for next patch. > > Thanks, > Yilun > > > + } > > + > > start = pci_resource_start(pcidev, bar) + offset; > > len = pci_resource_len(pcidev, bar) - offset; > > > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index > > 53572c7aced0..e0f0abfbeb8c 100644 > > --- a/drivers/fpga/dfl.h > > +++ b/drivers/fpga/dfl.h > > @@ -91,6 +91,7 @@ > > #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) > > #define FME_HDR_BITSTREAM_ID 0x60 > > #define FME_HDR_BITSTREAM_MD 0x68 > > +#define FME_PORT_OFST_BAR_SKIP 7 > > > > /* FME Fab Capability Register Bitfield */ > > #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric > version ID */ > > -- > > 2.26.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL 2022-04-25 8:20 ` Xu Yilun 2022-04-25 11:26 ` Zhang, Tianfei @ 2022-04-26 2:23 ` Wu, Hao 2022-04-26 2:29 ` Zhang, Tianfei 1 sibling, 1 reply; 5+ messages in thread From: Wu, Hao @ 2022-04-26 2:23 UTC (permalink / raw) To: Xu, Yilun, Zhang, Tianfei; +Cc: trix, mdf, linux-fpga, Matthew Gerlach > On Tue, Apr 19, 2022 at 03:52:24AM -0400, Tianfei Zhang wrote: > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > > Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are not > > connected FME DFL. But for some cases (e.g. Intel Open FPGA Stack device), > > PORT DFLs are connected to FME DFL directly, so we don't need to search > > PORT DFLs via PORTn_OFFSET again. If BAR value of PORTn_OFFSET is 0x7 > > (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for that > > port. If BAR value is invalid, return -EINVAL. > > > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > > --- > > v2: return -EINVAL if bar number invalid. > > --- > > drivers/fpga/dfl-pci.c | 11 +++++++++++ > > drivers/fpga/dfl.h | 1 + > > 2 files changed, 12 insertions(+) > > > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c > > index 86ed9e4223d3..5bd6ef231ccc 100644 > > --- a/drivers/fpga/dfl-pci.c > > +++ b/drivers/fpga/dfl-pci.c > > @@ -263,6 +263,17 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > > */ > > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > > + if (bar == FME_PORT_OFST_BAR_SKIP) { > > + dev_dbg(&pcidev->dev, "skipping search DFL > for port %d on BAR %d\n", > > + i, bar); > > I suggest we remove the dev_dbg, it's a normal case in DFL walking. > > > + continue; > > + } else if (bar >= PCI_STD_NUM_BARS) { > > + dev_err(&pcidev->dev, "bad BAR %d for > port %d\n", > > + bar, i); > > + ret = -EINVAL; > > + break; > > The code is workable, but I suggest we use goto instead of break for > error out. Maybe "break" is better, if additional code is required after the loop in the future, we don't have to modify the goto label code again. Just my personal preference. > > Thanks, > Yilun > > > + } > > + > > start = pci_resource_start(pcidev, bar) + offset; > > len = pci_resource_len(pcidev, bar) - offset; > > > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h > > index 53572c7aced0..e0f0abfbeb8c 100644 > > --- a/drivers/fpga/dfl.h > > +++ b/drivers/fpga/dfl.h > > @@ -91,6 +91,7 @@ > > #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) > > #define FME_HDR_BITSTREAM_ID 0x60 > > #define FME_HDR_BITSTREAM_MD 0x68 > > +#define FME_PORT_OFST_BAR_SKIP 7 > > > > /* FME Fab Capability Register Bitfield */ > > #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric > version ID */ > > -- > > 2.26.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL 2022-04-26 2:23 ` Wu, Hao @ 2022-04-26 2:29 ` Zhang, Tianfei 0 siblings, 0 replies; 5+ messages in thread From: Zhang, Tianfei @ 2022-04-26 2:29 UTC (permalink / raw) To: Wu, Hao, Xu, Yilun; +Cc: trix, mdf, linux-fpga, Matthew Gerlach > -----Original Message----- > From: Wu, Hao <hao.wu@intel.com> > Sent: Tuesday, April 26, 2022 10:23 AM > To: Xu, Yilun <yilun.xu@intel.com>; Zhang, Tianfei <tianfei.zhang@intel.com> > Cc: trix@redhat.com; mdf@kernel.org; linux-fpga@vger.kernel.org; Matthew > Gerlach <matthew.gerlach@linux.intel.com> > Subject: RE: [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL > > > On Tue, Apr 19, 2022 at 03:52:24AM -0400, Tianfei Zhang wrote: > > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > > > > Currently we use PORTn_OFFSET to locate PORT DFLs, and PORT DFLs are > > > not connected FME DFL. But for some cases (e.g. Intel Open FPGA > > > Stack device), PORT DFLs are connected to FME DFL directly, so we > > > don't need to search PORT DFLs via PORTn_OFFSET again. If BAR value > > > of PORTn_OFFSET is 0x7 > > > (FME_PORT_OFST_BAR_SKIP) then driver will skip searching the DFL for > > > that port. If BAR value is invalid, return -EINVAL. > > > > > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > > > --- > > > v2: return -EINVAL if bar number invalid. > > > --- > > > drivers/fpga/dfl-pci.c | 11 +++++++++++ > > > drivers/fpga/dfl.h | 1 + > > > 2 files changed, 12 insertions(+) > > > > > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index > > > 86ed9e4223d3..5bd6ef231ccc 100644 > > > --- a/drivers/fpga/dfl-pci.c > > > +++ b/drivers/fpga/dfl-pci.c > > > @@ -263,6 +263,17 @@ static int find_dfls_by_default(struct pci_dev > *pcidev, > > > */ > > > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > > > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > > > + if (bar == FME_PORT_OFST_BAR_SKIP) { > > > + dev_dbg(&pcidev->dev, "skipping search DFL > > for port %d on BAR %d\n", > > > + i, bar); > > > > I suggest we remove the dev_dbg, it's a normal case in DFL walking. > > > > > + continue; > > > + } else if (bar >= PCI_STD_NUM_BARS) { > > > + dev_err(&pcidev->dev, "bad BAR %d for > > port %d\n", > > > + bar, i); > > > + ret = -EINVAL; > > > + break; > > > > The code is workable, but I suggest we use goto instead of break for > > error out. > > Maybe "break" is better, if additional code is required after the loop in the > future, we don't have to modify the goto label code again. Just my personal > preference. Yes, Yilun suggested here is goto is better, because this is a hardware issue, it should be handle the error immediately. > > > > > Thanks, > > Yilun > > > > > + } > > > + > > > start = pci_resource_start(pcidev, bar) + offset; > > > len = pci_resource_len(pcidev, bar) - offset; > > > > > > diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index > > > 53572c7aced0..e0f0abfbeb8c 100644 > > > --- a/drivers/fpga/dfl.h > > > +++ b/drivers/fpga/dfl.h > > > @@ -91,6 +91,7 @@ > > > #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) > > > #define FME_HDR_BITSTREAM_ID 0x60 > > > #define FME_HDR_BITSTREAM_MD 0x68 > > > +#define FME_PORT_OFST_BAR_SKIP 7 > > > > > > /* FME Fab Capability Register Bitfield */ > > > #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric > > version ID */ > > > -- > > > 2.26.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-04-26 2:31 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-19 7:52 [PATCH v2] fpga: dfl: Allow Port to be linked to FME's DFL Tianfei Zhang 2022-04-25 8:20 ` Xu Yilun 2022-04-25 11:26 ` Zhang, Tianfei 2022-04-26 2:23 ` Wu, Hao 2022-04-26 2:29 ` Zhang, Tianfei
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