* [PATCH] drm/amdgpu: change the alignment size of TMR BO to 1M
@ 2022-09-09 3:14 Yang Wang
2022-09-09 3:19 ` Zhang, Hawking
0 siblings, 1 reply; 2+ messages in thread
From: Yang Wang @ 2022-09-09 3:14 UTC (permalink / raw)
To: amd-gfx; +Cc: Yang Wang, Hawking.zhang
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index cfcaf890a6a1..5585cda8d24b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -766,7 +766,7 @@ static int psp_tmr_init(struct psp_context *psp)
}
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
- ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
+ ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, SZ_1M,
AMDGPU_GEM_DOMAIN_VRAM,
&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amdgpu: change the alignment size of TMR BO to 1M
2022-09-09 3:14 [PATCH] drm/amdgpu: change the alignment size of TMR BO to 1M Yang Wang
@ 2022-09-09 3:19 ` Zhang, Hawking
0 siblings, 0 replies; 2+ messages in thread
From: Zhang, Hawking @ 2022-09-09 3:19 UTC (permalink / raw)
To: Wang, Yang(Kevin), amd-gfx; +Cc: Wang, Yang(Kevin)
[-- Attachment #1: Type: text/plain, Size: 1465 bytes --]
[AMD Official Use Only - General]
Let’s create a new macro PSP_TMR_ALIGNMENT in case we need to support ASIC specific TMR alignment in future.
Regards,
Hawking
From: Wang, Yang(Kevin) <KevinYang.Wang@amd.com>
Date: Friday, September 9, 2022 at 11:14
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>, Wang, Yang(Kevin) <KevinYang.Wang@amd.com>
Subject: [PATCH] drm/amdgpu: change the alignment size of TMR BO to 1M
align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index cfcaf890a6a1..5585cda8d24b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -766,7 +766,7 @@ static int psp_tmr_init(struct psp_context *psp)
}
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
- ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
+ ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, SZ_1M,
AMDGPU_GEM_DOMAIN_VRAM,
&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
--
2.25.1
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^ permalink raw reply related [flat|nested] 2+ messages in thread
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