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* [V2 0/6] drm/amdgpu: add support SR-IOV initialization
@ 2016-12-02  6:03 Xiangliang Yu
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Xiangliang Yu

As SR-IOV initialization is difference from bare metal, the series patch
will change code path of initialization according to HW design.

Changes in V2:
1. Remove VM fault patch;
2. Split out the third patch into two patches to make more clear;

Xiangliang Yu (6):
  drm/amdgpu: drop redundant vi_mqd define
  drm/amd/powerplay: cut digest part
  drm/amd/powerplay: Ignore smu buffer usage
  drm/amd/powerplay: Adjust the position of data size initial
  drm/amdgpu: Don't touch GFX hw during HW fini
  drm/amd/powerplay: Fix potential NULL pointer issue

 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              | 270 +--------------------
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |   4 +-
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c |  19 +-
 3 files changed, 25 insertions(+), 268 deletions(-)

-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [V2 1/6] drm/amdgpu: drop redundant vi_mqd define
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
@ 2016-12-02  6:03   ` Xiangliang Yu
  2016-12-02  6:03   ` [V2 2/6] drm/amd/powerplay: cut digest part Xiangliang Yu
                     ` (6 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Xiangliang Yu, Monk Liu

Vi_structs.h has defined vi_mqd, drop redundant vi_mqd define.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 266 +---------------------------------
 1 file changed, 3 insertions(+), 263 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 5054f83..e1b6614 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -25,6 +25,7 @@
 #include "amdgpu.h"
 #include "amdgpu_gfx.h"
 #include "vi.h"
+#include "vi_structs.h"
 #include "vid.h"
 #include "amdgpu_ucode.h"
 #include "amdgpu_atombios.h"
@@ -4470,267 +4471,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 	return 0;
 }
 
-struct vi_mqd {
-	uint32_t header;  /* ordinal0 */
-	uint32_t compute_dispatch_initiator;  /* ordinal1 */
-	uint32_t compute_dim_x;  /* ordinal2 */
-	uint32_t compute_dim_y;  /* ordinal3 */
-	uint32_t compute_dim_z;  /* ordinal4 */
-	uint32_t compute_start_x;  /* ordinal5 */
-	uint32_t compute_start_y;  /* ordinal6 */
-	uint32_t compute_start_z;  /* ordinal7 */
-	uint32_t compute_num_thread_x;  /* ordinal8 */
-	uint32_t compute_num_thread_y;  /* ordinal9 */
-	uint32_t compute_num_thread_z;  /* ordinal10 */
-	uint32_t compute_pipelinestat_enable;  /* ordinal11 */
-	uint32_t compute_perfcount_enable;  /* ordinal12 */
-	uint32_t compute_pgm_lo;  /* ordinal13 */
-	uint32_t compute_pgm_hi;  /* ordinal14 */
-	uint32_t compute_tba_lo;  /* ordinal15 */
-	uint32_t compute_tba_hi;  /* ordinal16 */
-	uint32_t compute_tma_lo;  /* ordinal17 */
-	uint32_t compute_tma_hi;  /* ordinal18 */
-	uint32_t compute_pgm_rsrc1;  /* ordinal19 */
-	uint32_t compute_pgm_rsrc2;  /* ordinal20 */
-	uint32_t compute_vmid;  /* ordinal21 */
-	uint32_t compute_resource_limits;  /* ordinal22 */
-	uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
-	uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
-	uint32_t compute_tmpring_size;  /* ordinal25 */
-	uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
-	uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
-	uint32_t compute_restart_x;  /* ordinal28 */
-	uint32_t compute_restart_y;  /* ordinal29 */
-	uint32_t compute_restart_z;  /* ordinal30 */
-	uint32_t compute_thread_trace_enable;  /* ordinal31 */
-	uint32_t compute_misc_reserved;  /* ordinal32 */
-	uint32_t compute_dispatch_id;  /* ordinal33 */
-	uint32_t compute_threadgroup_id;  /* ordinal34 */
-	uint32_t compute_relaunch;  /* ordinal35 */
-	uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
-	uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
-	uint32_t compute_wave_restore_control;  /* ordinal38 */
-	uint32_t reserved9;  /* ordinal39 */
-	uint32_t reserved10;  /* ordinal40 */
-	uint32_t reserved11;  /* ordinal41 */
-	uint32_t reserved12;  /* ordinal42 */
-	uint32_t reserved13;  /* ordinal43 */
-	uint32_t reserved14;  /* ordinal44 */
-	uint32_t reserved15;  /* ordinal45 */
-	uint32_t reserved16;  /* ordinal46 */
-	uint32_t reserved17;  /* ordinal47 */
-	uint32_t reserved18;  /* ordinal48 */
-	uint32_t reserved19;  /* ordinal49 */
-	uint32_t reserved20;  /* ordinal50 */
-	uint32_t reserved21;  /* ordinal51 */
-	uint32_t reserved22;  /* ordinal52 */
-	uint32_t reserved23;  /* ordinal53 */
-	uint32_t reserved24;  /* ordinal54 */
-	uint32_t reserved25;  /* ordinal55 */
-	uint32_t reserved26;  /* ordinal56 */
-	uint32_t reserved27;  /* ordinal57 */
-	uint32_t reserved28;  /* ordinal58 */
-	uint32_t reserved29;  /* ordinal59 */
-	uint32_t reserved30;  /* ordinal60 */
-	uint32_t reserved31;  /* ordinal61 */
-	uint32_t reserved32;  /* ordinal62 */
-	uint32_t reserved33;  /* ordinal63 */
-	uint32_t reserved34;  /* ordinal64 */
-	uint32_t compute_user_data_0;  /* ordinal65 */
-	uint32_t compute_user_data_1;  /* ordinal66 */
-	uint32_t compute_user_data_2;  /* ordinal67 */
-	uint32_t compute_user_data_3;  /* ordinal68 */
-	uint32_t compute_user_data_4;  /* ordinal69 */
-	uint32_t compute_user_data_5;  /* ordinal70 */
-	uint32_t compute_user_data_6;  /* ordinal71 */
-	uint32_t compute_user_data_7;  /* ordinal72 */
-	uint32_t compute_user_data_8;  /* ordinal73 */
-	uint32_t compute_user_data_9;  /* ordinal74 */
-	uint32_t compute_user_data_10;  /* ordinal75 */
-	uint32_t compute_user_data_11;  /* ordinal76 */
-	uint32_t compute_user_data_12;  /* ordinal77 */
-	uint32_t compute_user_data_13;  /* ordinal78 */
-	uint32_t compute_user_data_14;  /* ordinal79 */
-	uint32_t compute_user_data_15;  /* ordinal80 */
-	uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
-	uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
-	uint32_t reserved35;  /* ordinal83 */
-	uint32_t reserved36;  /* ordinal84 */
-	uint32_t reserved37;  /* ordinal85 */
-	uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
-	uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
-	uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
-	uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
-	uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
-	uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
-	uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
-	uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
-	uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
-	uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
-	uint32_t reserved38;  /* ordinal96 */
-	uint32_t reserved39;  /* ordinal97 */
-	uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
-	uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
-	uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
-	uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
-	uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
-	uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
-	uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
-	uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
-	uint32_t reserved40;  /* ordinal106 */
-	uint32_t reserved41;  /* ordinal107 */
-	uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
-	uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
-	uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
-	uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
-	uint32_t reserved42;  /* ordinal112 */
-	uint32_t reserved43;  /* ordinal113 */
-	uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
-	uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
-	uint32_t cp_packet_id_lo;  /* ordinal116 */
-	uint32_t cp_packet_id_hi;  /* ordinal117 */
-	uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
-	uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
-	uint32_t gds_save_base_addr_lo;  /* ordinal120 */
-	uint32_t gds_save_base_addr_hi;  /* ordinal121 */
-	uint32_t gds_save_mask_lo;  /* ordinal122 */
-	uint32_t gds_save_mask_hi;  /* ordinal123 */
-	uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
-	uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
-	uint32_t reserved44;  /* ordinal126 */
-	uint32_t reserved45;  /* ordinal127 */
-	uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
-	uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
-	uint32_t cp_hqd_active;  /* ordinal130 */
-	uint32_t cp_hqd_vmid;  /* ordinal131 */
-	uint32_t cp_hqd_persistent_state;  /* ordinal132 */
-	uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
-	uint32_t cp_hqd_queue_priority;  /* ordinal134 */
-	uint32_t cp_hqd_quantum;  /* ordinal135 */
-	uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
-	uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
-	uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
-	uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
-	uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
-	uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
-	uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
-	uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
-	uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
-	uint32_t cp_hqd_pq_control;  /* ordinal145 */
-	uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
-	uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
-	uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
-	uint32_t cp_hqd_ib_control;  /* ordinal149 */
-	uint32_t cp_hqd_iq_timer;  /* ordinal150 */
-	uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
-	uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
-	uint32_t cp_hqd_dma_offload;  /* ordinal153 */
-	uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
-	uint32_t cp_hqd_msg_type;  /* ordinal155 */
-	uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
-	uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
-	uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
-	uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
-	uint32_t cp_hqd_hq_status0;  /* ordinal160 */
-	uint32_t cp_hqd_hq_control0;  /* ordinal161 */
-	uint32_t cp_mqd_control;  /* ordinal162 */
-	uint32_t cp_hqd_hq_status1;  /* ordinal163 */
-	uint32_t cp_hqd_hq_control1;  /* ordinal164 */
-	uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
-	uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
-	uint32_t cp_hqd_eop_control;  /* ordinal167 */
-	uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
-	uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
-	uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
-	uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
-	uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
-	uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
-	uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
-	uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
-	uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
-	uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
-	uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
-	uint32_t cp_hqd_error;  /* ordinal179 */
-	uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
-	uint32_t cp_hqd_eop_dones;  /* ordinal181 */
-	uint32_t reserved46;  /* ordinal182 */
-	uint32_t reserved47;  /* ordinal183 */
-	uint32_t reserved48;  /* ordinal184 */
-	uint32_t reserved49;  /* ordinal185 */
-	uint32_t reserved50;  /* ordinal186 */
-	uint32_t reserved51;  /* ordinal187 */
-	uint32_t reserved52;  /* ordinal188 */
-	uint32_t reserved53;  /* ordinal189 */
-	uint32_t reserved54;  /* ordinal190 */
-	uint32_t reserved55;  /* ordinal191 */
-	uint32_t iqtimer_pkt_header;  /* ordinal192 */
-	uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
-	uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
-	uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
-	uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
-	uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
-	uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
-	uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
-	uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
-	uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
-	uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
-	uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
-	uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
-	uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
-	uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
-	uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
-	uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
-	uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
-	uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
-	uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
-	uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
-	uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
-	uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
-	uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
-	uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
-	uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
-	uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
-	uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
-	uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
-	uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
-	uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
-	uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
-	uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
-	uint32_t reserved56;  /* ordinal225 */
-	uint32_t reserved57;  /* ordinal226 */
-	uint32_t reserved58;  /* ordinal227 */
-	uint32_t set_resources_header;  /* ordinal228 */
-	uint32_t set_resources_dw1;  /* ordinal229 */
-	uint32_t set_resources_dw2;  /* ordinal230 */
-	uint32_t set_resources_dw3;  /* ordinal231 */
-	uint32_t set_resources_dw4;  /* ordinal232 */
-	uint32_t set_resources_dw5;  /* ordinal233 */
-	uint32_t set_resources_dw6;  /* ordinal234 */
-	uint32_t set_resources_dw7;  /* ordinal235 */
-	uint32_t reserved59;  /* ordinal236 */
-	uint32_t reserved60;  /* ordinal237 */
-	uint32_t reserved61;  /* ordinal238 */
-	uint32_t reserved62;  /* ordinal239 */
-	uint32_t reserved63;  /* ordinal240 */
-	uint32_t reserved64;  /* ordinal241 */
-	uint32_t reserved65;  /* ordinal242 */
-	uint32_t reserved66;  /* ordinal243 */
-	uint32_t reserved67;  /* ordinal244 */
-	uint32_t reserved68;  /* ordinal245 */
-	uint32_t reserved69;  /* ordinal246 */
-	uint32_t reserved70;  /* ordinal247 */
-	uint32_t reserved71;  /* ordinal248 */
-	uint32_t reserved72;  /* ordinal249 */
-	uint32_t reserved73;  /* ordinal250 */
-	uint32_t reserved74;  /* ordinal251 */
-	uint32_t reserved75;  /* ordinal252 */
-	uint32_t reserved76;  /* ordinal253 */
-	uint32_t reserved77;  /* ordinal254 */
-	uint32_t reserved78;  /* ordinal255 */
-
-	uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
-};
-
 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
 {
 	int i, r;
@@ -4915,9 +4655,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
 
 		/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 		wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-		mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
+		mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
 		mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
-		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
+		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
 		WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 		       mqd->cp_hqd_pq_wptr_poll_addr_hi);
 
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [V2 2/6] drm/amd/powerplay: cut digest part
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
  2016-12-02  6:03   ` [V2 1/6] drm/amdgpu: drop redundant vi_mqd define Xiangliang Yu
@ 2016-12-02  6:03   ` Xiangliang Yu
  2016-12-02  6:03   ` [V2 3/6] drm/amd/powerplay: Ignore smu buffer usage Xiangliang Yu
                     ` (5 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Frank Min, Xiangliang Yu, Monk Liu

For virtualization, FW size need to cut its digest part.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index c9bd1cf..877445d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -372,6 +372,10 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
 		entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
 		entry->meta_data_addr_high = 0;
 		entry->meta_data_addr_low = 0;
+
+		/* digest need be excluded out */
+		if (cgs_is_virtualization_enabled(smumgr->device))
+			info.image_size -= 20;
 		entry->data_size_byte = info.image_size;
 		entry->num_register_entries = 0;
 	}
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [V2 3/6] drm/amd/powerplay: Ignore smu buffer usage
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
  2016-12-02  6:03   ` [V2 1/6] drm/amdgpu: drop redundant vi_mqd define Xiangliang Yu
  2016-12-02  6:03   ` [V2 2/6] drm/amd/powerplay: cut digest part Xiangliang Yu
@ 2016-12-02  6:03   ` Xiangliang Yu
  2016-12-02  6:03   ` [V2 4/6] drm/amd/powerplay: Adjust the position of data size initial Xiangliang Yu
                     ` (4 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Xiangliang Yu, Monk Liu

SMU buffer is used for power feature, but for virtualization, the
power is controlled by hypervisor. Ignore it.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 877445d..0754911 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -407,8 +407,14 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
 					0x0);
 
 	if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
-		smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
-		smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
+		if (!cgs_is_virtualization_enabled(smumgr->device)) {
+			smu7_send_msg_to_smc_with_parameter(smumgr,
+						PPSMC_MSG_SMU_DRAM_ADDR_HI,
+						smu_data->smu_buffer.mc_addr_high);
+			smu7_send_msg_to_smc_with_parameter(smumgr,
+						PPSMC_MSG_SMU_DRAM_ADDR_LO,
+						smu_data->smu_buffer.mc_addr_low);
+		}
 		fw_to_load = UCODE_ID_RLC_G_MASK
 			   + UCODE_ID_SDMA0_MASK
 			   + UCODE_ID_SDMA1_MASK
@@ -566,6 +572,9 @@ int smu7_init(struct pp_smumgr *smumgr)
 		(cgs_handle_t)smu_data->header_buffer.handle);
 		return -EINVAL);
 
+	if (cgs_is_virtualization_enabled(smumgr->device))
+		return 0;
+
 	smu_allocate_memory(smumgr->device,
 		smu_data->smu_buffer.data_size,
 		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [V2 4/6] drm/amd/powerplay: Adjust the position of data size initial
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
                     ` (2 preceding siblings ...)
  2016-12-02  6:03   ` [V2 3/6] drm/amd/powerplay: Ignore smu buffer usage Xiangliang Yu
@ 2016-12-02  6:03   ` Xiangliang Yu
  2016-12-02  6:03   ` [V2 5/6] drm/amdgpu: Don't touch GFX hw during HW fini Xiangliang Yu
                     ` (3 subsequent siblings)
  7 siblings, 0 replies; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Xiangliang Yu

Put the initial part close to memory allocate, it will make code
more clear.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 0754911..f49b548 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -549,7 +549,6 @@ int smu7_init(struct pp_smumgr *smumgr)
 	smu_data = (struct smu7_smumgr *)(smumgr->backend);
 	smu_data->header_buffer.data_size =
 			((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
-	smu_data->smu_buffer.data_size = 200*4096;
 
 /* Allocate FW image data structure and header buffer and
  * send the header buffer address to SMU */
@@ -575,6 +574,7 @@ int smu7_init(struct pp_smumgr *smumgr)
 	if (cgs_is_virtualization_enabled(smumgr->device))
 		return 0;
 
+	smu_data->smu_buffer.data_size = 200*4096;
 	smu_allocate_memory(smumgr->device,
 		smu_data->smu_buffer.data_size,
 		CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [V2 5/6] drm/amdgpu: Don't touch GFX hw during HW fini
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
                     ` (3 preceding siblings ...)
  2016-12-02  6:03   ` [V2 4/6] drm/amd/powerplay: Adjust the position of data size initial Xiangliang Yu
@ 2016-12-02  6:03   ` Xiangliang Yu
       [not found]     ` <1480658628-24446-6-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
  2016-12-02  6:03   ` [V2 6/6] drm/amd/powerplay: Fix potential NULL pointer issue Xiangliang Yu
                     ` (2 subsequent siblings)
  7 siblings, 1 reply; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Xiangliang Yu, shaoyunl

For SR-IOV client, driver shouldn't touch the GFX hw during HW
fini, otherwise, gfx will fail to start after rebooting guest os.

Signed-off-by: shaoyunl <Shaoyun.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e1b6614..9b8d3fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4828,6 +4828,10 @@ static int gfx_v8_0_hw_fini(void *handle)
 
 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+	if (amdgpu_sriov_vf(adev)) {
+		pr_debug("For SRIOV client, shouldn't do anything.\n");
+		return 0;
+	}
 	gfx_v8_0_cp_enable(adev, false);
 	gfx_v8_0_rlc_stop(adev);
 	gfx_v8_0_cp_compute_fini(adev);
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [V2 6/6] drm/amd/powerplay: Fix potential NULL pointer issue
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
                     ` (4 preceding siblings ...)
  2016-12-02  6:03   ` [V2 5/6] drm/amdgpu: Don't touch GFX hw during HW fini Xiangliang Yu
@ 2016-12-02  6:03   ` Xiangliang Yu
       [not found]     ` <1480658628-24446-7-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
  2016-12-02  6:15   ` [V2 0/6] drm/amdgpu: add support SR-IOV initialization Alex Deucher
  2016-12-02 10:11   ` Christian König
  7 siblings, 1 reply; 12+ messages in thread
From: Xiangliang Yu @ 2016-12-02  6:03 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Xiangliang Yu

If doesn't enable dpm, the powerplay will not allocate memory for
hw management. So, hw_init_power_state_table function will reference
NULL pointer when resetting.

Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 51a3607..c81cf14 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1004,12 +1004,12 @@ int amd_powerplay_reset(void *handle)
 	if (ret)
 		return ret;
 
-	hw_init_power_state_table(instance->hwmgr);
-
 	if ((amdgpu_dpm == 0)
 		|| cgs_is_virtualization_enabled(instance->smu_mgr->device))
 		return 0;
 
+	hw_init_power_state_table(instance->hwmgr);
+
 	if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
 		return -EINVAL;
 
-- 
2.7.4

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [V2 0/6] drm/amdgpu: add support SR-IOV initialization
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
                     ` (5 preceding siblings ...)
  2016-12-02  6:03   ` [V2 6/6] drm/amd/powerplay: Fix potential NULL pointer issue Xiangliang Yu
@ 2016-12-02  6:15   ` Alex Deucher
       [not found]     ` <CADnq5_Ous-UGJQ_EREPudQYrwMc5FznH7Q5YHh08pd2pCp-yoQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  2016-12-02 10:11   ` Christian König
  7 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2016-12-02  6:15 UTC (permalink / raw)
  To: Xiangliang Yu; +Cc: amd-gfx list

On Fri, Dec 2, 2016 at 1:03 AM, Xiangliang Yu <Xiangliang.Yu@amd.com> wrote:
> As SR-IOV initialization is difference from bare metal, the series patch
> will change code path of initialization according to HW design.
>
> Changes in V2:
> 1. Remove VM fault patch;
> 2. Split out the third patch into two patches to make more clear;
>
> Xiangliang Yu (6):
>   drm/amdgpu: drop redundant vi_mqd define
>   drm/amd/powerplay: cut digest part
>   drm/amd/powerplay: Ignore smu buffer usage
>   drm/amd/powerplay: Adjust the position of data size initial
>   drm/amdgpu: Don't touch GFX hw during HW fini
>   drm/amd/powerplay: Fix potential NULL pointer issue
>
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              | 270 +--------------------
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |   4 +-
>  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c |  19 +-
>  3 files changed, 25 insertions(+), 268 deletions(-)

Patches 1-5 are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

I didn't see patch 6, but presumably it's the same NULL pointer fix
you send out previously.

Alex
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [V2 0/6] drm/amdgpu: add support SR-IOV initialization
       [not found]     ` <CADnq5_Ous-UGJQ_EREPudQYrwMc5FznH7Q5YHh08pd2pCp-yoQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-12-02  6:30       ` Yu, Xiangliang
  0 siblings, 0 replies; 12+ messages in thread
From: Yu, Xiangliang @ 2016-12-02  6:30 UTC (permalink / raw)
  To: Alex Deucher; +Cc: amd-gfx list

> -----Original Message-----
> From: Alex Deucher [mailto:alexdeucher@gmail.com]
> Sent: Friday, December 02, 2016 2:16 PM
> To: Yu, Xiangliang <Xiangliang.Yu@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: Re: [V2 0/6] drm/amdgpu: add support SR-IOV initialization
> 
> On Fri, Dec 2, 2016 at 1:03 AM, Xiangliang Yu <Xiangliang.Yu@amd.com>
> wrote:
> > As SR-IOV initialization is difference from bare metal, the series
> > patch will change code path of initialization according to HW design.
> >
> > Changes in V2:
> > 1. Remove VM fault patch;
> > 2. Split out the third patch into two patches to make more clear;
> >
> > Xiangliang Yu (6):
> >   drm/amdgpu: drop redundant vi_mqd define
> >   drm/amd/powerplay: cut digest part
> >   drm/amd/powerplay: Ignore smu buffer usage
> >   drm/amd/powerplay: Adjust the position of data size initial
> >   drm/amdgpu: Don't touch GFX hw during HW fini
> >   drm/amd/powerplay: Fix potential NULL pointer issue
> >
> >  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              | 270 +--------------------
> >  drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |   4 +-
> >  drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c |  19 +-
> >  3 files changed, 25 insertions(+), 268 deletions(-)
> 
> Patches 1-5 are:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> 
> I didn't see patch 6, but presumably it's the same NULL pointer fix you send
> out previously.

Yes, exactly same patch
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [V2 6/6] drm/amd/powerplay: Fix potential NULL pointer issue
       [not found]     ` <1480658628-24446-7-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
@ 2016-12-02  6:53       ` Deucher, Alexander
  0 siblings, 0 replies; 12+ messages in thread
From: Deucher, Alexander @ 2016-12-02  6:53 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yu, Xiangliang

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Xiangliang Yu
> Sent: Friday, December 02, 2016 1:04 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yu, Xiangliang
> Subject: [V2 6/6] drm/amd/powerplay: Fix potential NULL pointer issue
> 
> If doesn't enable dpm, the powerplay will not allocate memory for
> hw management. So, hw_init_power_state_table function will reference
> NULL pointer when resetting.
> 
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index 51a3607..c81cf14 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1004,12 +1004,12 @@ int amd_powerplay_reset(void *handle)
>  	if (ret)
>  		return ret;
> 
> -	hw_init_power_state_table(instance->hwmgr);
> -
>  	if ((amdgpu_dpm == 0)
>  		|| cgs_is_virtualization_enabled(instance->smu_mgr-
> >device))
>  		return 0;
> 
> +	hw_init_power_state_table(instance->hwmgr);
> +
>  	if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
>  		return -EINVAL;
> 
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [V2 0/6] drm/amdgpu: add support SR-IOV initialization
       [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
                     ` (6 preceding siblings ...)
  2016-12-02  6:15   ` [V2 0/6] drm/amdgpu: add support SR-IOV initialization Alex Deucher
@ 2016-12-02 10:11   ` Christian König
  7 siblings, 0 replies; 12+ messages in thread
From: Christian König @ 2016-12-02 10:11 UTC (permalink / raw)
  To: Xiangliang Yu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

I'm not so deeply into those parts, but that seem to make sense.

So whole set is Acked-by: Christian König <christian.koenig@amd.com>.

Regards,
Christian.

Am 02.12.2016 um 07:03 schrieb Xiangliang Yu:
> As SR-IOV initialization is difference from bare metal, the series patch
> will change code path of initialization according to HW design.
>
> Changes in V2:
> 1. Remove VM fault patch;
> 2. Split out the third patch into two patches to make more clear;
>
> Xiangliang Yu (6):
>    drm/amdgpu: drop redundant vi_mqd define
>    drm/amd/powerplay: cut digest part
>    drm/amd/powerplay: Ignore smu buffer usage
>    drm/amd/powerplay: Adjust the position of data size initial
>    drm/amdgpu: Don't touch GFX hw during HW fini
>    drm/amd/powerplay: Fix potential NULL pointer issue
>
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              | 270 +--------------------
>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c      |   4 +-
>   drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c |  19 +-
>   3 files changed, 25 insertions(+), 268 deletions(-)
>

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^ permalink raw reply	[flat|nested] 12+ messages in thread

* RE: [V2 5/6] drm/amdgpu: Don't touch GFX hw during HW fini
       [not found]     ` <1480658628-24446-6-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
@ 2016-12-02 14:37       ` Liu, Monk
  0 siblings, 0 replies; 12+ messages in thread
From: Liu, Monk @ 2016-12-02 14:37 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Yu, Xiangliang, Liu, Shaoyun

Reviewed-by: monk liu

-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Xiangliang Yu
Sent: Friday, December 02, 2016 2:04 PM
To: amd-gfx@lists.freedesktop.org
Cc: Yu, Xiangliang <Xiangliang.Yu@amd.com>; Liu, Shaoyun <Shaoyun.Liu@amd.com>
Subject: [V2 5/6] drm/amdgpu: Don't touch GFX hw during HW fini

For SR-IOV client, driver shouldn't touch the GFX hw during HW fini, otherwise, gfx will fail to start after rebooting guest os.

Signed-off-by: shaoyunl <Shaoyun.Liu@amd.com>
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e1b6614..9b8d3fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4828,6 +4828,10 @@ static int gfx_v8_0_hw_fini(void *handle)
 
 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+	if (amdgpu_sriov_vf(adev)) {
+		pr_debug("For SRIOV client, shouldn't do anything.\n");
+		return 0;
+	}
 	gfx_v8_0_cp_enable(adev, false);
 	gfx_v8_0_rlc_stop(adev);
 	gfx_v8_0_cp_compute_fini(adev);
--
2.7.4

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^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2016-12-02 14:37 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-02  6:03 [V2 0/6] drm/amdgpu: add support SR-IOV initialization Xiangliang Yu
     [not found] ` <1480658628-24446-1-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-02  6:03   ` [V2 1/6] drm/amdgpu: drop redundant vi_mqd define Xiangliang Yu
2016-12-02  6:03   ` [V2 2/6] drm/amd/powerplay: cut digest part Xiangliang Yu
2016-12-02  6:03   ` [V2 3/6] drm/amd/powerplay: Ignore smu buffer usage Xiangliang Yu
2016-12-02  6:03   ` [V2 4/6] drm/amd/powerplay: Adjust the position of data size initial Xiangliang Yu
2016-12-02  6:03   ` [V2 5/6] drm/amdgpu: Don't touch GFX hw during HW fini Xiangliang Yu
     [not found]     ` <1480658628-24446-6-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-02 14:37       ` Liu, Monk
2016-12-02  6:03   ` [V2 6/6] drm/amd/powerplay: Fix potential NULL pointer issue Xiangliang Yu
     [not found]     ` <1480658628-24446-7-git-send-email-Xiangliang.Yu-5C7GfCeVMHo@public.gmane.org>
2016-12-02  6:53       ` Deucher, Alexander
2016-12-02  6:15   ` [V2 0/6] drm/amdgpu: add support SR-IOV initialization Alex Deucher
     [not found]     ` <CADnq5_Ous-UGJQ_EREPudQYrwMc5FznH7Q5YHh08pd2pCp-yoQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-12-02  6:30       ` Yu, Xiangliang
2016-12-02 10:11   ` Christian König

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