* [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port
@ 2022-02-15 12:46 Bharat Kumar Gogada
2022-02-15 12:46 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Bharat Kumar Gogada @ 2022-02-15 12:46 UTC (permalink / raw)
To: linux-pci, linux-kernel
Cc: lorenzo.pieralisi, bhelgaas, michals, Bharat Kumar Gogada
Xilinx Versal Premium series has CPM5 block which supports Root Port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
to enable and handle legacy interrupts.
Changes in v2:
- changed commit message.
Bharat Kumar Gogada (2):
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
.../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++---
drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++-
2 files changed, 72 insertions(+), 8 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-02-15 12:46 [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada @ 2022-02-15 12:46 ` Bharat Kumar Gogada 2022-03-02 15:37 ` Lorenzo Pieralisi 2022-02-15 12:46 ` [PATCH v2 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada 2022-03-02 9:37 ` [PATCH v2 0/2] Add support for Xilinx " Bharat Kumar Gogada 2 siblings, 1 reply; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-02-15 12:46 UTC (permalink / raw) To: linux-pci, linux-kernel Cc: lorenzo.pieralisi, bhelgaas, michals, Bharat Kumar Gogada Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Add support for YAML schemas documentation for Versal CPM5 Root Port driver. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> --- .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- 1 file changed, 40 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 32f4641085bc..97c7229d7f91 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -14,17 +14,21 @@ allOf: properties: compatible: - const: xlnx,versal-cpm-host-1.00 + contains: + enum: + - xlnx,versal-cpm-host-1.00 + - xlnx,versal-cpm5-host-1.00 reg: - items: - - description: Configuration space region and bridge registers. - - description: CPM system level control and status registers. + description: | + Should contain cpm_slcr, cfg registers location and length. + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. + minItems: 2 + maxItems: 3 reg-names: - items: - - const: cfg - - const: cpm_slcr + minItems: 2 + maxItems: 3 interrupts: maxItems: 1 @@ -95,4 +99,33 @@ examples: interrupt-controller; }; }; + + cpm5_pcie: pcie@fcdd0000 { + compatible = "xlnx,versal-cpm5-host-1.00"; + device_type = "pci"; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + interrupts = <0 72 4>; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_1 0>, + <0 0 0 2 &pcie_intc_1 1>, + <0 0 0 3 &pcie_intc_1 2>, + <0 0 0 4 &pcie_intc_1 3>; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; + msi-map = <0x0 &its_gic 0x0 0x10000>; + reg = <0x00 0xfcdd0000 0x00 0x1000>, + <0x06 0x00000000 0x00 0x1000000>, + <0x00 0xfce20000 0x00 0x1000000>; + reg-names = "cpm_slcr", "cfg", "cpm_csr"; + + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-02-15 12:46 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada @ 2022-03-02 15:37 ` Lorenzo Pieralisi 2022-03-03 4:36 ` Bharat Kumar Gogada 0 siblings, 1 reply; 8+ messages in thread From: Lorenzo Pieralisi @ 2022-03-02 15:37 UTC (permalink / raw) To: Bharat Kumar Gogada; +Cc: linux-pci, linux-kernel, bhelgaas, michals On Tue, Feb 15, 2022 at 06:16:05PM +0530, Bharat Kumar Gogada wrote: > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Add support for YAML schemas documentation for Versal CPM5 Root Port driver. > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > --- > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > 1 file changed, 40 insertions(+), 7 deletions(-) https://docs.kernel.org/devicetree/bindings/submitting-patches.html You have to CC the devicetree ML and DT maintainers. Thanks, Lorenzo > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index 32f4641085bc..97c7229d7f91 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -14,17 +14,21 @@ allOf: > > properties: > compatible: > - const: xlnx,versal-cpm-host-1.00 > + contains: > + enum: > + - xlnx,versal-cpm-host-1.00 > + - xlnx,versal-cpm5-host-1.00 > > reg: > - items: > - - description: Configuration space region and bridge registers. > - - description: CPM system level control and status registers. > + description: | > + Should contain cpm_slcr, cfg registers location and length. > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. > + minItems: 2 > + maxItems: 3 > > reg-names: > - items: > - - const: cfg > - - const: cpm_slcr > + minItems: 2 > + maxItems: 3 > > interrupts: > maxItems: 1 > @@ -95,4 +99,33 @@ examples: > interrupt-controller; > }; > }; > + > + cpm5_pcie: pcie@fcdd0000 { > + compatible = "xlnx,versal-cpm5-host-1.00"; > + device_type = "pci"; > + #address-cells = <3>; > + #interrupt-cells = <1>; > + #size-cells = <2>; > + interrupts = <0 72 4>; > + interrupt-parent = <&gic>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_intc_1 0>, > + <0 0 0 2 &pcie_intc_1 1>, > + <0 0 0 3 &pcie_intc_1 2>, > + <0 0 0 4 &pcie_intc_1 3>; > + bus-range = <0x00 0xff>; > + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, > + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; > + msi-map = <0x0 &its_gic 0x0 0x10000>; > + reg = <0x00 0xfcdd0000 0x00 0x1000>, > + <0x06 0x00000000 0x00 0x1000000>, > + <0x00 0xfce20000 0x00 0x1000000>; > + reg-names = "cpm_slcr", "cfg", "cpm_csr"; > + > + pcie_intc_1: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > }; > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port 2022-03-02 15:37 ` Lorenzo Pieralisi @ 2022-03-03 4:36 ` Bharat Kumar Gogada 0 siblings, 0 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-03 4:36 UTC (permalink / raw) To: Lorenzo Pieralisi; +Cc: linux-pci, linux-kernel, bhelgaas, Michal Simek, robh +Rob > -----Original Message----- > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> > Sent: Wednesday, March 2, 2022 9:07 PM > To: Bharat Kumar Gogada <bharatku@xilinx.com> > Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org; > bhelgaas@google.com; Michal Simek <michals@xilinx.com> > Subject: Re: [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 > Root Port > > On Tue, Feb 15, 2022 at 06:16:05PM +0530, Bharat Kumar Gogada wrote: > > Xilinx Versal Premium series has CPM5 block which supports Root Port > > functioning at Gen5 speed. > > > > Add support for YAML schemas documentation for Versal CPM5 Root Port > driver. > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > > --- > > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > > 1 file changed, 40 insertions(+), 7 deletions(-) > > https://docs.kernel.org/devicetree/bindings/submitting-patches.html > > You have to CC the devicetree ML and DT maintainers. > > Thanks, > Lorenzo > > > diff --git > > a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > index 32f4641085bc..97c7229d7f91 100644 > > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > > @@ -14,17 +14,21 @@ allOf: > > > > properties: > > compatible: > > - const: xlnx,versal-cpm-host-1.00 > > + contains: > > + enum: > > + - xlnx,versal-cpm-host-1.00 > > + - xlnx,versal-cpm5-host-1.00 > > > > reg: > > - items: > > - - description: Configuration space region and bridge registers. > > - - description: CPM system level control and status registers. > > + description: | > > + Should contain cpm_slcr, cfg registers location and length. > > + For xlnx,versal-cpm5-host-1.00, it should also contain cpm_csr. > > + minItems: 2 > > + maxItems: 3 > > > > reg-names: > > - items: > > - - const: cfg > > - - const: cpm_slcr > > + minItems: 2 > > + maxItems: 3 > > > > interrupts: > > maxItems: 1 > > @@ -95,4 +99,33 @@ examples: > > interrupt-controller; > > }; > > }; > > + > > + cpm5_pcie: pcie@fcdd0000 { > > + compatible = "xlnx,versal-cpm5-host-1.00"; > > + device_type = "pci"; > > + #address-cells = <3>; > > + #interrupt-cells = <1>; > > + #size-cells = <2>; > > + interrupts = <0 72 4>; > > + interrupt-parent = <&gic>; > > + interrupt-map-mask = <0 0 0 7>; > > + interrupt-map = <0 0 0 1 &pcie_intc_1 0>, > > + <0 0 0 2 &pcie_intc_1 1>, > > + <0 0 0 3 &pcie_intc_1 2>, > > + <0 0 0 4 &pcie_intc_1 3>; > > + bus-range = <0x00 0xff>; > > + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 > 0x10000000>, > > + <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 > 0x80000000>; > > + msi-map = <0x0 &its_gic 0x0 0x10000>; > > + reg = <0x00 0xfcdd0000 0x00 0x1000>, > > + <0x06 0x00000000 0x00 0x1000000>, > > + <0x00 0xfce20000 0x00 0x1000000>; > > + reg-names = "cpm_slcr", "cfg", "cpm_csr"; > > + > > + pcie_intc_1: interrupt-controller { > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + interrupt-controller; > > + }; > > + }; > > }; > > -- > > 2.17.1 > > ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port 2022-02-15 12:46 [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada 2022-02-15 12:46 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada @ 2022-02-15 12:46 ` Bharat Kumar Gogada 2022-03-02 15:33 ` Lorenzo Pieralisi 2022-03-02 9:37 ` [PATCH v2 0/2] Add support for Xilinx " Bharat Kumar Gogada 2 siblings, 1 reply; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-02-15 12:46 UTC (permalink / raw) To: linux-pci, linux-kernel Cc: lorenzo.pieralisi, bhelgaas, michals, Bharat Kumar Gogada Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has few changes with existing CPM block. - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additional register bit to enable and handle legacy interrupts. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> --- drivers/pci/controller/pcie-xilinx-cpm.c | 33 +++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c index c7cd44ed4dfc..eb69f494571a 100644 --- a/drivers/pci/controller/pcie-xilinx-cpm.c +++ b/drivers/pci/controller/pcie-xilinx-cpm.c @@ -35,6 +35,10 @@ #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) +#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 +#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 +#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) + /* Interrupt registers definitions */ #define XILINX_CPM_PCIE_INTR_LINK_DOWN 0 #define XILINX_CPM_PCIE_INTR_HOT_RESET 3 @@ -109,6 +113,7 @@ * @intx_irq: legacy interrupt number * @irq: Error interrupt number * @lock: lock protecting shared register access + * @is_cpm5: value to check cpm version */ struct xilinx_cpm_pcie { struct device *dev; @@ -120,6 +125,7 @@ struct xilinx_cpm_pcie { int intx_irq; int irq; raw_spinlock_t lock; + bool is_cpm5; }; static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) @@ -285,6 +291,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) generic_handle_domain_irq(port->cpm_domain, i); pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); + if (port->is_cpm5) { + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); + if (val) + writel_relaxed(val, + port->cpm_base + + XILINX_CPM_PCIE_IR_STATUS); + } + /* * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to * CPM SLCR block. @@ -484,6 +498,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) */ writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); + + if (port->is_cpm5) { + writel(XILINX_CPM_PCIE_IR_LOCAL, + port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); + } + /* Enable the Bridge enable bit */ pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | XILINX_CPM_PCIE_REG_RPSC_BEN, @@ -504,6 +524,9 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, struct platform_device *pdev = to_platform_device(dev); struct resource *res; + if (of_device_is_compatible(dev->of_node, "xlnx,versal-cpm5-host-1.00")) + port->is_cpm5 = true; + port->cpm_base = devm_platform_ioremap_resource_byname(pdev, "cpm_slcr"); if (IS_ERR(port->cpm_base)) @@ -518,7 +541,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, if (IS_ERR(port->cfg)) return PTR_ERR(port->cfg); - port->reg_base = port->cfg->win; + if (!port->is_cpm5) { + port->reg_base = port->cfg->win; + } else { + port->reg_base = devm_platform_ioremap_resource_byname(pdev, + "cpm_csr"); + if (IS_ERR(port->reg_base)) + return PTR_ERR(port->reg_base); + } return 0; } @@ -593,6 +623,7 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) static const struct of_device_id xilinx_cpm_pcie_of_match[] = { { .compatible = "xlnx,versal-cpm-host-1.00", }, + { .compatible = "xlnx,versal-cpm5-host-1.00", }, {} }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port 2022-02-15 12:46 ` [PATCH v2 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada @ 2022-03-02 15:33 ` Lorenzo Pieralisi 2022-03-03 9:25 ` Bharat Kumar Gogada 0 siblings, 1 reply; 8+ messages in thread From: Lorenzo Pieralisi @ 2022-03-02 15:33 UTC (permalink / raw) To: Bharat Kumar Gogada; +Cc: linux-pci, linux-kernel, bhelgaas, michals On Tue, Feb 15, 2022 at 06:16:06PM +0530, Bharat Kumar Gogada wrote: > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Xilinx Versal CPM5 has few changes with existing CPM block. > - CPM5 has dedicated register space for control and status registers. > - CPM5 legacy interrupt handling needs additional register bit > to enable and handle legacy interrupts. > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > --- > drivers/pci/controller/pcie-xilinx-cpm.c | 33 +++++++++++++++++++++++- > 1 file changed, 32 insertions(+), 1 deletion(-) Only a couple of very minor suggestions below. > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c > index c7cd44ed4dfc..eb69f494571a 100644 > --- a/drivers/pci/controller/pcie-xilinx-cpm.c > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c > @@ -35,6 +35,10 @@ > #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 > #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) > > +#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 > +#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 > +#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) > + > /* Interrupt registers definitions */ > #define XILINX_CPM_PCIE_INTR_LINK_DOWN 0 > #define XILINX_CPM_PCIE_INTR_HOT_RESET 3 > @@ -109,6 +113,7 @@ > * @intx_irq: legacy interrupt number > * @irq: Error interrupt number > * @lock: lock protecting shared register access > + * @is_cpm5: value to check cpm version > */ > struct xilinx_cpm_pcie { > struct device *dev; > @@ -120,6 +125,7 @@ struct xilinx_cpm_pcie { > int intx_irq; > int irq; > raw_spinlock_t lock; > + bool is_cpm5; > }; > > static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) > @@ -285,6 +291,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) > generic_handle_domain_irq(port->cpm_domain, i); > pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); > > + if (port->is_cpm5) { > + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); > + if (val) > + writel_relaxed(val, > + port->cpm_base + > + XILINX_CPM_PCIE_IR_STATUS); > + } > + > /* > * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to > * CPM SLCR block. > @@ -484,6 +498,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) > */ > writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, > port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); > + > + if (port->is_cpm5) { > + writel(XILINX_CPM_PCIE_IR_LOCAL, > + port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); > + } > + > /* Enable the Bridge enable bit */ > pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | > XILINX_CPM_PCIE_REG_RPSC_BEN, > @@ -504,6 +524,9 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, > struct platform_device *pdev = to_platform_device(dev); > struct resource *res; > > + if (of_device_is_compatible(dev->of_node, "xlnx,versal-cpm5-host-1.00")) > + port->is_cpm5 = true; port->is_cpm5 = of_device_is_compatible(dev->of_node, "xlnx,versal-cpm5-host-1.00"); ? > + port->is_cpm5 = true; > + > port->cpm_base = devm_platform_ioremap_resource_byname(pdev, > "cpm_slcr"); > if (IS_ERR(port->cpm_base)) > @@ -518,7 +541,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port, > if (IS_ERR(port->cfg)) > return PTR_ERR(port->cfg); > > - port->reg_base = port->cfg->win; > + if (!port->is_cpm5) { Nit: I'd keep the check as above for consistency but it is not really important: if (port->is_cpm5) ... else ... > + port->reg_base = port->cfg->win; > + } else { > + port->reg_base = devm_platform_ioremap_resource_byname(pdev, > + "cpm_csr"); > + if (IS_ERR(port->reg_base)) > + return PTR_ERR(port->reg_base); > + } > > return 0; > } > @@ -593,6 +623,7 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev) > > static const struct of_device_id xilinx_cpm_pcie_of_match[] = { > { .compatible = "xlnx,versal-cpm-host-1.00", }, > + { .compatible = "xlnx,versal-cpm5-host-1.00", }, > {} > }; > > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port 2022-03-02 15:33 ` Lorenzo Pieralisi @ 2022-03-03 9:25 ` Bharat Kumar Gogada 0 siblings, 0 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-03 9:25 UTC (permalink / raw) To: Lorenzo Pieralisi; +Cc: linux-pci, linux-kernel, bhelgaas, Michal Simek > On Tue, Feb 15, 2022 at 06:16:06PM +0530, Bharat Kumar Gogada wrote: > > Xilinx Versal Premium series has CPM5 block which supports Root Port > > functioning at Gen5 speed. > > > > Xilinx Versal CPM5 has few changes with existing CPM block. > > - CPM5 has dedicated register space for control and status registers. > > - CPM5 legacy interrupt handling needs additional register bit > > to enable and handle legacy interrupts. > > > > Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > > --- > > drivers/pci/controller/pcie-xilinx-cpm.c | 33 > > +++++++++++++++++++++++- > > 1 file changed, 32 insertions(+), 1 deletion(-) > > Only a couple of very minor suggestions below. > > > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c > > b/drivers/pci/controller/pcie-xilinx-cpm.c > > index c7cd44ed4dfc..eb69f494571a 100644 > > --- a/drivers/pci/controller/pcie-xilinx-cpm.c > > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c > > @@ -35,6 +35,10 @@ > > #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 > > #define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) > > > > +#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 > > +#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 > > +#define XILINX_CPM_PCIE_IR_LOCAL BIT(0) > > + > > /* Interrupt registers definitions */ > > #define XILINX_CPM_PCIE_INTR_LINK_DOWN 0 > > #define XILINX_CPM_PCIE_INTR_HOT_RESET 3 > > @@ -109,6 +113,7 @@ > > * @intx_irq: legacy interrupt number > > * @irq: Error interrupt number > > * @lock: lock protecting shared register access > > + * @is_cpm5: value to check cpm version > > */ > > struct xilinx_cpm_pcie { > > struct device *dev; > > @@ -120,6 +125,7 @@ struct xilinx_cpm_pcie { > > int intx_irq; > > int irq; > > raw_spinlock_t lock; > > + bool is_cpm5; > > }; > > > > static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg) @@ -285,6 > > +291,14 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) > > generic_handle_domain_irq(port->cpm_domain, i); > > pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); > > > > + if (port->is_cpm5) { > > + val = readl_relaxed(port->cpm_base + > XILINX_CPM_PCIE_IR_STATUS); > > + if (val) > > + writel_relaxed(val, > > + port->cpm_base + > > + XILINX_CPM_PCIE_IR_STATUS); > > + } > > + > > /* > > * XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to > > * CPM SLCR block. > > @@ -484,6 +498,12 @@ static void xilinx_cpm_pcie_init_port(struct > xilinx_cpm_pcie *port) > > */ > > writel(XILINX_CPM_PCIE_MISC_IR_LOCAL, > > port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE); > > + > > + if (port->is_cpm5) { > > + writel(XILINX_CPM_PCIE_IR_LOCAL, > > + port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE); > > + } > > + > > /* Enable the Bridge enable bit */ > > pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) | > > XILINX_CPM_PCIE_REG_RPSC_BEN, > > @@ -504,6 +524,9 @@ static int xilinx_cpm_pcie_parse_dt(struct > xilinx_cpm_pcie *port, > > struct platform_device *pdev = to_platform_device(dev); > > struct resource *res; > > > > + if (of_device_is_compatible(dev->of_node, "xlnx,versal-cpm5-host- > 1.00")) > > + port->is_cpm5 = true; > > port->is_cpm5 = of_device_is_compatible(dev->of_node, > "xlnx,versal-cpm5-host-1.00"); > > ? > > > + port->is_cpm5 = true; > > + > > port->cpm_base = devm_platform_ioremap_resource_byname(pdev, > > "cpm_slcr"); > > if (IS_ERR(port->cpm_base)) > > @@ -518,7 +541,14 @@ static int xilinx_cpm_pcie_parse_dt(struct > xilinx_cpm_pcie *port, > > if (IS_ERR(port->cfg)) > > return PTR_ERR(port->cfg); > > > > - port->reg_base = port->cfg->win; > > + if (!port->is_cpm5) { > > Nit: I'd keep the check as above for consistency but it is not really > important: Thanks Lorenzo, will fix these in next patch. ^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port 2022-02-15 12:46 [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada 2022-02-15 12:46 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada 2022-02-15 12:46 ` [PATCH v2 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada @ 2022-03-02 9:37 ` Bharat Kumar Gogada 2 siblings, 0 replies; 8+ messages in thread From: Bharat Kumar Gogada @ 2022-03-02 9:37 UTC (permalink / raw) To: Bharat Kumar Gogada, linux-pci, linux-kernel Cc: lorenzo.pieralisi, bhelgaas, Michal Simek Ping > -----Original Message----- > From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > Sent: Tuesday, February 15, 2022 6:16 PM > To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: lorenzo.pieralisi@arm.com; bhelgaas@google.com; Michal Simek > <michals@xilinx.com>; Bharat Kumar Gogada <bharatku@xilinx.com> > Subject: [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port > > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Xilinx Versal CPM5 has few changes with existing CPM block. > - CPM5 has dedicated register space for control and status registers. > - CPM5 legacy interrupt handling needs additonal register bit > to enable and handle legacy interrupts. > > Changes in v2: > - changed commit message. > > Bharat Kumar Gogada (2): > dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port > PCI: xilinx-cpm: Add support for Versal CPM5 Root Port > > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- > 2 files changed, 72 insertions(+), 8 deletions(-) > > -- > 2.17.1 ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-03-03 9:26 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-02-15 12:46 [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port Bharat Kumar Gogada 2022-02-15 12:46 ` [PATCH v2 1/2] dt-bindings: PCI: xilinx-cpm: Add " Bharat Kumar Gogada 2022-03-02 15:37 ` Lorenzo Pieralisi 2022-03-03 4:36 ` Bharat Kumar Gogada 2022-02-15 12:46 ` [PATCH v2 2/2] PCI: xilinx-cpm: Add support for " Bharat Kumar Gogada 2022-03-02 15:33 ` Lorenzo Pieralisi 2022-03-03 9:25 ` Bharat Kumar Gogada 2022-03-02 9:37 ` [PATCH v2 0/2] Add support for Xilinx " Bharat Kumar Gogada
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.