* [v1 0/5] Restructure Stratix10 and Agilex handoff code
@ 2021-03-15 9:43 Siew Chin Lim
2021-03-15 9:43 ` [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Siew Chin Lim
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Siew Chin Lim @ 2021-03-15 9:43 UTC (permalink / raw)
To: u-boot
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to clean up some code before enable N5X device.
This patchset restructure Stratix10 and Agilex handoff code to be
generic and to be used by all SOC64 devices.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Rename all handoff macro prefix from S10_* to SOC64* and change
all corresponding file name from *_s10 to *_soc64. Last,
change the code to use generic fundtion from wrap_handoff_soc64.c.
History:
--------
The first version of this patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
https://patchwork.ozlabs.org/project/uboot/cover/20201110064439.9683-1-elly.siew.chin.lim at intel.com/
This patchset has dependency on:
--------
1. arm: socfpga: Move Stratix10 and Agilex SPL common code
https://patchwork.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin.lim at intel.com/
Siew Chin Lim (5):
arm: socfpga: Rename Stratix10 and Agilex handoff common macros
arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
arm: socfpga: Restructure Stratix10 and Agilex handoff code
arch/arm/mach-socfpga/Makefile | 12 ++--
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 ------------
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 62 ++++++++++++++++++
.../include/mach/system_manager_soc64.h | 4 --
...system_manager_s10.c => system_manager_soc64.c} | 53 ++++++++++------
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 ++++++++++++++++++++++
arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 -----------------
...ap_pll_config_s10.c => wrap_pll_config_soc64.c} | 16 ++---
include/configs/socfpga_soc64_common.h | 4 +-
10 files changed, 187 insertions(+), 134 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h
rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} (57%)
create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c
delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c
rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} (74%)
--
2.13.0
^ permalink raw reply [flat|nested] 13+ messages in thread* [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros 2021-03-15 9:43 [v1 0/5] Restructure Stratix10 and Agilex handoff code Siew Chin Lim @ 2021-03-15 9:43 ` Siew Chin Lim 2021-03-23 8:33 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Siew Chin Lim ` (3 subsequent siblings) 4 siblings, 1 reply; 13+ messages in thread From: Siew Chin Lim @ 2021-03-15 9:43 UTC (permalink / raw) To: u-boot Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 ---------------------- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 39 ++++++++++++++++++++++ arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 18 +++++----- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 16 ++++----- include/configs/socfpga_soc64_common.h | 4 +-- 6 files changed, 59 insertions(+), 59 deletions(-) delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index 642dcbb0ac..e060e5754e 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -8,7 +8,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> -#include <asm/arch/handoff_s10.h> +#include <asm/arch/handoff_soc64.h> #include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h deleted file mode 100644 index 3e9b606ce2..0000000000 --- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> - * - */ - -#ifndef _HANDOFF_S10_H_ -#define _HANDOFF_S10_H_ - -/* - * Offset for HW handoff from Quartus tools - */ -#define S10_HANDOFF_BASE 0xFFE3F000 -#define S10_HANDOFF_MUX (S10_HANDOFF_BASE + 0x10) -#define S10_HANDOFF_IOCTL (S10_HANDOFF_BASE + 0x1A0) -#define S10_HANDOFF_FPGA (S10_HANDOFF_BASE + 0x330) -#define S10_HANODFF_DELAY (S10_HANDOFF_BASE + 0x3F0) -#define S10_HANDOFF_CLOCK (S10_HANDOFF_BASE + 0x580) -#define S10_HANDOFF_MISC (S10_HANDOFF_BASE + 0x610) -#define S10_HANDOFF_MAGIC_MUX 0x504D5558 -#define S10_HANDOFF_MAGIC_IOCTL 0x494F4354 -#define S10_HANDOFF_MAGIC_FPGA 0x46504741 -#define S10_HANDOFF_MAGIC_DELAY 0x444C4159 -#define S10_HANDOFF_MAGIC_CLOCK 0x434C4B53 -#define S10_HANDOFF_MAGIC_MISC 0x4D495343 -#define S10_HANDOFF_OFFSET_LENGTH 0x4 -#define S10_HANDOFF_OFFSET_DATA 0x10 - -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 -#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) -#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) -#else -#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc) -#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600) -#endif - -#define S10_HANDOFF_SIZE 4096 - -#endif /* _HANDOFF_S10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h new file mode 100644 index 0000000000..804715b13d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * + */ + +#ifndef _HANDOFF_SOC64_H_ +#define _HANDOFF_SOC64_H_ + +/* + * Offset for HW handoff from Quartus tools + */ +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 +#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 +#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 +#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 +#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 +#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 +#define SOC64_HANDOFF_OFFSET_LENGTH 0x4 +#define SOC64_HANDOFF_OFFSET_DATA 0x10 + +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) +#else +#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc) +#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) +#endif + +#define SOC64_HANDOFF_SIZE 4096 + +#endif /* _HANDOFF_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c index 0b497ec30c..d10fb5e454 100644 --- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c @@ -7,23 +7,23 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/handoff_s10.h> +#include <asm/arch/handoff_soc64.h> static void sysmgr_pinmux_handoff_read(void *handoff_address, const u32 **table, unsigned int *table_len) { unsigned int handoff_entry = (swab32(readl(handoff_address + - S10_HANDOFF_OFFSET_LENGTH)) - - S10_HANDOFF_OFFSET_DATA) / + SOC64_HANDOFF_OFFSET_LENGTH)) - + SOC64_HANDOFF_OFFSET_DATA) / sizeof(unsigned int); unsigned int handoff_chunk[handoff_entry], temp, i; - if (swab32(readl(S10_HANDOFF_MUX)) == S10_HANDOFF_MAGIC_MUX) { + if (swab32(readl(SOC64_HANDOFF_MUX)) == SOC64_HANDOFF_MAGIC_MUX) { /* using handoff from Quartus tools if exists */ for (i = 0; i < handoff_entry; i++) { temp = readl(handoff_address + - S10_HANDOFF_OFFSET_DATA + (i * 4)); + SOC64_HANDOFF_OFFSET_DATA + (i * 4)); handoff_chunk[i] = swab32(temp); } *table = handoff_chunk; @@ -33,24 +33,24 @@ static void sysmgr_pinmux_handoff_read(void *handoff_address, void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_MUX, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_MUX, table, table_len); } void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_IOCTL, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_IOCTL, table, table_len); } void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANDOFF_FPGA, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_FPGA, table, table_len); } void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) { - sysmgr_pinmux_handoff_read((void *)S10_HANODFF_DELAY, table, + sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_DELAY, table, table_len); } diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index 049c5711a8..6a0d6b5ead 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -7,24 +7,24 @@ #include <common.h> #include <asm/arch/clock_manager.h> #include <asm/io.h> -#include <asm/arch/handoff_s10.h> +#include <asm/arch/handoff_soc64.h> #include <asm/arch/system_manager.h> const struct cm_config * const cm_get_default_config(void) { #ifdef CONFIG_SPL_BUILD struct cm_config *cm_handoff_cfg = (struct cm_config *) - (S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA); + (SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA); u32 *conversion = (u32 *)cm_handoff_cfg; u32 i; - u32 handoff_clk = readl(S10_HANDOFF_CLOCK); + u32 handoff_clk = readl(SOC64_HANDOFF_CLOCK); - if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) { - writel(swab32(handoff_clk), S10_HANDOFF_CLOCK); + if (swab32(handoff_clk) == SOC64_HANDOFF_MAGIC_CLOCK) { + writel(swab32(handoff_clk), SOC64_HANDOFF_CLOCK); for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++) conversion[i] = swab32(conversion[i]); return cm_handoff_cfg; - } else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) { + } else if (handoff_clk == SOC64_HANDOFF_MAGIC_CLOCK) { return cm_handoff_cfg; } #endif @@ -35,7 +35,7 @@ const unsigned int cm_get_osc_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(HANDOFF_CLOCK_OSC); + u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC); writel(clock, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); @@ -52,7 +52,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(HANDOFF_CLOCK_FPGA); + u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA); writel(clock, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 1cfa190047..5afdb10454 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -8,7 +8,7 @@ #define __CONFIG_SOCFPGA_SOC64_COMMON_H__ #include <asm/arch/base_addr_s10.h> -#include <asm/arch/handoff_s10.h> +#include <asm/arch/handoff_soc64.h> #include <linux/stringify.h> /* @@ -43,7 +43,7 @@ #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + CONFIG_SYS_INIT_RAM_SIZE \ - - S10_HANDOFF_SIZE) + - SOC64_HANDOFF_SIZE) #else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE \ + 0x100000) -- 2.13.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros 2021-03-15 9:43 ` [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Siew Chin Lim @ 2021-03-23 8:33 ` Tan, Ley Foon 0 siblings, 0 replies; 13+ messages in thread From: Tan, Ley Foon @ 2021-03-23 8:33 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common > macros > > Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from > S10_HANDOFF to SOC64_HANDOFF. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > --- Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c 2021-03-15 9:43 [v1 0/5] Restructure Stratix10 and Agilex handoff code Siew Chin Lim 2021-03-15 9:43 ` [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Siew Chin Lim @ 2021-03-15 9:43 ` Siew Chin Lim 2021-03-23 9:11 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c Siew Chin Lim ` (2 subsequent siblings) 4 siblings, 1 reply; 13+ messages in thread From: Siew Chin Lim @ 2021-03-15 9:43 UTC (permalink / raw) To: u-boot Rename to common file name to used by all SOC64 devices. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- arch/arm/mach-socfpga/Makefile | 4 ++-- .../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} (100%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index e4c2da93d5..eca6fd173f 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -38,7 +38,7 @@ obj-y += reset_manager_s10.o obj-y += system_manager_s10.o obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o -obj-y += wrap_pll_config_s10.o +obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX @@ -53,7 +53,7 @@ obj-y += system_manager_s10.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_pinmux_config_s10.o -obj-y += wrap_pll_config_s10.o +obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_soc64.c similarity index 100% rename from arch/arm/mach-socfpga/wrap_pll_config_s10.c rename to arch/arm/mach-socfpga/wrap_pll_config_soc64.c -- 2.13.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c 2021-03-15 9:43 ` [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Siew Chin Lim @ 2021-03-23 9:11 ` Tan, Ley Foon 0 siblings, 0 replies; 13+ messages in thread From: Tan, Ley Foon @ 2021-03-23 9:11 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to > wrap_pll_config_soc64.c > > Rename to common file name to used by all SOC64 devices. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > --- Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c 2021-03-15 9:43 [v1 0/5] Restructure Stratix10 and Agilex handoff code Siew Chin Lim 2021-03-15 9:43 ` [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Siew Chin Lim 2021-03-15 9:43 ` [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Siew Chin Lim @ 2021-03-15 9:43 ` Siew Chin Lim 2021-03-23 9:21 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h Siew Chin Lim 2021-03-15 9:43 ` [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code Siew Chin Lim 4 siblings, 1 reply; 13+ messages in thread From: Siew Chin Lim @ 2021-03-15 9:43 UTC (permalink / raw) To: u-boot Rename to common file name to used by all SOC64 devices. No functionality change. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- arch/arm/mach-socfpga/Makefile | 4 ++-- .../arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} (100%) diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index eca6fd173f..f9dd166ab3 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -35,7 +35,7 @@ obj-y += mailbox_s10.o obj-y += misc_s10.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o -obj-y += system_manager_s10.o +obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_soc64.o @@ -49,7 +49,7 @@ obj-y += misc_s10.o obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o -obj-y += system_manager_s10.o +obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_pinmux_config_s10.o diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_soc64.c similarity index 100% rename from arch/arm/mach-socfpga/system_manager_s10.c rename to arch/arm/mach-socfpga/system_manager_soc64.c -- 2.13.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c 2021-03-15 9:43 ` [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c Siew Chin Lim @ 2021-03-23 9:21 ` Tan, Ley Foon 0 siblings, 0 replies; 13+ messages in thread From: Tan, Ley Foon @ 2021-03-23 9:21 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v1 3/5] arm: socfpga: Changed system_manager_s10.c to > system_manager_soc64.c > > Rename to common file name to used by all SOC64 devices. > No functionality change. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > --- Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h 2021-03-15 9:43 [v1 0/5] Restructure Stratix10 and Agilex handoff code Siew Chin Lim ` (2 preceding siblings ...) 2021-03-15 9:43 ` [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c Siew Chin Lim @ 2021-03-15 9:43 ` Siew Chin Lim 2021-03-23 9:22 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code Siew Chin Lim 4 siblings, 1 reply; 13+ messages in thread From: Siew Chin Lim @ 2021-03-15 9:43 UTC (permalink / raw) To: u-boot Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 804715b13d..2561255712 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2020 Intel Corporation <www.intel.com> * */ @@ -10,21 +10,25 @@ /* * Offset for HW handoff from Quartus tools */ -#define SOC64_HANDOFF_BASE 0xFFE3F000 -#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) -#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0) -#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) -#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) -#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) -#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +/* HPS handoff */ #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 + #define SOC64_HANDOFF_OFFSET_LENGTH 0x4 #define SOC64_HANDOFF_OFFSET_DATA 0x10 +#define SOC64_HANDOFF_SIZE 4096 + +#define SOC64_HANDOFF_BASE 0xFFE3F000 +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10) +#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0) +#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) +#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) +#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) @@ -34,6 +38,4 @@ #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif -#define SOC64_HANDOFF_SIZE 4096 - #endif /* _HANDOFF_SOC64_H_ */ -- 2.13.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h 2021-03-15 9:43 ` [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h Siew Chin Lim @ 2021-03-23 9:22 ` Tan, Ley Foon 0 siblings, 0 replies; 13+ messages in thread From: Tan, Ley Foon @ 2021-03-23 9:22 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v1 4/5] arm: socfpga: Rearrange sequence of macros in > handoff_soc64.h > > Rearrange sequence of macros in handoff_soc64.h without any functionality > change. In preparation for Stratix10 and Agilex handoff function restructuring. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > --- > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 > ++++++++++++---------- > 1 file changed, 12 insertions(+), 10 deletions(-) > Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code 2021-03-15 9:43 [v1 0/5] Restructure Stratix10 and Agilex handoff code Siew Chin Lim ` (3 preceding siblings ...) 2021-03-15 9:43 ` [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h Siew Chin Lim @ 2021-03-15 9:43 ` Siew Chin Lim 2021-03-23 10:03 ` Tan, Ley Foon 4 siblings, 1 reply; 13+ messages in thread From: Siew Chin Lim @ 2021-03-15 9:43 UTC (permalink / raw) To: u-boot Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, in preparation to support handoff for Diamond Mesa. Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which contains the generic function to parse the handoff data. Update system_manager_soc64.c to use generic handoff function in wrap_handoff_soc64.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> --- arch/arm/mach-socfpga/Makefile | 4 +- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++++++ .../include/mach/system_manager_soc64.h | 4 -- arch/arm/mach-socfpga/system_manager_soc64.c | 53 ++++++++++------ arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 ++++++++++++++++++++++ arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 ----------------- 6 files changed, 131 insertions(+), 80 deletions(-) create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index f9dd166ab3..5779c55621 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -37,7 +37,7 @@ obj-y += mmu-arm64_s10.o obj-y += reset_manager_s10.o obj-y += system_manager_soc64.o obj-y += timer_s10.o -obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif @@ -52,7 +52,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-y += system_manager_soc64.o obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o -obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 2561255712..f4c03688d6 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -11,6 +11,7 @@ * Offset for HW handoff from Quartus tools */ /* HPS handoff */ +#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54 #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 @@ -38,4 +39,24 @@ #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600) #endif +#define SOC64_HANDOFF_MUX_LEN 96 +#define SOC64_HANDOFF_IOCTL_LEN 96 +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#define SOC64_HANDOFF_FPGA_LEN 42 +#else +#define SOC64_HANDOFF_FPGA_LEN 40 +#endif +#define SOC64_HANDOFF_DELAY_LEN 96 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +enum endianness { + little_endian, + big_endian +}; + +int socfpga_get_handoff_size(void *handoff_address, enum endianness endian); +int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len, + enum endianness big_endian); +#endif #endif /* _HANDOFF_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 4949cae97a..1eb8e7a904 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -10,10 +10,6 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_SOC64_WDDBG 0x08 #define SYSMGR_SOC64_DMA 0x20 diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index c123cc9644..a19d3c2de9 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -5,9 +5,10 @@ */ #include <common.h> +#include <asm/arch/handoff_soc64.h> +#include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> -#include <asm/arch/system_manager.h> DECLARE_GLOBAL_DATA_PTR; @@ -64,39 +65,55 @@ void populate_sysmgr_fpgaintf_module(void) */ void populate_sysmgr_pinmux(void) { - const u32 *sys_mgr_table_u32; - unsigned int len, i; + u32 len, i; + u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX, big_endian); + u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL, big_endian); + u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA, big_endian); + u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY, big_endian); + + len = (len_mux > len_ioctl) ? len_mux : len_ioctl; + len = (len > len_fpga) ? len : len_fpga; + len = (len > len_delay) ? len : len_delay; + + u32 handoff_table[len]; /* setup the pin sel */ - sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len); + len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len, big_endian); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + - (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_PINSEL0); + writel(handoff_table[i + 1], + handoff_table[i] + + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_PINSEL0); } /* setup the pin ctrl */ - sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len); + len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len, big_endian); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + - (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IOCTRL0); + writel(handoff_table[i + 1], + handoff_table[i] + + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_IOCTRL0); } /* setup the fpga use */ - sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len); + len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len, big_endian); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + + writel(handoff_table[i + 1], + handoff_table[i] + (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA); } /* setup the IO delay */ - sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len); + len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN; + socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len, big_endian); for (i = 0; i < len; i = i + 2) { - writel(sys_mgr_table_u32[i + 1], - sys_mgr_table_u32[i] + - (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_SOC64_IODELAY0); + writel(handoff_table[i + 1], + handoff_table[i] + + (u8 *)socfpga_get_sysmgr_addr() + + SYSMGR_SOC64_IODELAY0); } } diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c new file mode 100644 index 0000000000..ba168676e9 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <asm/arch/handoff_soc64.h> +#include <asm/io.h> +#include <errno.h> +#include "log.h" + +int socfpga_get_handoff_size(void *handoff_address, enum endianness endian) +{ + u32 handoff_size; + + if (endian == little_endian) { + handoff_size = (readl(handoff_address + SOC64_HANDOFF_OFFSET_LENGTH) - + SOC64_HANDOFF_OFFSET_DATA) / + sizeof(u32); + } else if (endian == big_endian) { + handoff_size = swab32(readl(handoff_address + + SOC64_HANDOFF_OFFSET_LENGTH)); + handoff_size = (handoff_size - SOC64_HANDOFF_OFFSET_DATA) / + sizeof(u32); + } else { + return -EINVAL; + } + + debug("%s: handoff address = 0x%p handoff size = 0x%08x\n", __func__, + (u32 *)handoff_address, handoff_size); + + return handoff_size; +} + +int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len, + enum endianness big_endian) +{ + u32 temp, i; + u32 *table_x32 = table; + + debug("%s: handoff addr = 0x%p ", __func__, (u32 *)handoff_address); + + if (big_endian) { + if (swab32(readl(SOC64_HANDOFF_BASE)) == SOC64_HANDOFF_MAGIC_BOOT) { + debug("Handoff table address = 0x%p ", table_x32); + debug("table length = 0x%x\n", table_len); + debug("%s: handoff data =\n{\n", __func__); + + for (i = 0; i < table_len; i++) { + temp = readl(handoff_address + + SOC64_HANDOFF_OFFSET_DATA + + (i * sizeof(u32))); + *table_x32 = swab32(temp); + + if (!(i % 2)) + debug(" No.%d Addr 0x%08x: ", i, + *table_x32); + else + debug(" 0x%08x\n", *table_x32); + + table_x32++; + } + debug("\n}\n"); + } else { + debug("%s: Cannot find SOC64_HANDOFF_MAGIC_BOOT ", __func__); + debug("at addr 0x%p\n", (u32 *)handoff_address); + return -EPERM; + } + } + + return 0; +} diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c b/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c deleted file mode 100644 index d10fb5e454..0000000000 --- a/arch/arm/mach-socfpga/wrap_pinmux_config_s10.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> - * - */ - -#include <common.h> -#include <errno.h> -#include <asm/io.h> -#include <asm/arch/handoff_soc64.h> - -static void sysmgr_pinmux_handoff_read(void *handoff_address, - const u32 **table, - unsigned int *table_len) -{ - unsigned int handoff_entry = (swab32(readl(handoff_address + - SOC64_HANDOFF_OFFSET_LENGTH)) - - SOC64_HANDOFF_OFFSET_DATA) / - sizeof(unsigned int); - unsigned int handoff_chunk[handoff_entry], temp, i; - - if (swab32(readl(SOC64_HANDOFF_MUX)) == SOC64_HANDOFF_MAGIC_MUX) { - /* using handoff from Quartus tools if exists */ - for (i = 0; i < handoff_entry; i++) { - temp = readl(handoff_address + - SOC64_HANDOFF_OFFSET_DATA + (i * 4)); - handoff_chunk[i] = swab32(temp); - } - *table = handoff_chunk; - *table_len = ARRAY_SIZE(handoff_chunk); - } -} - -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_MUX, table, - table_len); -} - -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_IOCTL, table, - table_len); -} - -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_FPGA, table, - table_len); -} - -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len) -{ - sysmgr_pinmux_handoff_read((void *)SOC64_HANDOFF_DELAY, table, - table_len); -} -- 2.13.0 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code 2021-03-15 9:43 ` [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code Siew Chin Lim @ 2021-03-23 10:03 ` Tan, Ley Foon 2021-03-24 3:02 ` Lim, Elly Siew Chin 0 siblings, 1 reply; 13+ messages in thread From: Tan, Ley Foon @ 2021-03-23 10:03 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Monday, March 15, 2021 5:43 PM > To: u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code > > Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, > in preparation to support handoff for Diamond Mesa. > > Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which > contains the generic function to parse the handoff data. > > Update system_manager_soc64.c to use generic handoff function in > wrap_handoff_soc64.c. > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > --- > arch/arm/mach-socfpga/Makefile | 4 +- > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++++++ > .../include/mach/system_manager_soc64.h | 4 -- > arch/arm/mach-socfpga/system_manager_soc64.c | 53 ++++++++++----- > - > arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 > ++++++++++++++++++++++ > > diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > index 2561255712..f4c03688d6 100644 > --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > @@ -11,6 +11,7 @@ > * Offset for HW handoff from Quartus tools > */ > /* HPS handoff */ > +#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54 > #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 > #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 > #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 > @@ -38,4 +39,24 @@ > #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + > 0x600) > #endif > > +#define SOC64_HANDOFF_MUX_LEN 96 > +#define SOC64_HANDOFF_IOCTL_LEN 96 > +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 Can change to #if CONFIG_IS_ENABLED() > +#define SOC64_HANDOFF_FPGA_LEN 42 > +#else > +#define SOC64_HANDOFF_FPGA_LEN 40 > +#endif > +#define SOC64_HANDOFF_DELAY_LEN 96 > + > +#ifndef __ASSEMBLY__ > +#include <asm/types.h> > +enum endianness { > + little_endian, > + big_endian > +}; Uses capital letter for enum macros. > + > +int socfpga_get_handoff_size(void *handoff_address, enum endianness > +endian); int socfpga_handoff_read(void *handoff_address, void *table, > u32 table_len, > + enum endianness big_endian); > +#endif > #endif /* _HANDOFF_SOC64_H_ */ > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > index 4949cae97a..1eb8e7a904 100644 > --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > @@ -10,10 +10,6 @@ > void sysmgr_pinmux_init(void); > void populate_sysmgr_fpgaintf_module(void); > void populate_sysmgr_pinmux(void); > -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); > -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); > -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int > *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned > int *table_len); > > #define SYSMGR_SOC64_WDDBG 0x08 > #define SYSMGR_SOC64_DMA 0x20 [...] > diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c > b/arch/arm/mach-socfpga/wrap_handoff_soc64.c > new file mode 100644 > index 0000000000..ba168676e9 > --- /dev/null > +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c > @@ -0,0 +1,73 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2020 Intel Corporation <www.intel.com> > + * > + */ > + > +#include <common.h> > +#include <asm/arch/handoff_soc64.h> > +#include <asm/io.h> > +#include <errno.h> > +#include "log.h" Sort this. > + > +int socfpga_get_handoff_size(void *handoff_address, enum endianness > +endian) { > + u32 handoff_size; > + > + if (endian == little_endian) { > + handoff_size = (readl(handoff_address + > SOC64_HANDOFF_OFFSET_LENGTH) - > + SOC64_HANDOFF_OFFSET_DATA) / > + sizeof(u32); > + } else if (endian == big_endian) { > + handoff_size = swab32(readl(handoff_address + > + Can merge this, just need do additional swab32 if it is bit endian. [.....] > + > +int socfpga_handoff_read(void *handoff_address, void *table, u32 > table_len, > + enum endianness big_endian) > +{ > + u32 temp, i; > + u32 *table_x32 = table; > + > + debug("%s: handoff addr = 0x%p ", __func__, (u32 > *)handoff_address); > + > + if (big_endian) { > + if (swab32(readl(SOC64_HANDOFF_BASE)) == > SOC64_HANDOFF_MAGIC_BOOT) { > + debug("Handoff table address = 0x%p ", table_x32); > + debug("table length = 0x%x\n", table_len); > + debug("%s: handoff data =\n{\n", __func__); > + > + for (i = 0; i < table_len; i++) { > + temp = readl(handoff_address + > + SOC64_HANDOFF_OFFSET_DATA + > + (i * sizeof(u32))); > + *table_x32 = swab32(temp); > + > + if (!(i % 2)) > + debug(" No.%d Addr 0x%08x: ", i, > + *table_x32); > + else > + debug(" 0x%08x\n", *table_x32); > + > + table_x32++; > + } > + debug("\n}\n"); > + } else { > + debug("%s: Cannot find > SOC64_HANDOFF_MAGIC_BOOT ", __func__); > + debug("at addr 0x%p\n", (u32 *)handoff_address); > + return -EPERM; > + } > + } How about if it is little endian, why don't need to fill up table_x32? Regards Ley Foon ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code 2021-03-23 10:03 ` Tan, Ley Foon @ 2021-03-24 3:02 ` Lim, Elly Siew Chin 2021-03-24 4:00 ` Tan, Ley Foon 0 siblings, 1 reply; 13+ messages in thread From: Lim, Elly Siew Chin @ 2021-03-24 3:02 UTC (permalink / raw) To: u-boot Hi Ley Foon, > -----Original Message----- > From: Tan, Ley Foon <ley.foon.tan@intel.com> > Sent: Tuesday, March 23, 2021 6:04 PM > To: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>; u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; See, Chin Liang > <chin.liang.see@intel.com>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com> > Subject: RE: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff > code > > > > > -----Original Message----- > > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > > Sent: Monday, March 15, 2021 5:43 PM > > To: u-boot at lists.denx.de > > Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon > > <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>; > > Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > > <tien.fong.chee@intel.com>; Westergreen, Dalon > > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > > Yau Wai <yau.wai.gan@intel.com>; Lim, Elly Siew Chin > > <elly.siew.chin.lim@intel.com> > > Subject: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex > > handoff code > > > > Restructure Stratix10 and Agilex handoff code to used by all SOC64 > > devices, in preparation to support handoff for Diamond Mesa. > > > > Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which > > contains the generic function to parse the handoff data. > > > > Update system_manager_soc64.c to use generic handoff function in > > wrap_handoff_soc64.c. > > > > Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> > > --- > > arch/arm/mach-socfpga/Makefile | 4 +- > > arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++++++ > > .../include/mach/system_manager_soc64.h | 4 -- > > arch/arm/mach-socfpga/system_manager_soc64.c | 53 ++++++++++--- > -- > > - > > arch/arm/mach-socfpga/wrap_handoff_soc64.c | 73 > > ++++++++++++++++++++++ > > > > diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > > b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > > index 2561255712..f4c03688d6 100644 > > --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > > +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h > > @@ -11,6 +11,7 @@ > > * Offset for HW handoff from Quartus tools > > */ > > /* HPS handoff */ > > +#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54 > > #define SOC64_HANDOFF_MAGIC_MUX 0x504D5558 > > #define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354 > > #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 > > @@ -38,4 +39,24 @@ > > #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + > > 0x600) > > #endif > > > > +#define SOC64_HANDOFF_MUX_LEN 96 > > +#define SOC64_HANDOFF_IOCTL_LEN 96 > > +#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 > Can change to #if CONFIG_IS_ENABLED() > > > > +#define SOC64_HANDOFF_FPGA_LEN 42 > > +#else > > +#define SOC64_HANDOFF_FPGA_LEN 40 > > +#endif > > +#define SOC64_HANDOFF_DELAY_LEN 96 > > + > > +#ifndef __ASSEMBLY__ > > +#include <asm/types.h> > > +enum endianness { > > + little_endian, > > + big_endian > > +}; > Uses capital letter for enum macros. > > > + > > +int socfpga_get_handoff_size(void *handoff_address, enum endianness > > +endian); int socfpga_handoff_read(void *handoff_address, void *table, > > u32 table_len, > > + enum endianness big_endian); > > +#endif > > #endif /* _HANDOFF_SOC64_H_ */ > > diff --git a/arch/arm/mach- > socfpga/include/mach/system_manager_soc64.h > > b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > > index 4949cae97a..1eb8e7a904 100644 > > --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h > > @@ -10,10 +10,6 @@ > > void sysmgr_pinmux_init(void); > > void populate_sysmgr_fpgaintf_module(void); > > void populate_sysmgr_pinmux(void); > > -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int > > *table_len); -void sysmgr_pinmux_table_ctrl(const u32 **table, > > unsigned int *table_len); -void sysmgr_pinmux_table_fpga(const u32 > > **table, unsigned int *table_len); -void > > sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); > > > > #define SYSMGR_SOC64_WDDBG 0x08 > > #define SYSMGR_SOC64_DMA 0x20 > > [...] > > > diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c > > b/arch/arm/mach-socfpga/wrap_handoff_soc64.c > > new file mode 100644 > > index 0000000000..ba168676e9 > > --- /dev/null > > +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c > > @@ -0,0 +1,73 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2020 Intel Corporation <www.intel.com> > > + * > > + */ > > + > > +#include <common.h> > > +#include <asm/arch/handoff_soc64.h> > > +#include <asm/io.h> > > +#include <errno.h> > > +#include "log.h" > Sort this. > > > > + > > +int socfpga_get_handoff_size(void *handoff_address, enum endianness > > +endian) { > > + u32 handoff_size; > > + > > + if (endian == little_endian) { > > + handoff_size = (readl(handoff_address + > > SOC64_HANDOFF_OFFSET_LENGTH) - > > + SOC64_HANDOFF_OFFSET_DATA) / > > + sizeof(u32); > > + } else if (endian == big_endian) { > > + handoff_size = swab32(readl(handoff_address + > > + > Can merge this, just need do additional swab32 if it is bit endian. > > > [.....] > > > > + > > +int socfpga_handoff_read(void *handoff_address, void *table, u32 > > table_len, > > + enum endianness big_endian) > > +{ > > + u32 temp, i; > > + u32 *table_x32 = table; > > + > > + debug("%s: handoff addr = 0x%p ", __func__, (u32 > > *)handoff_address); > > + > > + if (big_endian) { > > + if (swab32(readl(SOC64_HANDOFF_BASE)) == > > SOC64_HANDOFF_MAGIC_BOOT) { > > + debug("Handoff table address = 0x%p ", table_x32); > > + debug("table length = 0x%x\n", table_len); > > + debug("%s: handoff data =\n{\n", __func__); > > + > > + for (i = 0; i < table_len; i++) { > > + temp = readl(handoff_address + > > + SOC64_HANDOFF_OFFSET_DATA + > > + (i * sizeof(u32))); > > + *table_x32 = swab32(temp); > > + > > + if (!(i % 2)) > > + debug(" No.%d Addr 0x%08x: ", i, > > + *table_x32); > > + else > > + debug(" 0x%08x\n", *table_x32); > > + > > + table_x32++; > > + } > > + debug("\n}\n"); > > + } else { > > + debug("%s: Cannot find > > SOC64_HANDOFF_MAGIC_BOOT ", __func__); > > + debug("at addr 0x%p\n", (u32 *)handoff_address); > > + return -EPERM; > > + } > > + } > How about if it is little endian, why don't need to fill up table_x32? > The little endian only needed in new Intel SOC N5X (Diamond Mesa) , we will upstream this part together with N5X patches later. And, I will update the code per comment above in next review. Thanks. > > > Regards > Ley Foon ^ permalink raw reply [flat|nested] 13+ messages in thread
* [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code 2021-03-24 3:02 ` Lim, Elly Siew Chin @ 2021-03-24 4:00 ` Tan, Ley Foon 0 siblings, 0 replies; 13+ messages in thread From: Tan, Ley Foon @ 2021-03-24 4:00 UTC (permalink / raw) To: u-boot > -----Original Message----- > From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com> > Sent: Wednesday, March 24, 2021 11:02 AM > To: Tan, Ley Foon <ley.foon.tan@intel.com>; u-boot at lists.denx.de > Cc: Marek Vasut <marex@denx.de>; See, Chin Liang > <chin.liang.see@intel.com>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong > <tien.fong.chee@intel.com>; Westergreen, Dalon > <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Gan, > Yau Wai <yau.wai.gan@intel.com> > Subject: RE: [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff > code > > Hi Ley Foon, > > > > + > > > +int socfpga_handoff_read(void *handoff_address, void *table, u32 > > > table_len, > > > + enum endianness big_endian) > > > +{ > > > + u32 temp, i; > > > + u32 *table_x32 = table; > > > + > > > + debug("%s: handoff addr = 0x%p ", __func__, (u32 > > > *)handoff_address); > > > + > > > + if (big_endian) { > > > + if (swab32(readl(SOC64_HANDOFF_BASE)) == > > > SOC64_HANDOFF_MAGIC_BOOT) { > > > + debug("Handoff table address = 0x%p ", table_x32); > > > + debug("table length = 0x%x\n", table_len); > > > + debug("%s: handoff data =\n{\n", __func__); > > > + > > > + for (i = 0; i < table_len; i++) { > > > + temp = readl(handoff_address + > > > + SOC64_HANDOFF_OFFSET_DATA + > > > + (i * sizeof(u32))); > > > + *table_x32 = swab32(temp); > > > + > > > + if (!(i % 2)) > > > + debug(" No.%d Addr 0x%08x: ", i, > > > + *table_x32); > > > + else > > > + debug(" 0x%08x\n", *table_x32); > > > + > > > + table_x32++; > > > + } > > > + debug("\n}\n"); > > > + } else { > > > + debug("%s: Cannot find > > > SOC64_HANDOFF_MAGIC_BOOT ", __func__); > > > + debug("at addr 0x%p\n", (u32 *)handoff_address); > > > + return -EPERM; > > > + } > > > + } > > How about if it is little endian, why don't need to fill up table_x32? > > > The little endian only needed in new Intel SOC N5X (Diamond Mesa) , we will > upstream this part together with N5X patches later. Then can return error if doesn't support little endian as now. ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2021-03-24 4:00 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-15 9:43 [v1 0/5] Restructure Stratix10 and Agilex handoff code Siew Chin Lim 2021-03-15 9:43 ` [v1 1/5] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Siew Chin Lim 2021-03-23 8:33 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 2/5] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Siew Chin Lim 2021-03-23 9:11 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 3/5] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c Siew Chin Lim 2021-03-23 9:21 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 4/5] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h Siew Chin Lim 2021-03-23 9:22 ` Tan, Ley Foon 2021-03-15 9:43 ` [v1 5/5] arm: socfpga: Restructure Stratix10 and Agilex handoff code Siew Chin Lim 2021-03-23 10:03 ` Tan, Ley Foon 2021-03-24 3:02 ` Lim, Elly Siew Chin 2021-03-24 4:00 ` Tan, Ley Foon
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