* [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1
@ 2022-08-08 10:31 Tim Huang
2022-08-08 10:31 ` [PATCH 2/2] drm/amdgpu: add GFX Power Gating support " Tim Huang
2022-08-08 20:12 ` [PATCH 1/2] drm/amdgpu: enable GFX Power Gating " Alex Deucher
0 siblings, 2 replies; 4+ messages in thread
From: Tim Huang @ 2022-08-08 10:31 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan1.zhang, Xiaojian.Du, Tim Huang
Enable GFX Power Gating control for GC IP v11.0.1.
Signed-off-by: Tim Huang <tim.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index e03618803a1c..319f07f61be5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -53,6 +53,7 @@
#define GFX11_MEC_HPD_SIZE 2048
#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
+#define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
#define regCGTT_WD_CLK_CTRL 0x5086
#define regCGTT_WD_CLK_CTRL_BASE_IDX 1
@@ -5279,6 +5280,38 @@ static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
.update_spm_vmid = gfx_v11_0_update_spm_vmid,
};
+static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
+{
+ u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
+
+ if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
+ data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+ else
+ data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
+
+ WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
+
+ // Program RLC_PG_DELAY3 for CGPG hysteresis
+ if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
+ switch (adev->ip_versions[GC_HWIP][0]) {
+ case IP_VERSION(11, 0, 1):
+ WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
+{
+ amdgpu_gfx_rlc_enter_safe_mode(adev);
+
+ gfx_v11_cntl_power_gating(adev, enable);
+
+ amdgpu_gfx_rlc_exit_safe_mode(adev);
+}
+
static int gfx_v11_0_set_powergating_state(void *handle,
enum amd_powergating_state state)
{
@@ -5293,6 +5326,8 @@ static int gfx_v11_0_set_powergating_state(void *handle,
case IP_VERSION(11, 0, 2):
amdgpu_gfx_off_ctrl(adev, enable);
break;
+ case IP_VERSION(11, 0, 1):
+ gfx_v11_cntl_pg(adev, enable);
default:
break;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/amdgpu: add GFX Power Gating support for GC IP v11.0.1
2022-08-08 10:31 [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1 Tim Huang
@ 2022-08-08 10:31 ` Tim Huang
2022-08-08 20:12 ` [PATCH 1/2] drm/amdgpu: enable GFX Power Gating " Alex Deucher
1 sibling, 0 replies; 4+ messages in thread
From: Tim Huang @ 2022-08-08 10:31 UTC (permalink / raw)
To: amd-gfx; +Cc: Alexander.Deucher, Yifan1.zhang, Xiaojian.Du, Tim Huang
Add AMD_PG_SUPPORT_GFX_PG support.
Signed-off-by: Tim Huang <tim.huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index b700c6cb14b4..bbbf760f8ad2 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -595,6 +595,7 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags =
+ AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_JPEG;
adev->external_rev_id = adev->rev_id + 0x1;
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1
2022-08-08 10:31 [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1 Tim Huang
2022-08-08 10:31 ` [PATCH 2/2] drm/amdgpu: add GFX Power Gating support " Tim Huang
@ 2022-08-08 20:12 ` Alex Deucher
2022-08-09 2:34 ` Huang, Tim
1 sibling, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2022-08-08 20:12 UTC (permalink / raw)
To: Tim Huang; +Cc: Alexander.Deucher, Yifan1.zhang, Xiaojian.Du, amd-gfx
On Mon, Aug 8, 2022 at 6:32 AM Tim Huang <tim.huang@amd.com> wrote:
>
> Enable GFX Power Gating control for GC IP v11.0.1.
>
> Signed-off-by: Tim Huang <tim.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 35 ++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index e03618803a1c..319f07f61be5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -53,6 +53,7 @@
> #define GFX11_MEC_HPD_SIZE 2048
>
> #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
> +#define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
>
> #define regCGTT_WD_CLK_CTRL 0x5086
> #define regCGTT_WD_CLK_CTRL_BASE_IDX 1
> @@ -5279,6 +5280,38 @@ static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
> .update_spm_vmid = gfx_v11_0_update_spm_vmid,
> };
>
> +static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
> +{
> + u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
> +
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> + else
> + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> +
> + WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
> +
> + // Program RLC_PG_DELAY3 for CGPG hysteresis
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(11, 0, 1):
> + WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
> + break;
> + default:
> + break;
> + }
> + }
> +}
> +
> +static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
> +{
> + amdgpu_gfx_rlc_enter_safe_mode(adev);
> +
> + gfx_v11_cntl_power_gating(adev, enable);
> +
> + amdgpu_gfx_rlc_exit_safe_mode(adev);
> +}
> +
> static int gfx_v11_0_set_powergating_state(void *handle,
> enum amd_powergating_state state)
> {
> @@ -5293,6 +5326,8 @@ static int gfx_v11_0_set_powergating_state(void *handle,
> case IP_VERSION(11, 0, 2):
> amdgpu_gfx_off_ctrl(adev, enable);
> break;
> + case IP_VERSION(11, 0, 1):
> + gfx_v11_cntl_pg(adev, enable);
do we need to call amdgpu_gfx_off_ctrl(adev, enable); here as well?
Alex
> default:
> break;
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1
2022-08-08 20:12 ` [PATCH 1/2] drm/amdgpu: enable GFX Power Gating " Alex Deucher
@ 2022-08-09 2:34 ` Huang, Tim
0 siblings, 0 replies; 4+ messages in thread
From: Huang, Tim @ 2022-08-09 2:34 UTC (permalink / raw)
To: Alex Deucher; +Cc: Deucher, Alexander, Zhang, Yifan, Du, Xiaojian, amd-gfx
[AMD Official Use Only - General]
Hi Alex,
Yes, we need to call amdgpu_gfx_off_ctrl(adev, enable) as well, but now the GFXOFF feature is still not ready
on the FW side. I will add some comments about this and resend this patch to avoid confusion.
Best Regards,
Tim Huang
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Tuesday, August 9, 2022 4:13 AM
To: Huang, Tim <Tim.Huang@amd.com>
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>
Subject: Re: [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1
On Mon, Aug 8, 2022 at 6:32 AM Tim Huang <tim.huang@amd.com> wrote:
>
> Enable GFX Power Gating control for GC IP v11.0.1.
>
> Signed-off-by: Tim Huang <tim.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 35
> ++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index e03618803a1c..319f07f61be5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -53,6 +53,7 @@
> #define GFX11_MEC_HPD_SIZE 2048
>
> #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
> +#define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1 0x1388
>
> #define regCGTT_WD_CLK_CTRL 0x5086
> #define regCGTT_WD_CLK_CTRL_BASE_IDX 1
> @@ -5279,6 +5280,38 @@ static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
> .update_spm_vmid = gfx_v11_0_update_spm_vmid, };
>
> +static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev,
> +bool enable) {
> + u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
> +
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
> + data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> + else
> + data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
> +
> + WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
> +
> + // Program RLC_PG_DELAY3 for CGPG hysteresis
> + if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
> + switch (adev->ip_versions[GC_HWIP][0]) {
> + case IP_VERSION(11, 0, 1):
> + WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
> + break;
> + default:
> + break;
> + }
> + }
> +}
> +
> +static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
> +{
> + amdgpu_gfx_rlc_enter_safe_mode(adev);
> +
> + gfx_v11_cntl_power_gating(adev, enable);
> +
> + amdgpu_gfx_rlc_exit_safe_mode(adev);
> +}
> +
> static int gfx_v11_0_set_powergating_state(void *handle,
> enum amd_powergating_state
> state) { @@ -5293,6 +5326,8 @@ static int
> gfx_v11_0_set_powergating_state(void *handle,
> case IP_VERSION(11, 0, 2):
> amdgpu_gfx_off_ctrl(adev, enable);
> break;
> + case IP_VERSION(11, 0, 1):
> + gfx_v11_cntl_pg(adev, enable);
do we need to call amdgpu_gfx_off_ctrl(adev, enable); here as well?
Alex
> default:
> break;
> }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-08-09 2:34 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-08-08 10:31 [PATCH 1/2] drm/amdgpu: enable GFX Power Gating for GC IP v11.0.1 Tim Huang
2022-08-08 10:31 ` [PATCH 2/2] drm/amdgpu: add GFX Power Gating support " Tim Huang
2022-08-08 20:12 ` [PATCH 1/2] drm/amdgpu: enable GFX Power Gating " Alex Deucher
2022-08-09 2:34 ` Huang, Tim
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