AST2600 support in QEMU

AST2600 support in QEMU

[Shivi Fotedar]

[-- Attachment #1: Type: text/plain, Size: 405 bytes --]

Hello, we are looking for support for few features for AST2600 in QEMU, specifically

  *   PCIe RC support so BMC can talk to downstream devices for management functions.
  *   MCTP controller to run MCTP protocol on top of PCIe or I2C.
  *   I2C slave so BMC can talk to host CPU QEMU for IPMI

Can someone let us know if there is effort going on these areas? Appreciate any help here.

Thanks

[-- Attachment #2: Type: text/html, Size: 4590 bytes --]

Re: AST2600 support in QEMU

[Joel Stanley]

Hello Shivi,

I've added others to cc who may have some input.

On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar <sfotedar@nvidia.com> wrote:
>
> Hello, we are looking for support for few features for AST2600 in QEMU, specifically
>
> PCIe RC support so BMC can talk to downstream devices for management functions.

I haven't seen any PCIe work done yet.

> MCTP controller to run MCTP protocol on top of PCIe or I2C.

What work would be required to do this on top of i2c?

> I2C slave so BMC can talk to host CPU QEMU for IPMI

Some support for slave mode was merged in v7.1.

Cheers,

Joel

Re: AST2600 support in QEMU

[Cédric Le Goater]

Hello,

On 8/10/22 04:37, Joel Stanley wrote:
> Hello Shivi,
> 
> I've added others to cc who may have some input.
> 
> On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar <sfotedar@nvidia.com> wrote:
>>
>> Hello, we are looking for support for few features for AST2600 in QEMU, specifically
>>
>> PCIe RC support so BMC can talk to downstream devices for management functions.
> 
> I haven't seen any PCIe work done yet.

I haven't either. There is clearly a need now that we are moving
away from LPC.

>> MCTP controller to run MCTP protocol on top of PCIe or I2C.
> 
> What work would be required to do this on top of i2c?

I think Jonathan and Klaus worked on this. See :

   https://lore.kernel.org/qemu-devel/20220525121422.00003a84@Huawei.com/

>> I2C slave so BMC can talk to host CPU QEMU for IPMI
>
> Some support for slave mode was merged in v7.1.

yes.

Peter D. experimented with IPMI. See :

   https://lore.kernel.org/qemu-devel/20220630045133.32251-14-me@pjd.dev/

We also merged a new machine including a BMC ast2600 running OpenBMC
and an ast1030 SoC running OpenBIC. Work to interconnect them on the
same I2C bus is in progress.

Thanks,

C.

RE: AST2600 support in QEMU

[Shivi Fotedar]

Cedric, Joel

Thanks so much for the pointers. This definitely helps. We will get back to you with any further questions once we have looked them over. 

-----Original Message-----
From: Cédric Le Goater <clg@kaod.org> 
Sent: Tuesday, August 9, 2022 10:50 PM
To: Joel Stanley <joel@jms.id.au>; Shivi Fotedar <sfotedar@nvidia.com>; Peter Delevoryas <peter@pjd.dev>; Jeremy Kerr <jk@ozlabs.org>; Klaus Jensen <its@irrelevant.dk>; Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: qemu-devel@nongnu.org; Andrew Jeffery <andrew@aj.id.au>; Amit Kumar (Engrg-SW) <asinghal@nvidia.com>; Prasanna Karmalkar <pkarmalkar@nvidia.com>; Tim Chen (SW-GPU) <timch@nvidia.com>; Newton Liu <newtonl@nvidia.com>; Deepak Kodihalli <dkodihalli@nvidia.com>; qemu-arm <qemu-arm@nongnu.org>
Subject: Re: AST2600 support in QEMU

External email: Use caution opening links or attachments


Hello,

On 8/10/22 04:37, Joel Stanley wrote:
> Hello Shivi,
>
> I've added others to cc who may have some input.
>
> On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar <sfotedar@nvidia.com> wrote:
>>
>> Hello, we are looking for support for few features for AST2600 in 
>> QEMU, specifically
>>
>> PCIe RC support so BMC can talk to downstream devices for management functions.
>
> I haven't seen any PCIe work done yet.

I haven't either. There is clearly a need now that we are moving away from LPC.

>> MCTP controller to run MCTP protocol on top of PCIe or I2C.
>
> What work would be required to do this on top of i2c?

I think Jonathan and Klaus worked on this. See :

   https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F20220525121422.00003a84%40Huawei.com%2F&amp;data=05%7C01%7Csfotedar%40nvidia.com%7C09cd2aefa2a24815b86e08da7a94370d%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C637957074871711009%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=Z0jZN8QEjZIk1zxgfr37NOt%2BNp4q6bDRkxO8KI4Clrw%3D&amp;reserved=0

>> I2C slave so BMC can talk to host CPU QEMU for IPMI
>
> Some support for slave mode was merged in v7.1.

yes.

Peter D. experimented with IPMI. See :

   https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fqemu-devel%2F20220630045133.32251-14-me%40pjd.dev%2F&amp;data=05%7C01%7Csfotedar%40nvidia.com%7C09cd2aefa2a24815b86e08da7a94370d%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C637957074871711009%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=a4bP1xJGC25Dp9UkYKU5i%2BODLQrpfgLN%2BaQPkK9LRZc%3D&amp;reserved=0

We also merged a new machine including a BMC ast2600 running OpenBMC and an ast1030 SoC running OpenBIC. Work to interconnect them on the same I2C bus is in progress.

Thanks,

C.

Re: AST2600 support in QEMU

[Joel Stanley]

On Wed, 10 Aug 2022 at 19:12, Shivi Fotedar <sfotedar@nvidia.com> wrote:
>
> Cedric, Joel
>
> Thanks so much for the pointers. This definitely helps. We will get back to you with any further questions once we have looked them over.

Great! We look forward to your contributions. I am particularly
interested in reviewing your PCIe changes.

Cheers,

Joel

Re: AST2600 support in QEMU

[Dan Zhang]

On Tue, Aug 9, 2022 at 10:51 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> Hello,
>
> On 8/10/22 04:37, Joel Stanley wrote:
> > Hello Shivi,
> >
> > I've added others to cc who may have some input.
> >
> > On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar <sfotedar@nvidia.com> wrote:
> >>
> >> Hello, we are looking for support for few features for AST2600 in QEMU, specifically
> >>
> >> PCIe RC support so BMC can talk to downstream devices for management functions.
Normally the RC is the host CPU, BMC and the devices to be managed,
which support MCTP-over-PCIe will be the endpoint (downstream) device
as BMC.  The MCTP message Peer transaction between BMC and managed
device will using route-by-Id to RC(host) then down to endpoint.  I am
referring to DMTF DSP0238 spec. section 6.4

So what does the "PCIe RC support" means? the BMC will be the PCIe RC?
or BMC will be PCIe-Endpoint connect to host PCIe RC.

> >
> > I haven't seen any PCIe work done yet.
>
> I haven't either. There is clearly a need now that we are moving
> away from LPC.
>
> >> MCTP controller to run MCTP protocol on top of PCIe or I2C.
> >
> > What work would be required to do this on top of i2c?
>
> I think Jonathan and Klaus worked on this. See :
>
>    https://lore.kernel.org/qemu-devel/20220525121422.00003a84@Huawei.com/
>
> >> I2C slave so BMC can talk to host CPU QEMU for IPMI
> >
> > Some support for slave mode was merged in v7.1.
>
> yes.
>
> Peter D. experimented with IPMI. See :
>
>    https://lore.kernel.org/qemu-devel/20220630045133.32251-14-me@pjd.dev/
>
> We also merged a new machine including a BMC ast2600 running OpenBMC
> and an ast1030 SoC running OpenBIC. Work to interconnect them on the
> same I2C bus is in progress.
>
> Thanks,
>
> C.
>

RE: AST2600 support in QEMU

[Amit Kumar (Engrg-SW)]

Hi Dan,

Responding on behalf of Shivi.

>> "So what does the "PCIe RC support" means? the BMC will be the PCIe RC?"
Yes, BMC will be the PCIe RC to control downstream PCIe devices (end-points).

- Amit

-----Original Message-----
From: Dan Zhang <dz4list@gmail.com> 
Sent: 15 August 2022 11:18
To: Cédric Le Goater <clg@kaod.org>
Cc: Joel Stanley <joel@jms.id.au>; Shivi Fotedar <sfotedar@nvidia.com>; Peter Delevoryas <peter@pjd.dev>; Jeremy Kerr <jk@ozlabs.org>; Klaus Jensen <its@irrelevant.dk>; Jonathan Cameron <jonathan.cameron@huawei.com>; qemu-devel@nongnu.org; Andrew Jeffery <andrew@aj.id.au>; Amit Kumar (Engrg-SW) <asinghal@nvidia.com>; Prasanna Karmalkar <pkarmalkar@nvidia.com>; Tim Chen (SW-GPU) <timch@nvidia.com>; Newton Liu <newtonl@nvidia.com>; Deepak Kodihalli <dkodihalli@nvidia.com>; qemu-arm <qemu-arm@nongnu.org>
Subject: Re: AST2600 support in QEMU

External email: Use caution opening links or attachments


On Tue, Aug 9, 2022 at 10:51 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> Hello,
>
> On 8/10/22 04:37, Joel Stanley wrote:
> > Hello Shivi,
> >
> > I've added others to cc who may have some input.
> >
> > On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar <sfotedar@nvidia.com> wrote:
> >>
> >> Hello, we are looking for support for few features for AST2600 in 
> >> QEMU, specifically
> >>
> >> PCIe RC support so BMC can talk to downstream devices for management functions.
Normally the RC is the host CPU, BMC and the devices to be managed, which support MCTP-over-PCIe will be the endpoint (downstream) device as BMC.  The MCTP message Peer transaction between BMC and managed device will using route-by-Id to RC(host) then down to endpoint.  I am referring to DMTF DSP0238 spec. section 6.4

So what does the "PCIe RC support" means? the BMC will be the PCIe RC?
or BMC will be PCIe-Endpoint connect to host PCIe RC.

> >
> > I haven't seen any PCIe work done yet.
>
> I haven't either. There is clearly a need now that we are moving away 
> from LPC.
>
> >> MCTP controller to run MCTP protocol on top of PCIe or I2C.
> >
> > What work would be required to do this on top of i2c?
>
> I think Jonathan and Klaus worked on this. See :
>
>    
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> .kernel.org%2Fqemu-devel%2F20220525121422.00003a84%40Huawei.com%2F&amp
> ;data=05%7C01%7Casinghal%40nvidia.com%7C714d293de2ac4b7f5f9308da7e81b2
> 7b%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C637961392786299602%7CU
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha
> WwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=9I35YQPk86Tjza6fa0jFVnLGCM
> SZ7ioTHpJEQN5c%2F1g%3D&amp;reserved=0
>
> >> I2C slave so BMC can talk to host CPU QEMU for IPMI
> >
> > Some support for slave mode was merged in v7.1.
>
> yes.
>
> Peter D. experimented with IPMI. See :
>
>    
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> .kernel.org%2Fqemu-devel%2F20220630045133.32251-14-me%40pjd.dev%2F&amp
> ;data=05%7C01%7Casinghal%40nvidia.com%7C714d293de2ac4b7f5f9308da7e81b2
> 7b%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C637961392786299602%7CU
> nknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1ha
> WwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&amp;sdata=HwFjdPHcM4MocoDz8hrZatYJiz
> gmDePy24KFivENpeU%3D&amp;reserved=0
>
> We also merged a new machine including a BMC ast2600 running OpenBMC 
> and an ast1030 SoC running OpenBIC. Work to interconnect them on the 
> same I2C bus is in progress.
>
> Thanks,
>
> C.
>