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* [PATCH v2] ARC: mm: Update ARC_REG_*C_PTAG on each cacheline operation
@ 2021-12-14 12:18 Barbaros Tokaoglu
  2021-12-14 12:42 ` Vladimir Isaev
  0 siblings, 1 reply; 3+ messages in thread
From: Barbaros Tokaoglu @ 2021-12-14 12:18 UTC (permalink / raw)
  To: Vineet Gupta, Vladimir Isaev, linux-snps-arc; +Cc: Miika Keskinen

For 16 kB data cache with 4 ways and 32 byte cache lines we have tag LSB
[(128 locations for each way: 7 bits) + byte offset (32 bytes: 5 bits)]
lower than page offset (13 bits for 8 kB pages).
So it is possible for PTAG to change even for single page loop. Hence 
update ARC_REG_*C_PTAG register on each cacheline iteration.

Signed-off-by: Barbaros Tokaoglu <btokaoglu@airspan.com>
---
  arch/arc/mm/cache.c | 13 ++-----------
  1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 8aa1231..d0875a8 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -251,13 +251,6 @@ void __cache_line_loop_v3(phys_addr_t paddr, 
unsigned long vaddr,
  	num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);

  	/*
-	 * MMUv3, cache ops require paddr in PTAG reg
-	 * if V-P const for loop, PTAG can be written once outside loop
-	 */
-	if (full_page)
-		write_aux_reg(aux_tag, paddr);
-
-	/*
  	 * This is technically for MMU v4, using the MMU v3 programming model
  	 * Special work for HS38 aliasing I-cache configuration with PAE40
  	 *   - upper 8 bits of paddr need to be written into PTAG_HI
@@ -268,10 +261,8 @@ void __cache_line_loop_v3(phys_addr_t paddr, 
unsigned long vaddr,
  		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);

  	while (num_lines-- > 0) {
-		if (!full_page) {
-			write_aux_reg(aux_tag, paddr);
-			paddr += L1_CACHE_BYTES;
-		}
+		write_aux_reg(aux_tag, paddr);
+		paddr += L1_CACHE_BYTES;

  		write_aux_reg(aux_cmd, vaddr);
  		vaddr += L1_CACHE_BYTES;
-- 
2.7.4
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^ permalink raw reply related	[flat|nested] 3+ messages in thread
* RE: [PATCH v2] ARC: mm: Update ARC_REG_*C_PTAG on each cacheline operation
  2021-12-14 12:18 [PATCH v2] ARC: mm: Update ARC_REG_*C_PTAG on each cacheline operation Barbaros Tokaoglu
@ 2021-12-14 12:42 ` Vladimir Isaev
  2021-12-15 14:15   ` Barbaros Tokaoglu
  0 siblings, 1 reply; 3+ messages in thread
From: Vladimir Isaev @ 2021-12-14 12:42 UTC (permalink / raw)
  To: Barbaros Tokaoglu, Vineet Gupta, linux-snps-arc; +Cc: Miika Keskinen

On Dec 14, 2021 3:18 PM, Barbaros Tokaoglu <btokaoglu@airspan.com> wrote:
> For 16 kB data cache with 4 ways and 32 byte cache lines we have tag LSB
> [(128 locations for each way: 7 bits) + byte offset (32 bytes: 5 bits)]
> lower than page offset (13 bits for 8 kB pages).
> So it is possible for PTAG to change even for single page loop. Hence
> update ARC_REG_*C_PTAG register on each cacheline iteration.
> 
> Signed-off-by: Barbaros Tokaoglu <btokaoglu@airspan.com>
> ---
>   arch/arc/mm/cache.c | 13 ++-----------
>   1 file changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
> index 8aa1231..d0875a8 100644
> --- a/arch/arc/mm/cache.c
> +++ b/arch/arc/mm/cache.c
> @@ -251,13 +251,6 @@ void __cache_line_loop_v3(phys_addr_t paddr,
> unsigned long vaddr,
>   	num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
> 
>   	/*
> -	 * MMUv3, cache ops require paddr in PTAG reg
> -	 * if V-P const for loop, PTAG can be written once outside loop
> -	 */
> -	if (full_page)
> -		write_aux_reg(aux_tag, paddr);
> -
> -	/*
>   	 * This is technically for MMU v4, using the MMU v3 programming
> model
>   	 * Special work for HS38 aliasing I-cache configuration with PAE40
>   	 *   - upper 8 bits of paddr need to be written into PTAG_HI
> @@ -268,10 +261,8 @@ void __cache_line_loop_v3(phys_addr_t paddr,
> unsigned long vaddr,
>   		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
> 
>   	while (num_lines-- > 0) {
> -		if (!full_page) {
> -			write_aux_reg(aux_tag, paddr);
> -			paddr += L1_CACHE_BYTES;
> -		}
> +		write_aux_reg(aux_tag, paddr);
> +		paddr += L1_CACHE_BYTES;
> 
>   		write_aux_reg(aux_cmd, vaddr);
>   		vaddr += L1_CACHE_BYTES;
> --
> 2.7.4

Acked-by: Vladimir Isaev <isaev@synopsys.com>

Thank you,
Vladimir Isaev
_______________________________________________
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH v2] ARC: mm: Update ARC_REG_*C_PTAG on each cacheline operation
  2021-12-14 12:42 ` Vladimir Isaev
@ 2021-12-15 14:15   ` Barbaros Tokaoglu
  0 siblings, 0 replies; 3+ messages in thread
From: Barbaros Tokaoglu @ 2021-12-15 14:15 UTC (permalink / raw)
  To: Vladimir Isaev, Vineet Gupta, linux-snps-arc; +Cc: Miika Keskinen

On 12/14/21 3:42 PM, Vladimir Isaev wrote:
> On Dec 14, 2021 3:18 PM, Barbaros Tokaoglu <btokaoglu@airspan.com> wrote:
>> For 16 kB data cache with 4 ways and 32 byte cache lines we have tag LSB
>> [(128 locations for each way: 7 bits) + byte offset (32 bytes: 5 bits)]
>> lower than page offset (13 bits for 8 kB pages).
>> So it is possible for PTAG to change even for single page loop. Hence
>> update ARC_REG_*C_PTAG register on each cacheline iteration.
>>
>> Signed-off-by: Barbaros Tokaoglu <btokaoglu@airspan.com>
>> ---
>>    arch/arc/mm/cache.c | 13 ++-----------
>>    1 file changed, 2 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
>> index 8aa1231..d0875a8 100644
>> --- a/arch/arc/mm/cache.c
>> +++ b/arch/arc/mm/cache.c
>> @@ -251,13 +251,6 @@ void __cache_line_loop_v3(phys_addr_t paddr,
>> unsigned long vaddr,
>>    	num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
>>
>>    	/*
>> -	 * MMUv3, cache ops require paddr in PTAG reg
>> -	 * if V-P const for loop, PTAG can be written once outside loop
>> -	 */
>> -	if (full_page)
>> -		write_aux_reg(aux_tag, paddr);
>> -
>> -	/*
>>    	 * This is technically for MMU v4, using the MMU v3 programming
>> model
>>    	 * Special work for HS38 aliasing I-cache configuration with PAE40
>>    	 *   - upper 8 bits of paddr need to be written into PTAG_HI
>> @@ -268,10 +261,8 @@ void __cache_line_loop_v3(phys_addr_t paddr,
>> unsigned long vaddr,
>>    		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
>>
>>    	while (num_lines-- > 0) {
>> -		if (!full_page) {
>> -			write_aux_reg(aux_tag, paddr);
>> -			paddr += L1_CACHE_BYTES;
>> -		}
>> +		write_aux_reg(aux_tag, paddr);
>> +		paddr += L1_CACHE_BYTES;
>>
>>    		write_aux_reg(aux_cmd, vaddr);
>>    		vaddr += L1_CACHE_BYTES;
>> --
>> 2.7.4
> 
> Acked-by: Vladimir Isaev <isaev@synopsys.com>
> 
> Thank you,
> Vladimir Isaev
> 
Please consider v3, there was an issue with patch of v2. Sorry for this.

Best Regards,
Barbaros
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linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-12-15 14:16 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-14 12:18 [PATCH v2] ARC: mm: Update ARC_REG_*C_PTAG on each cacheline operation Barbaros Tokaoglu
2021-12-14 12:42 ` Vladimir Isaev
2021-12-15 14:15   ` Barbaros Tokaoglu

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