From: Yash Shah <yash.shah@openfive.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>, "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>, "linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>, "linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>, linux-kernel <linux-kernel@vger.kernel.org>, linux-riscv <linux-riscv@lists.infradead.org>, devicetree <devicetree@vger.kernel.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>, "broonie@kernel.org" <broonie@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Albert Ou <aou@eecs.berkeley.edu>, "lee.jones@linaro.org" <lee.jones@linaro.org>, "u.kleine-koenig@pengutronix.de" <u.kleine-koenig@pengutronix.de>, Thierry Reding <thierry.reding@gmail.com>, "andrew@lunn.ch" <andrew@lunn.ch>, Peter Korsgaard <peter@korsgaard.com>, "Paul Walmsley ( Sifive)" <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Rob Herring <robh+dt@kernel.org>, Bartosz Golaszewski <bgolaszewski@baylibre.com>, Linus Walleij <linus.walleij@linaro.org> Subject: RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC Date: Wed, 16 Dec 2020 06:12:30 +0000 [thread overview] Message-ID: <BY5PR13MB4453C2D078F13E60DAE356B982C50@BY5PR13MB4453.namprd13.prod.outlook.com> (raw) In-Reply-To: <CAEUhbmWrCpKraUpijggkiNXa40OAnN9YJF1iFWnrnrhJZN1joA@mail.gmail.com> > -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 16 December 2020 11:36 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > Hi Yash, > > On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> > wrote: > > > > > -----Original Message----- > > > From: Bin Meng <bmeng.cn@gmail.com> > > > Sent: 10 December 2020 19:05 > > > To: Yash Shah <yash.shah@openfive.com> > > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > > kernel@vger.kernel.org>; linux-riscv > > > <linux-riscv@lists.infradead.org>; > > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM > > > <linux- gpio@vger.kernel.org>; broonie@kernel.org; Greg > > > Kroah-Hartman <gregkh@linuxfoundation.org>; Albert Ou > > > <aou@eecs.berkeley.edu>; lee.jones@linaro.org; > > > u.kleine-koenig@pengutronix.de; Thierry Reding > > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > Rob > > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > > <bgolaszewski@baylibre.com>; Linus Walleij > > > <linus.walleij@linaro.org> > > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the > > > SiFive FU740- > > > C000 SoC > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> > wrote: > > > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is > > > > built > > > > > > FU740-C000 Soc > > > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > > > This file is expected to grow as more device drivers are added to > > > > the kernel. > > > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > > --- > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > > +++++++++++++++++++++++++++++ > > > > 1 file changed, 293 insertions(+) create mode 100644 > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > new file mode 100644 > > > > index 0000000..eeb4f8c3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > @@ -0,0 +1,293 @@ > > > > ... > > > > > > + plic0: interrupt-controller@c000000 { > > > > + #interrupt-cells = <1>; > > > > + #address-cells = <0>; > > > > + compatible = "sifive,fu540-c000-plic", > > > > + "sifive,plic-1.0.0"; > > > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > > > That's because it is not required. There won't be any difference in driver > code for FU740 plic. > > Are there any driver changes for the drivers that have an updated > fu640-c000-* bindings? I don't see them in the linux-riscv list. Yes, they will be posted soon. - Yash > > > > > ... > > > > > > + eth0: ethernet@10090000 { > > > > + compatible = "sifive,fu540-c000-gem"; > > > > > > "sifive,fu740-c000-gem"? > > > > > > > Same reason as above. > > > > Thanks for your review. > > Regards, > Bin
WARNING: multiple messages have this Message-ID (diff)
From: Yash Shah <yash.shah@openfive.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: "linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>, Peter Korsgaard <peter@korsgaard.com>, Albert Ou <aou@eecs.berkeley.edu>, devicetree <devicetree@vger.kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Bartosz Golaszewski <bgolaszewski@baylibre.com>, "Paul Walmsley \( Sifive\)" <paul.walmsley@sifive.com>, linux-kernel <linux-kernel@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, "linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>, "andrew@lunn.ch" <andrew@lunn.ch>, "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>, "broonie@kernel.org" <broonie@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, "linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>, "linux-serial@vger.kernel.org" <linux-serial@vger.kernel.org>, "u.kleine-koenig@pengutronix.de" <u.kleine-koenig@pengutronix.de>, Palmer Dabbelt <palmer@dabbelt.com>, linux-riscv <linux-riscv@lists.infradead.org>, "lee.jones@linaro.org" <lee.jones@linaro.org>, Linus Walleij <linus.walleij@linaro.org> Subject: RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC Date: Wed, 16 Dec 2020 06:12:30 +0000 [thread overview] Message-ID: <BY5PR13MB4453C2D078F13E60DAE356B982C50@BY5PR13MB4453.namprd13.prod.outlook.com> (raw) In-Reply-To: <CAEUhbmWrCpKraUpijggkiNXa40OAnN9YJF1iFWnrnrhJZN1joA@mail.gmail.com> > -----Original Message----- > From: Bin Meng <bmeng.cn@gmail.com> > Sent: 16 December 2020 11:36 > To: Yash Shah <yash.shah@openfive.com> > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > kernel@vger.kernel.org>; linux-riscv <linux-riscv@lists.infradead.org>; > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@vger.kernel.org>; broonie@kernel.org; Greg Kroah-Hartman > <gregkh@linuxfoundation.org>; Albert Ou <aou@eecs.berkeley.edu>; > lee.jones@linaro.org; u.kleine-koenig@pengutronix.de; Thierry Reding > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Rob > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > <bgolaszewski@baylibre.com>; Linus Walleij <linus.walleij@linaro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > Hi Yash, > > On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@openfive.com> > wrote: > > > > > -----Original Message----- > > > From: Bin Meng <bmeng.cn@gmail.com> > > > Sent: 10 December 2020 19:05 > > > To: Yash Shah <yash.shah@openfive.com> > > > Cc: linux-spi@vger.kernel.org; linux-serial@vger.kernel.org; linux- > > > pwm@vger.kernel.org; linux-i2c@vger.kernel.org; linux-kernel <linux- > > > kernel@vger.kernel.org>; linux-riscv > > > <linux-riscv@lists.infradead.org>; > > > devicetree <devicetree@vger.kernel.org>; open list:GPIO SUBSYSTEM > > > <linux- gpio@vger.kernel.org>; broonie@kernel.org; Greg > > > Kroah-Hartman <gregkh@linuxfoundation.org>; Albert Ou > > > <aou@eecs.berkeley.edu>; lee.jones@linaro.org; > > > u.kleine-koenig@pengutronix.de; Thierry Reding > > > <thierry.reding@gmail.com>; andrew@lunn.ch; Peter Korsgaard > > > <peter@korsgaard.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; > Rob > > > Herring <robh+dt@kernel.org>; Bartosz Golaszewski > > > <bgolaszewski@baylibre.com>; Linus Walleij > > > <linus.walleij@linaro.org> > > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the > > > SiFive FU740- > > > C000 SoC > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@sifive.com> > wrote: > > > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is > > > > built > > > > > > FU740-C000 Soc > > > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > > > This file is expected to grow as more device drivers are added to > > > > the kernel. > > > > > > > > Signed-off-by: Yash Shah <yash.shah@sifive.com> > > > > --- > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > > +++++++++++++++++++++++++++++ > > > > 1 file changed, 293 insertions(+) create mode 100644 > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > new file mode 100644 > > > > index 0000000..eeb4f8c3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > @@ -0,0 +1,293 @@ > > > > ... > > > > > > + plic0: interrupt-controller@c000000 { > > > > + #interrupt-cells = <1>; > > > > + #address-cells = <0>; > > > > + compatible = "sifive,fu540-c000-plic", > > > > + "sifive,plic-1.0.0"; > > > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > > > That's because it is not required. There won't be any difference in driver > code for FU740 plic. > > Are there any driver changes for the drivers that have an updated > fu640-c000-* bindings? I don't see them in the linux-riscv list. Yes, they will be posted soon. - Yash > > > > > ... > > > > > > + eth0: ethernet@10090000 { > > > > + compatible = "sifive,fu540-c000-gem"; > > > > > > "sifive,fu740-c000-gem"? > > > > > > > Same reason as above. > > > > Thanks for your review. > > Regards, > Bin _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-12-16 6:13 UTC|newest] Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-08 4:55 [PATCH v2 0/9] arch: riscv: add board and SoC DT file support Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-08 4:55 ` [PATCH v2 1/9] dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 3:55 ` Rob Herring 2020-12-10 3:55 ` Rob Herring 2020-12-10 13:34 ` Bin Meng 2020-12-10 13:34 ` Bin Meng 2020-12-08 4:55 ` [PATCH v2 2/9] dt-bindings: spi: " Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-08 4:55 ` [PATCH v2 3/9] dt-bindings: pwm: " Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 3:56 ` Rob Herring 2020-12-10 3:56 ` Rob Herring 2020-12-08 4:55 ` [PATCH v2 4/9] dt-bindings: serial: " Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 3:56 ` Rob Herring 2020-12-10 3:56 ` Rob Herring 2020-12-08 4:55 ` [PATCH v2 5/9] dt-bindings: gpio: " Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 3:57 ` Rob Herring 2020-12-10 3:57 ` Rob Herring 2020-12-08 4:55 ` [PATCH v2 6/9] dt-bindings: i2c: " Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 3:59 ` Rob Herring 2020-12-10 3:59 ` Rob Herring 2020-12-22 3:23 ` Palmer Dabbelt 2020-12-22 3:23 ` Palmer Dabbelt 2020-12-08 4:55 ` [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 13:34 ` Bin Meng 2020-12-10 13:34 ` Bin Meng 2020-12-16 5:24 ` Yash Shah 2020-12-16 5:24 ` Yash Shah 2020-12-16 6:06 ` Bin Meng 2020-12-16 6:06 ` Bin Meng 2020-12-16 6:12 ` Yash Shah [this message] 2020-12-16 6:12 ` Yash Shah 2021-07-16 12:49 ` Geert Uytterhoeven 2021-07-16 12:49 ` Geert Uytterhoeven 2021-07-19 17:12 ` David Abdurachmanov 2021-07-19 17:12 ` David Abdurachmanov 2020-12-08 4:55 ` [PATCH v2 8/9] dt-bindings: riscv: Update YAML doc to support SiFive HiFive Unmatched board Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 3:59 ` Rob Herring 2020-12-10 3:59 ` Rob Herring 2020-12-10 13:34 ` Bin Meng 2020-12-10 13:34 ` Bin Meng 2020-12-08 4:55 ` [PATCH v2 9/9] riscv: dts: add initial board data for the SiFive HiFive Unmatched Yash Shah 2020-12-08 4:55 ` Yash Shah 2020-12-10 13:34 ` Bin Meng 2020-12-10 13:34 ` Bin Meng 2020-12-08 17:11 ` (subset) [PATCH v2 0/9] arch: riscv: add board and SoC DT file support Mark Brown 2020-12-08 17:11 ` Mark Brown 2020-12-22 4:38 ` Palmer Dabbelt 2020-12-22 4:38 ` Palmer Dabbelt 2021-01-08 3:12 ` Palmer Dabbelt 2021-01-08 3:12 ` Palmer Dabbelt
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