* [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-24 20:02 ` fei.yang
0 siblings, 0 replies; 17+ messages in thread
From: fei.yang @ 2023-05-24 20:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Fei Yang, andi.shyti, dri-devel, rodrigo.vivi
From: Fei Yang <fei.yang@intel.com>
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased on https://patchwork.freedesktop.org/series/117082/
v4: fix missing unlock introduced in v3, and
solve a rebase conflict
v5: replace obj->cache_level with pat_set_by_user,
fix i915_cache_level_str() for legacy platforms.
v6: rebased on https://patchwork.freedesktop.org/series/117480/
v7: rebased on https://patchwork.freedesktop.org/series/117528/
v8: dropped the two dependent patches that has been merged
separately. Add IGT link and Tested-by (MESA).
v9: addressing comments (Andi)
v10: acked-by and tested-by MESA
v11: drop "end support for set caching ioctl" (merged)
remove tools/include/uapi/drm/i915_drm.h
v12: drop Bspec reference in comment. add to commit message instead
Fei Yang (1):
drm/i915: Allow user to set cache at BO creation
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
3 files changed, 83 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-24 20:02 ` fei.yang
0 siblings, 0 replies; 17+ messages in thread
From: fei.yang @ 2023-05-24 20:02 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, rodrigo.vivi
From: Fei Yang <fei.yang@intel.com>
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased on https://patchwork.freedesktop.org/series/117082/
v4: fix missing unlock introduced in v3, and
solve a rebase conflict
v5: replace obj->cache_level with pat_set_by_user,
fix i915_cache_level_str() for legacy platforms.
v6: rebased on https://patchwork.freedesktop.org/series/117480/
v7: rebased on https://patchwork.freedesktop.org/series/117528/
v8: dropped the two dependent patches that has been merged
separately. Add IGT link and Tested-by (MESA).
v9: addressing comments (Andi)
v10: acked-by and tested-by MESA
v11: drop "end support for set caching ioctl" (merged)
remove tools/include/uapi/drm/i915_drm.h
v12: drop Bspec reference in comment. add to commit message instead
Fei Yang (1):
drm/i915: Allow user to set cache at BO creation
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
3 files changed, 83 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
@ 2023-05-24 20:02 ` fei.yang
-1 siblings, 0 replies; 17+ messages in thread
From: fei.yang @ 2023-05-24 20:02 UTC (permalink / raw)
To: intel-gfx
Cc: andi.shyti, Jordan Justen, Chris Wilson, dri-devel, Fei Yang,
rodrigo.vivi, Matt Roper
From: Fei Yang <fei.yang@intel.com>
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.
BSpec: 45101
Test igt@gem_create@create_ext_set_pat posted at
https://patchwork.freedesktop.org/series/118314/
Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
Signed-off-by: Fei Yang <fei.yang@intel.com>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
3 files changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index bfe1dbda4cb7..644a936248ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -245,6 +245,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+ unsigned int pat_index;
};
static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data
return 0;
}
+static int ext_set_pat(struct i915_user_extension __user *base, void *data)
+{
+ struct create_ext *ext_data = data;
+ struct drm_i915_private *i915 = ext_data->i915;
+ struct drm_i915_gem_create_ext_set_pat ext;
+ unsigned int max_pat_index;
+
+ BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
+ offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ max_pat_index = INTEL_INFO(i915)->max_pat_index;
+
+ if (ext.pat_index > max_pat_index) {
+ drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
+ ext.pat_index);
+ return -EINVAL;
+ }
+
+ ext_data->pat_index = ext.pat_index;
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+ [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
};
+#define PAT_INDEX_NOT_SET 0xffff
/**
* i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,
if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
+ ext_data.pat_index = PAT_INDEX_NOT_SET;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
create_extensions,
ARRAY_SIZE(create_extensions),
@@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
+ i915_gem_object_set_pat_index(obj, ext_data.pat_index);
+ /* Mark pat_index is set by UMD */
+ obj->pat_set_by_user = true;
+ }
+
return i915_gem_publish(obj, file, &args->size, &args->handle);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 46a19b099ec8..97ac6fb37958 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
if (!(obj->flags & I915_BO_ALLOC_USER))
return false;
+ /*
+ * Always flush cache for UMD objects at creation time.
+ */
+ if (obj->pat_set_by_user)
+ return true;
+
/*
* EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
* possible for userspace to bypass the GTT caching bits set by the
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f31dfacde601..4083a23e0614 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3679,9 +3679,13 @@ struct drm_i915_gem_create_ext {
*
* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
* struct drm_i915_gem_create_ext_protected_content.
+ *
+ * For I915_GEM_CREATE_EXT_SET_PAT usage see
+ * struct drm_i915_gem_create_ext_set_pat.
*/
#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
+#define I915_GEM_CREATE_EXT_SET_PAT 2
__u64 extensions;
};
@@ -3796,6 +3800,43 @@ struct drm_i915_gem_create_ext_protected_content {
__u32 flags;
};
+/**
+ * struct drm_i915_gem_create_ext_set_pat - The
+ * I915_GEM_CREATE_EXT_SET_PAT extension.
+ *
+ * If this extension is provided, the specified caching policy (PAT index) is
+ * applied to the buffer object.
+ *
+ * Below is an example on how to create an object with specific caching policy:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_create_ext_set_pat set_pat_ext = {
+ * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT },
+ * .pat_index = 0,
+ * };
+ * struct drm_i915_gem_create_ext create_ext = {
+ * .size = PAGE_SIZE,
+ * .extensions = (uintptr_t)&set_pat_ext,
+ * };
+ *
+ * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ * if (err) ...
+ */
+struct drm_i915_gem_create_ext_set_pat {
+ /** @base: Extension link. See struct i915_user_extension. */
+ struct i915_user_extension base;
+ /**
+ * @pat_index: PAT index to be set
+ * PAT index is a bit field in Page Table Entry to control caching
+ * behaviors for GPU accesses. The definition of PAT index is
+ * platform dependent and can be found in hardware specifications,
+ */
+ __u32 pat_index;
+ /** @rsvd: reserved for future use */
+ __u32 rsvd;
+};
+
/* ID of the protected content session managed by i915 when PXP is active */
#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-24 20:02 ` fei.yang
0 siblings, 0 replies; 17+ messages in thread
From: fei.yang @ 2023-05-24 20:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, dri-devel, rodrigo.vivi, Matt Roper
From: Fei Yang <fei.yang@intel.com>
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a default (platform dependent) cache setting for all objects.
However this is not optimal for performance tuning. The patch extends
the existing gem_create uAPI to let user set PAT index for the object
at creation time.
The new extension is platform independent, so UMD's can switch to using
this extension for older platforms as well, while {set, get}_caching are
still supported on these legacy paltforms for compatibility reason.
BSpec: 45101
Test igt@gem_create@create_ext_set_pat posted at
https://patchwork.freedesktop.org/series/118314/
Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
Signed-off-by: Fei Yang <fei.yang@intel.com>
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
3 files changed, 83 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index bfe1dbda4cb7..644a936248ad 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -245,6 +245,7 @@ struct create_ext {
unsigned int n_placements;
unsigned int placement_mask;
unsigned long flags;
+ unsigned int pat_index;
};
static void repr_placements(char *buf, size_t size,
@@ -394,11 +395,39 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data
return 0;
}
+static int ext_set_pat(struct i915_user_extension __user *base, void *data)
+{
+ struct create_ext *ext_data = data;
+ struct drm_i915_private *i915 = ext_data->i915;
+ struct drm_i915_gem_create_ext_set_pat ext;
+ unsigned int max_pat_index;
+
+ BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
+ offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ max_pat_index = INTEL_INFO(i915)->max_pat_index;
+
+ if (ext.pat_index > max_pat_index) {
+ drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
+ ext.pat_index);
+ return -EINVAL;
+ }
+
+ ext_data->pat_index = ext.pat_index;
+
+ return 0;
+}
+
static const i915_user_extension_fn create_extensions[] = {
[I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
[I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
+ [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
};
+#define PAT_INDEX_NOT_SET 0xffff
/**
* i915_gem_create_ext_ioctl - Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -418,6 +447,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,
if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
return -EINVAL;
+ ext_data.pat_index = PAT_INDEX_NOT_SET;
ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
create_extensions,
ARRAY_SIZE(create_extensions),
@@ -454,5 +484,11 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ if (ext_data.pat_index != PAT_INDEX_NOT_SET) {
+ i915_gem_object_set_pat_index(obj, ext_data.pat_index);
+ /* Mark pat_index is set by UMD */
+ obj->pat_set_by_user = true;
+ }
+
return i915_gem_publish(obj, file, &args->size, &args->handle);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 46a19b099ec8..97ac6fb37958 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -208,6 +208,12 @@ bool i915_gem_object_can_bypass_llc(struct drm_i915_gem_object *obj)
if (!(obj->flags & I915_BO_ALLOC_USER))
return false;
+ /*
+ * Always flush cache for UMD objects at creation time.
+ */
+ if (obj->pat_set_by_user)
+ return true;
+
/*
* EHL and JSL add the 'Bypass LLC' MOCS entry, which should make it
* possible for userspace to bypass the GTT caching bits set by the
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index f31dfacde601..4083a23e0614 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -3679,9 +3679,13 @@ struct drm_i915_gem_create_ext {
*
* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
* struct drm_i915_gem_create_ext_protected_content.
+ *
+ * For I915_GEM_CREATE_EXT_SET_PAT usage see
+ * struct drm_i915_gem_create_ext_set_pat.
*/
#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
+#define I915_GEM_CREATE_EXT_SET_PAT 2
__u64 extensions;
};
@@ -3796,6 +3800,43 @@ struct drm_i915_gem_create_ext_protected_content {
__u32 flags;
};
+/**
+ * struct drm_i915_gem_create_ext_set_pat - The
+ * I915_GEM_CREATE_EXT_SET_PAT extension.
+ *
+ * If this extension is provided, the specified caching policy (PAT index) is
+ * applied to the buffer object.
+ *
+ * Below is an example on how to create an object with specific caching policy:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_gem_create_ext_set_pat set_pat_ext = {
+ * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT },
+ * .pat_index = 0,
+ * };
+ * struct drm_i915_gem_create_ext create_ext = {
+ * .size = PAGE_SIZE,
+ * .extensions = (uintptr_t)&set_pat_ext,
+ * };
+ *
+ * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ * if (err) ...
+ */
+struct drm_i915_gem_create_ext_set_pat {
+ /** @base: Extension link. See struct i915_user_extension. */
+ struct i915_user_extension base;
+ /**
+ * @pat_index: PAT index to be set
+ * PAT index is a bit field in Page Table Entry to control caching
+ * behaviors for GPU accesses. The definition of PAT index is
+ * platform dependent and can be found in hardware specifications,
+ */
+ __u32 pat_index;
+ /** @rsvd: reserved for future use */
+ __u32 rsvd;
+};
+
/* ID of the protected content session managed by i915 when PXP is active */
#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation (rev12)
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
(?)
(?)
@ 2023-05-24 22:34 ` Patchwork
-1 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-05-24 22:34 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8073 bytes --]
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev12)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13187 -> Patchwork_116870v12
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/index.html
Participating hosts (39 -> 37)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (3): fi-kbl-soraka fi-snb-2520m bat-mtlp-6
Known issues
------------
Here are the changes found in Patchwork_116870v12 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#3546] / [i915#7561])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][5] ([i915#6367])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][6] ([i915#7443] / [i915#8102])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_edid@dp-edid-read:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#7828]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([i915#4103]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([fdo#109285])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#1845] / [i915#5354]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][11] ([i915#3546]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
* igt@kms_psr@cursor_plane_move:
- fi-tgl-1115g4: NOTRUN -> [SKIP][12] ([fdo#110189]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#4579])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@i915_selftest@live@guc:
- bat-rpls-1: [DMESG-WARN][14] ([i915#7852]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/bat-rpls-1/igt@i915_selftest@live@guc.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-rpls-1/igt@i915_selftest@live@guc.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][16] ([i915#7699]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/bat-dg2-11/igt@i915_selftest@live@migrate.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@mman:
- bat-rpls-2: [TIMEOUT][18] ([i915#6794] / [i915#7392]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/bat-rpls-2/igt@i915_selftest@live@mman.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-rpls-2/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [DMESG-FAIL][20] ([i915#8497]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/bat-mtlp-8/igt@i915_selftest@live@requests.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
- bat-dg2-8: [FAIL][22] ([i915#7932]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7852]: https://gitlab.freedesktop.org/drm/intel/issues/7852
[i915#7932]: https://gitlab.freedesktop.org/drm/intel/issues/7932
[i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
Build changes
-------------
* Linux: CI_DRM_13187 -> Patchwork_116870v12
CI-20190529: 20190529
CI_DRM_13187: e72bc131968e21d9deeae208605481c93581f142 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7303: 8f09a9f1da506db907b549bb477f3233b5416733 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116870v12: e72bc131968e21d9deeae208605481c93581f142 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b3fbf140752b drm/i915: Allow user to set cache at BO creation
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/index.html
[-- Attachment #2: Type: text/html, Size: 9135 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
` (2 preceding siblings ...)
(?)
@ 2023-05-25 8:33 ` Tvrtko Ursulin
2023-05-25 15:12 ` Yang, Fei
-1 siblings, 1 reply; 17+ messages in thread
From: Tvrtko Ursulin @ 2023-05-25 8:33 UTC (permalink / raw)
To: fei.yang, intel-gfx; +Cc: dri-devel, rodrigo.vivi
On 24/05/2023 21:02, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
>
> This series introduce a new extension for GEM_CREATE,
> 1. end support for set caching ioctl [PATCH 1/2]
> 2. add set_pat extension for gem_create [PATCH 2/2]
>
> v2: drop one patch that was merged separately
> commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
> v3: rebased on https://patchwork.freedesktop.org/series/117082/
> v4: fix missing unlock introduced in v3, and
> solve a rebase conflict
> v5: replace obj->cache_level with pat_set_by_user,
> fix i915_cache_level_str() for legacy platforms.
> v6: rebased on https://patchwork.freedesktop.org/series/117480/
> v7: rebased on https://patchwork.freedesktop.org/series/117528/
> v8: dropped the two dependent patches that has been merged
> separately. Add IGT link and Tested-by (MESA).
> v9: addressing comments (Andi)
> v10: acked-by and tested-by MESA
> v11: drop "end support for set caching ioctl" (merged)
> remove tools/include/uapi/drm/i915_drm.h
> v12: drop Bspec reference in comment. add to commit message instead
>
> Fei Yang (1):
> drm/i915: Allow user to set cache at BO creation
>
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
> include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
> 3 files changed, 83 insertions(+)
>
Do you also have a Test-with: run against the new IGT somewhere?
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
2023-05-25 8:33 ` [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation Tvrtko Ursulin
@ 2023-05-25 15:12 ` Yang, Fei
2023-05-25 15:26 ` Yang, Fei
2023-05-25 15:29 ` Yang, Fei
0 siblings, 2 replies; 17+ messages in thread
From: Yang, Fei @ 2023-05-25 15:12 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: dri-devel, Vivi, Rodrigo
[-- Attachment #1: Type: text/plain, Size: 2074 bytes --]
Sounds weird to have a platform restriction on uAPI though. UMD not using this extension is not a problem, is it?
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Sent: Thursday, May 25, 2023 1:33 AM
To: Yang, Fei <fei.yang@intel.com>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>
Cc: dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
On 24/05/2023 21:02, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
>
> This series introduce a new extension for GEM_CREATE,
> 1. end support for set caching ioctl [PATCH 1/2]
> 2. add set_pat extension for gem_create [PATCH 2/2]
>
> v2: drop one patch that was merged separately
> commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
> v3: rebased on https://patchwork.freedesktop.org/series/117082/
> v4: fix missing unlock introduced in v3, and
> solve a rebase conflict
> v5: replace obj->cache_level with pat_set_by_user,
> fix i915_cache_level_str() for legacy platforms.
> v6: rebased on https://patchwork.freedesktop.org/series/117480/
> v7: rebased on https://patchwork.freedesktop.org/series/117528/
> v8: dropped the two dependent patches that has been merged
> separately. Add IGT link and Tested-by (MESA).
> v9: addressing comments (Andi)
> v10: acked-by and tested-by MESA
> v11: drop "end support for set caching ioctl" (merged)
> remove tools/include/uapi/drm/i915_drm.h
> v12: drop Bspec reference in comment. add to commit message instead
>
> Fei Yang (1):
> drm/i915: Allow user to set cache at BO creation
>
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
> include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
> 3 files changed, 83 insertions(+)
>
Do you also have a Test-with: run against the new IGT somewhere?
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
2023-05-25 15:12 ` Yang, Fei
@ 2023-05-25 15:26 ` Yang, Fei
2023-05-25 15:29 ` Yang, Fei
1 sibling, 0 replies; 17+ messages in thread
From: Yang, Fei @ 2023-05-25 15:26 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: dri-devel, Vivi, Rodrigo
[-- Attachment #1: Type: text/plain, Size: 1722 bytes --]
> On 24/05/2023 21:02, fei.yang@intel.com wrote:
>> From: Fei Yang <fei.yang@intel.com>
>>
>> This series introduce a new extension for GEM_CREATE,
>> 1. end support for set caching ioctl [PATCH 1/2]
>> 2. add set_pat extension for gem_create [PATCH 2/2]
>>
>> v2: drop one patch that was merged separately
>> commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
>> v3: rebased on https://patchwork.freedesktop.org/series/117082/
>> v4: fix missing unlock introduced in v3, and
>> solve a rebase conflict
>> v5: replace obj->cache_level with pat_set_by_user,
>> fix i915_cache_level_str() for legacy platforms.
>> v6: rebased on https://patchwork.freedesktop.org/series/117480/
>> v7: rebased on https://patchwork.freedesktop.org/series/117528/
>> v8: dropped the two dependent patches that has been merged
>> separately. Add IGT link and Tested-by (MESA).
>> v9: addressing comments (Andi)
>> v10: acked-by and tested-by MESA
>> v11: drop "end support for set caching ioctl" (merged)
>> remove tools/include/uapi/drm/i915_drm.h
>> v12: drop Bspec reference in comment. add to commit message instead
>>
>> Fei Yang (1):
>> drm/i915: Allow user to set cache at BO creation
>>
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
>> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
>> include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
>> 3 files changed, 83 insertions(+)
>>
>
> Do you also have a Test-with: run against the new IGT somewhere?
I ran locate test, not sure how to get a IGT result with updated kernel on patchwork,
looks like a chicken and egg problem.
> Regards,
>
> Tvrtko
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^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
2023-05-25 15:12 ` Yang, Fei
@ 2023-05-25 15:29 ` Yang, Fei
2023-05-25 15:29 ` Yang, Fei
1 sibling, 0 replies; 17+ messages in thread
From: Yang, Fei @ 2023-05-25 15:29 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: dri-devel, Vivi, Rodrigo
[-- Attachment #1: Type: text/plain, Size: 2758 bytes --]
Sorry replied on top of wrong thread.
From: Yang, Fei <fei.yang@intel.com>
Sent: Thursday, May 25, 2023 8:12 AM
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>; intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
Sounds weird to have a platform restriction on uAPI though. UMD not using this extension is not a problem, is it?
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com<mailto:tvrtko.ursulin@linux.intel.com>>
Sent: Thursday, May 25, 2023 1:33 AM
To: Yang, Fei <fei.yang@intel.com<mailto:fei.yang@intel.com>>; intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org> <intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>>
Cc: dri-devel@lists.freedesktop.org<mailto:dri-devel@lists.freedesktop.org> <dri-devel@lists.freedesktop.org<mailto:dri-devel@lists.freedesktop.org>>; Vivi, Rodrigo <rodrigo.vivi@intel.com<mailto:rodrigo.vivi@intel.com>>
Subject: Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
On 24/05/2023 21:02, fei.yang@intel.com<mailto:fei.yang@intel.com> wrote:
> From: Fei Yang <fei.yang@intel.com<mailto:fei.yang@intel.com>>
>
> This series introduce a new extension for GEM_CREATE,
> 1. end support for set caching ioctl [PATCH 1/2]
> 2. add set_pat extension for gem_create [PATCH 2/2]
>
> v2: drop one patch that was merged separately
> commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
> v3: rebased on https://patchwork.freedesktop.org/series/117082/
> v4: fix missing unlock introduced in v3, and
> solve a rebase conflict
> v5: replace obj->cache_level with pat_set_by_user,
> fix i915_cache_level_str() for legacy platforms.
> v6: rebased on https://patchwork.freedesktop.org/series/117480/
> v7: rebased on https://patchwork.freedesktop.org/series/117528/
> v8: dropped the two dependent patches that has been merged
> separately. Add IGT link and Tested-by (MESA).
> v9: addressing comments (Andi)
> v10: acked-by and tested-by MESA
> v11: drop "end support for set caching ioctl" (merged)
> remove tools/include/uapi/drm/i915_drm.h
> v12: drop Bspec reference in comment. add to commit message instead
>
> Fei Yang (1):
> drm/i915: Allow user to set cache at BO creation
>
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
> include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
> 3 files changed, 83 insertions(+)
>
Do you also have a Test-with: run against the new IGT somewhere?
Regards,
Tvrtko
[-- Attachment #2: Type: text/html, Size: 6583 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-25 15:29 ` Yang, Fei
0 siblings, 0 replies; 17+ messages in thread
From: Yang, Fei @ 2023-05-25 15:29 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: dri-devel, Vivi, Rodrigo
[-- Attachment #1: Type: text/plain, Size: 2758 bytes --]
Sorry replied on top of wrong thread.
From: Yang, Fei <fei.yang@intel.com>
Sent: Thursday, May 25, 2023 8:12 AM
To: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>; intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
Sounds weird to have a platform restriction on uAPI though. UMD not using this extension is not a problem, is it?
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com<mailto:tvrtko.ursulin@linux.intel.com>>
Sent: Thursday, May 25, 2023 1:33 AM
To: Yang, Fei <fei.yang@intel.com<mailto:fei.yang@intel.com>>; intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org> <intel-gfx@lists.freedesktop.org<mailto:intel-gfx@lists.freedesktop.org>>
Cc: dri-devel@lists.freedesktop.org<mailto:dri-devel@lists.freedesktop.org> <dri-devel@lists.freedesktop.org<mailto:dri-devel@lists.freedesktop.org>>; Vivi, Rodrigo <rodrigo.vivi@intel.com<mailto:rodrigo.vivi@intel.com>>
Subject: Re: [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation
On 24/05/2023 21:02, fei.yang@intel.com<mailto:fei.yang@intel.com> wrote:
> From: Fei Yang <fei.yang@intel.com<mailto:fei.yang@intel.com>>
>
> This series introduce a new extension for GEM_CREATE,
> 1. end support for set caching ioctl [PATCH 1/2]
> 2. add set_pat extension for gem_create [PATCH 2/2]
>
> v2: drop one patch that was merged separately
> commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
> v3: rebased on https://patchwork.freedesktop.org/series/117082/
> v4: fix missing unlock introduced in v3, and
> solve a rebase conflict
> v5: replace obj->cache_level with pat_set_by_user,
> fix i915_cache_level_str() for legacy platforms.
> v6: rebased on https://patchwork.freedesktop.org/series/117480/
> v7: rebased on https://patchwork.freedesktop.org/series/117528/
> v8: dropped the two dependent patches that has been merged
> separately. Add IGT link and Tested-by (MESA).
> v9: addressing comments (Andi)
> v10: acked-by and tested-by MESA
> v11: drop "end support for set caching ioctl" (merged)
> remove tools/include/uapi/drm/i915_drm.h
> v12: drop Bspec reference in comment. add to commit message instead
>
> Fei Yang (1):
> drm/i915: Allow user to set cache at BO creation
>
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 36 +++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_object.c | 6 ++++
> include/uapi/drm/i915_drm.h | 41 ++++++++++++++++++++++
> 3 files changed, 83 insertions(+)
>
Do you also have a Test-with: run against the new IGT somewhere?
Regards,
Tvrtko
[-- Attachment #2: Type: text/html, Size: 6583 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation (rev12)
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
` (3 preceding siblings ...)
(?)
@ 2023-05-25 18:33 ` Patchwork
-1 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-05-25 18:33 UTC (permalink / raw)
To: fei.yang; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 46781 bytes --]
== Series Details ==
Series: drm/i915: Allow user to set cache at BO creation (rev12)
URL : https://patchwork.freedesktop.org/series/116870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13187_full -> Patchwork_116870v12_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between CI_DRM_13187_full and Patchwork_116870v12_full:
### New IGT tests (283) ###
* igt@kms_flip@2x-dpms-vs-vblank-race@ab-hdmi-a1-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race@ac-hdmi-a1-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race@bc-hdmi-a1-hdmi-a2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-a-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-b-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-a-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-b-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-hdmi-a-1:
- Statuses : 1 pass(s) 3 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-b-hdmi-a-1:
- Statuses : 1 pass(s) 3 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-hdmi-a-1:
- Statuses : 3 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling:
- Statuses :
- Exec time: [None] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-a-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-b-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-scaler-unity-scaling@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-b-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-a-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b-vga-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-c-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a-hdmi-a-1:
- Statuses : 3 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b-hdmi-a-1:
- Statuses : 3 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-20x20@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 2 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-c-hdmi-a-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-a-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-a-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-a-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-dp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-hdmi-a-1:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-hdmi-a-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b-vga-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-c-dp-1:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s) 1 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_116870v12_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-glk: [PASS][1] -> [ABORT][2] ([i915#7461] / [i915#8211])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk8/igt@gem_barrier_race@remote-request@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-glk9/igt@gem_barrier_race@remote-request@rcs0.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][3] -> [FAIL][4] ([IGT#6] / [i915#72])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4579]) +12 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-snb1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2 (NEW):
- {shard-rkl}: NOTRUN -> [SKIP][6] ([i915#4579] / [i915#5176]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-hdmi-a-1 (NEW):
- {shard-rkl}: NOTRUN -> [SKIP][7] ([i915#5176])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-rkl-7/igt@kms_plane_scaling@plane-scaler-with-rotation-unity-scaling@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +15 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-snb1/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2 (NEW):
- {shard-rkl}: NOTRUN -> [SKIP][9] ([i915#4579] / [i915#5235])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-rkl-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][10] ([i915#5465]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#1731])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk1/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-glk5/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}: [FAIL][13] ([i915#2842]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][15] ([i915#2842]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-tglu-9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-tglu-8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_spin_batch@user-each:
- shard-apl: [FAIL][17] ([i915#2898]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-apl3/igt@gem_spin_batch@user-each.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-apl6/igt@gem_spin_batch@user-each.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-tglu}: [FAIL][19] ([i915#3989] / [i915#454]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-tglu-5/igt@i915_pm_dc@dc6-dpms.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-tglu-9/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][21] ([IGT#6] / [i915#2346]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][23] ([i915#79]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13187/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
Build changes
-------------
* Linux: CI_DRM_13187 -> Patchwork_116870v12
CI-20190529: 20190529
CI_DRM_13187: e72bc131968e21d9deeae208605481c93581f142 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7303: 8f09a9f1da506db907b549bb477f3233b5416733 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116870v12: e72bc131968e21d9deeae208605481c93581f142 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116870v12/index.html
[-- Attachment #2: Type: text/html, Size: 55639 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
@ 2023-05-31 10:49 ` Andi Shyti
-1 siblings, 0 replies; 17+ messages in thread
From: Andi Shyti @ 2023-05-31 10:49 UTC (permalink / raw)
To: fei.yang, Carl Zhang
Cc: Jordan Justen, Chris Wilson, intel-gfx, dri-devel, andi.shyti,
rodrigo.vivi, Matt Roper
Hi Carl,
On Wed, May 24, 2023 at 01:02:55PM -0700, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
>
> To comply with the design that buffer objects shall have immutable
> cache setting through out their life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at object creation time. The current code
> applies a default (platform dependent) cache setting for all objects.
> However this is not optimal for performance tuning. The patch extends
> the existing gem_create uAPI to let user set PAT index for the object
> at creation time.
> The new extension is platform independent, so UMD's can switch to using
> this extension for older platforms as well, while {set, get}_caching are
> still supported on these legacy paltforms for compatibility reason.
>
> BSpec: 45101
>
> Test igt@gem_create@create_ext_set_pat posted at
> https://patchwork.freedesktop.org/series/118314/
>
> Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
>
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
> Tested-by: Jordan Justen <jordan.l.justen@intel.com>
was it your intention to ack this patch?
Thanks,
Andi
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-31 10:49 ` Andi Shyti
0 siblings, 0 replies; 17+ messages in thread
From: Andi Shyti @ 2023-05-31 10:49 UTC (permalink / raw)
To: fei.yang, Carl Zhang
Cc: Chris Wilson, intel-gfx, dri-devel, rodrigo.vivi, Matt Roper
Hi Carl,
On Wed, May 24, 2023 at 01:02:55PM -0700, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
>
> To comply with the design that buffer objects shall have immutable
> cache setting through out their life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at object creation time. The current code
> applies a default (platform dependent) cache setting for all objects.
> However this is not optimal for performance tuning. The patch extends
> the existing gem_create uAPI to let user set PAT index for the object
> at creation time.
> The new extension is platform independent, so UMD's can switch to using
> this extension for older platforms as well, while {set, get}_caching are
> still supported on these legacy paltforms for compatibility reason.
>
> BSpec: 45101
>
> Test igt@gem_create@create_ext_set_pat posted at
> https://patchwork.freedesktop.org/series/118314/
>
> Tested with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
>
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> Acked-by: Jordan Justen <jordan.l.justen@intel.com>
> Tested-by: Jordan Justen <jordan.l.justen@intel.com>
was it your intention to ack this patch?
Thanks,
Andi
^ permalink raw reply [flat|nested] 17+ messages in thread
* RE: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
2023-05-31 10:49 ` [Intel-gfx] " Andi Shyti
@ 2023-05-31 12:24 ` Zhang, Carl
-1 siblings, 0 replies; 17+ messages in thread
From: Zhang, Carl @ 2023-05-31 12:24 UTC (permalink / raw)
To: Andi Shyti, Yang, Fei
Cc: Chris Wilson, intel-gfx, Vivi, Rodrigo, dri-devel, Justen,
Jordan L, Roper, Matthew D
Hi Andi & Fei,
We verified your change by UMD change:
1. implement the uAPI by
https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
2. old kernel may not support new uAPI, so UMD try the interface firstly, if it failed, will fallback to older interfaces
https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
3. removed some check for CPU cacheable and PAT conflict
https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
after that, UMD works with your patches serious on MTL.
Acked-by: Carl Zhang <carl.zhang@intel.com>
Tested-by: Lihao Gu <lihao.gu@intel.com>
Thanks
Carl
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Wednesday, May 31, 2023 6:49 PM
> To: Yang, Fei <fei.yang@intel.com>; Zhang, Carl <carl.zhang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vivi,
> Rodrigo <rodrigo.vivi@intel.com>; andi.shyti@linux.intel.com; Chris Wilson
> <chris.p.wilson@linux.intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: Re: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
>
> Hi Carl,
>
> On Wed, May 24, 2023 at 01:02:55PM -0700, fei.yang@intel.com wrote:
> > From: Fei Yang <fei.yang@intel.com>
> >
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out their life cycle, {set, get}_caching ioctl's
> > are no longer supported from MTL onward. With that change caching
> > policy can only be set at object creation time. The current code
> > applies a default (platform dependent) cache setting for all objects.
> > However this is not optimal for performance tuning. The patch extends
> > the existing gem_create uAPI to let user set PAT index for the object
> > at creation time.
> > The new extension is platform independent, so UMD's can switch to
> > using this extension for older platforms as well, while {set,
> > get}_caching are still supported on these legacy paltforms for compatibility
> reason.
> >
> > BSpec: 45101
> >
> > Test igt@gem_create@create_ext_set_pat posted at
> > https://patchwork.freedesktop.org/series/118314/
> >
> > Tested with
> > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> >
> > Signed-off-by: Fei Yang <fei.yang@intel.com>
> > Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Acked-by: Jordan Justen <jordan.l.justen@intel.com>
> > Tested-by: Jordan Justen <jordan.l.justen@intel.com>
>
> was it your intention to ack this patch?
>
> Thanks,
> Andi
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-31 12:24 ` Zhang, Carl
0 siblings, 0 replies; 17+ messages in thread
From: Zhang, Carl @ 2023-05-31 12:24 UTC (permalink / raw)
To: Andi Shyti, Yang, Fei
Cc: Chris Wilson, intel-gfx, Vivi, Rodrigo, dri-devel, Roper, Matthew D
Hi Andi & Fei,
We verified your change by UMD change:
1. implement the uAPI by
https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
2. old kernel may not support new uAPI, so UMD try the interface firstly, if it failed, will fallback to older interfaces
https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
3. removed some check for CPU cacheable and PAT conflict
https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
after that, UMD works with your patches serious on MTL.
Acked-by: Carl Zhang <carl.zhang@intel.com>
Tested-by: Lihao Gu <lihao.gu@intel.com>
Thanks
Carl
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Wednesday, May 31, 2023 6:49 PM
> To: Yang, Fei <fei.yang@intel.com>; Zhang, Carl <carl.zhang@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vivi,
> Rodrigo <rodrigo.vivi@intel.com>; andi.shyti@linux.intel.com; Chris Wilson
> <chris.p.wilson@linux.intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: Re: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
>
> Hi Carl,
>
> On Wed, May 24, 2023 at 01:02:55PM -0700, fei.yang@intel.com wrote:
> > From: Fei Yang <fei.yang@intel.com>
> >
> > To comply with the design that buffer objects shall have immutable
> > cache setting through out their life cycle, {set, get}_caching ioctl's
> > are no longer supported from MTL onward. With that change caching
> > policy can only be set at object creation time. The current code
> > applies a default (platform dependent) cache setting for all objects.
> > However this is not optimal for performance tuning. The patch extends
> > the existing gem_create uAPI to let user set PAT index for the object
> > at creation time.
> > The new extension is platform independent, so UMD's can switch to
> > using this extension for older platforms as well, while {set,
> > get}_caching are still supported on these legacy paltforms for compatibility
> reason.
> >
> > BSpec: 45101
> >
> > Test igt@gem_create@create_ext_set_pat posted at
> > https://patchwork.freedesktop.org/series/118314/
> >
> > Tested with
> > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> >
> > Signed-off-by: Fei Yang <fei.yang@intel.com>
> > Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> > Acked-by: Jordan Justen <jordan.l.justen@intel.com>
> > Tested-by: Jordan Justen <jordan.l.justen@intel.com>
>
> was it your intention to ack this patch?
>
> Thanks,
> Andi
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
2023-05-31 12:24 ` [Intel-gfx] " Zhang, Carl
@ 2023-05-31 12:28 ` Andi Shyti
-1 siblings, 0 replies; 17+ messages in thread
From: Andi Shyti @ 2023-05-31 12:28 UTC (permalink / raw)
To: Zhang, Carl, Lihao Gu
Cc: Andi Shyti, Justen, Jordan L, Roper, Matthew D, intel-gfx,
dri-devel, Yang, Fei, Vivi, Rodrigo, Chris Wilson
Hi Carl,
On Wed, May 31, 2023 at 12:24:07PM +0000, Zhang, Carl wrote:
> Hi Andi & Fei,
> We verified your change by UMD change:
> 1. implement the uAPI by
> https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
> 2. old kernel may not support new uAPI, so UMD try the interface firstly, if it failed, will fallback to older interfaces
> https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
> 3. removed some check for CPU cacheable and PAT conflict
> https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
Thanks a lot... we can add these commits in the log, as well.
> after that, UMD works with your patches serious on MTL.
>
> Acked-by: Carl Zhang <carl.zhang@intel.com>
> Tested-by: Lihao Gu <lihao.gu@intel.com>
Thanks Carl and Lihao! Very appreciated :)
Andi
> Thanks
> Carl
> > -----Original Message-----
> > From: Andi Shyti <andi.shyti@linux.intel.com>
> > Sent: Wednesday, May 31, 2023 6:49 PM
> > To: Yang, Fei <fei.yang@intel.com>; Zhang, Carl <carl.zhang@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vivi,
> > Rodrigo <rodrigo.vivi@intel.com>; andi.shyti@linux.intel.com; Chris Wilson
> > <chris.p.wilson@linux.intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>
> > Subject: Re: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
> >
> > Hi Carl,
> >
> > On Wed, May 24, 2023 at 01:02:55PM -0700, fei.yang@intel.com wrote:
> > > From: Fei Yang <fei.yang@intel.com>
> > >
> > > To comply with the design that buffer objects shall have immutable
> > > cache setting through out their life cycle, {set, get}_caching ioctl's
> > > are no longer supported from MTL onward. With that change caching
> > > policy can only be set at object creation time. The current code
> > > applies a default (platform dependent) cache setting for all objects.
> > > However this is not optimal for performance tuning. The patch extends
> > > the existing gem_create uAPI to let user set PAT index for the object
> > > at creation time.
> > > The new extension is platform independent, so UMD's can switch to
> > > using this extension for older platforms as well, while {set,
> > > get}_caching are still supported on these legacy paltforms for compatibility
> > reason.
> > >
> > > BSpec: 45101
> > >
> > > Test igt@gem_create@create_ext_set_pat posted at
> > > https://patchwork.freedesktop.org/series/118314/
> > >
> > > Tested with
> > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> > >
> > > Signed-off-by: Fei Yang <fei.yang@intel.com>
> > > Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> > > Acked-by: Jordan Justen <jordan.l.justen@intel.com>
> > > Tested-by: Jordan Justen <jordan.l.justen@intel.com>
> >
> > was it your intention to ack this patch?
> >
> > Thanks,
> > Andi
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
@ 2023-05-31 12:28 ` Andi Shyti
0 siblings, 0 replies; 17+ messages in thread
From: Andi Shyti @ 2023-05-31 12:28 UTC (permalink / raw)
To: Zhang, Carl, Lihao Gu
Cc: Roper, Matthew D, intel-gfx, dri-devel, Vivi, Rodrigo, Chris Wilson
Hi Carl,
On Wed, May 31, 2023 at 12:24:07PM +0000, Zhang, Carl wrote:
> Hi Andi & Fei,
> We verified your change by UMD change:
> 1. implement the uAPI by
> https://github.com/intel/media-driver/commit/92c00a857433ebb34ec575e9834f473c6fcb6341
> 2. old kernel may not support new uAPI, so UMD try the interface firstly, if it failed, will fallback to older interfaces
> https://github.com/intel/media-driver/commit/fd375cf2c5e1f6bf6b43258ff797b3134aadc9fd
> 3. removed some check for CPU cacheable and PAT conflict
> https://github.com/intel/media-driver/commit/08dd244b22484770a33464c2c8ae85430e548000
Thanks a lot... we can add these commits in the log, as well.
> after that, UMD works with your patches serious on MTL.
>
> Acked-by: Carl Zhang <carl.zhang@intel.com>
> Tested-by: Lihao Gu <lihao.gu@intel.com>
Thanks Carl and Lihao! Very appreciated :)
Andi
> Thanks
> Carl
> > -----Original Message-----
> > From: Andi Shyti <andi.shyti@linux.intel.com>
> > Sent: Wednesday, May 31, 2023 6:49 PM
> > To: Yang, Fei <fei.yang@intel.com>; Zhang, Carl <carl.zhang@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Vivi,
> > Rodrigo <rodrigo.vivi@intel.com>; andi.shyti@linux.intel.com; Chris Wilson
> > <chris.p.wilson@linux.intel.com>; Roper, Matthew D
> > <matthew.d.roper@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>
> > Subject: Re: [PATCH v12 1/1] drm/i915: Allow user to set cache at BO creation
> >
> > Hi Carl,
> >
> > On Wed, May 24, 2023 at 01:02:55PM -0700, fei.yang@intel.com wrote:
> > > From: Fei Yang <fei.yang@intel.com>
> > >
> > > To comply with the design that buffer objects shall have immutable
> > > cache setting through out their life cycle, {set, get}_caching ioctl's
> > > are no longer supported from MTL onward. With that change caching
> > > policy can only be set at object creation time. The current code
> > > applies a default (platform dependent) cache setting for all objects.
> > > However this is not optimal for performance tuning. The patch extends
> > > the existing gem_create uAPI to let user set PAT index for the object
> > > at creation time.
> > > The new extension is platform independent, so UMD's can switch to
> > > using this extension for older platforms as well, while {set,
> > > get}_caching are still supported on these legacy paltforms for compatibility
> > reason.
> > >
> > > BSpec: 45101
> > >
> > > Test igt@gem_create@create_ext_set_pat posted at
> > > https://patchwork.freedesktop.org/series/118314/
> > >
> > > Tested with
> > > https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22878
> > >
> > > Signed-off-by: Fei Yang <fei.yang@intel.com>
> > > Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > > Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> > > Acked-by: Jordan Justen <jordan.l.justen@intel.com>
> > > Tested-by: Jordan Justen <jordan.l.justen@intel.com>
> >
> > was it your intention to ack this patch?
> >
> > Thanks,
> > Andi
>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-05-31 12:28 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-24 20:02 [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation fei.yang
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
2023-05-24 20:02 ` [PATCH v12 1/1] " fei.yang
2023-05-24 20:02 ` [Intel-gfx] " fei.yang
2023-05-31 10:49 ` Andi Shyti
2023-05-31 10:49 ` [Intel-gfx] " Andi Shyti
2023-05-31 12:24 ` Zhang, Carl
2023-05-31 12:24 ` [Intel-gfx] " Zhang, Carl
2023-05-31 12:28 ` Andi Shyti
2023-05-31 12:28 ` [Intel-gfx] " Andi Shyti
2023-05-24 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Allow user to set cache at BO creation (rev12) Patchwork
2023-05-25 8:33 ` [Intel-gfx] [PATCH v12 0/1] drm/i915: Allow user to set cache at BO creation Tvrtko Ursulin
2023-05-25 15:12 ` Yang, Fei
2023-05-25 15:26 ` Yang, Fei
2023-05-25 15:29 ` Yang, Fei
2023-05-25 15:29 ` Yang, Fei
2023-05-25 18:33 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Allow user to set cache at BO creation (rev12) Patchwork
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