* [PATCH v3 0/2] Add the driver for Intel Keem Bay SoC timer block @ 2021-05-27 6:39 shruthi.sanil 2021-05-27 6:39 ` [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil 2021-05-27 6:39 ` [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil 0 siblings, 2 replies; 9+ messages in thread From: shruthi.sanil @ 2021-05-27 6:39 UTC (permalink / raw) To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala, lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar, shruthi.sanil From: Shruthi Sanil <shruthi.sanil@intel.com> The timer block supports 1 64-bit free running counter and 8 32-bit general purpose timers. Patch 1 holds the device tree binding documentation. Patch 2 holds the device driver. This driver is tested on the Keem Bay evaluation module board. I would like to inform that, I would be taking the ownership of this patch series from this version. Changes since v2: - Add multi timer support. - Update in the device tree binding to support multi timers. - Code optimization. Changes since v1: - Add support for KEEMBAY_TIMER to get selected through Kconfig.platforms. - Add CLOCK_EVT_FEAT_DYNIRQ as part of clockevent feature. - Avoid overlapping reg regions across 2 device nodes. - Simplify 2 device nodes as 1 because both are from same IP block. - Adapt the driver code according to the new simplified devicetree. Shruthi Sanil (2): dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer clocksource: Add Intel Keem Bay timer support .../bindings/timer/intel,keembay-timer.yaml | 180 +++++++++++++ MAINTAINERS | 5 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-keembay.c | 255 ++++++++++++++++++ 5 files changed, 452 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml create mode 100644 drivers/clocksource/timer-keembay.c base-commit: ad9f25d338605d26acedcaf3ba5fab5ca26f1c10 -- 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer 2021-05-27 6:39 [PATCH v3 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil @ 2021-05-27 6:39 ` shruthi.sanil 2021-06-02 19:21 ` Rob Herring 2021-05-27 6:39 ` [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil 1 sibling, 1 reply; 9+ messages in thread From: shruthi.sanil @ 2021-05-27 6:39 UTC (permalink / raw) To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala, lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar, shruthi.sanil From: Shruthi Sanil <shruthi.sanil@intel.com> Add Device Tree bindings for the Timer IP, which can be used as clocksource and clockevent device in the Intel Keem Bay SoC. Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> --- .../bindings/timer/intel,keembay-timer.yaml | 180 ++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml new file mode 100644 index 000000000000..e0152e19208f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay SoC Timers + +maintainers: + - Shruthi Sanil <shruthi.sanil@intel.com> + +description: | + The Intel Keem Bay timer driver supports clocksource and clockevent + features for the timer IP used in Intel Keembay SoC. + The timer block supports 1 free running counter and 8 timers. + The free running counter can be used as a clocksouce and + the timers can be used as clockevent. Each timer is capable of + generating inividual interrupt. + Both the features are enabled through the timer general config register. + + The parent node represents the common general configuration details and + the child nodes represents the counter and timers. + +properties: + reg: + description: General configuration register address and length. + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^counter@[0-9a-f]+$": + type: object + description: Properties for Intel Keem Bay counter + + properties: + compatible: + enum: + - intel,keembay-counter + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - clocks + + "^timer@[0-9a-f]+$": + type: object + description: Properties for Intel Keem Bay timer + + properties: + compatible: + enum: + - intel,keembay-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #define KEEM_BAY_A53_TIM + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + + gpt@20331000 { + reg = <0x0 0x20331000 0x0 0xc>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + counter@203300e8 { + compatible = "intel,keembay-counter"; + reg = <0x0 0x203300e8 0x0 0x8>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330010 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330010 0x0 0xc>; + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330020 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330020 0x0 0xc>; + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330030 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330030 0x0 0xc>; + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330040 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330040 0x0 0xc>; + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330050 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330050 0x0 0xc>; + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330060 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330060 0x0 0xc>; + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330070 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330070 0x0 0xc>; + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + + timer@20330080 { + compatible = "intel,keembay-timer"; + reg = <0x0 0x20330080 0x0 0xc>; + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + status = "okay"; + }; + }; + }; + +... -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer 2021-05-27 6:39 ` [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil @ 2021-06-02 19:21 ` Rob Herring 2021-06-03 11:31 ` Sanil, Shruthi 0 siblings, 1 reply; 9+ messages in thread From: Rob Herring @ 2021-06-02 19:21 UTC (permalink / raw) To: shruthi.sanil Cc: daniel.lezcano, tglx, linux-kernel, devicetree, andriy.shevchenko, kris.pan, mgross, srikanth.thokala, lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar On Thu, May 27, 2021 at 12:09:05PM +0530, shruthi.sanil@intel.com wrote: > From: Shruthi Sanil <shruthi.sanil@intel.com> > > Add Device Tree bindings for the Timer IP, which can be used as > clocksource and clockevent device in the Intel Keem Bay SoC. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > --- > .../bindings/timer/intel,keembay-timer.yaml | 180 ++++++++++++++++++ > 1 file changed, 180 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > new file mode 100644 > index 000000000000..e0152e19208f > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > @@ -0,0 +1,180 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Intel Keem Bay SoC Timers > + > +maintainers: > + - Shruthi Sanil <shruthi.sanil@intel.com> > + > +description: | > + The Intel Keem Bay timer driver supports clocksource and clockevent > + features for the timer IP used in Intel Keembay SoC. > + The timer block supports 1 free running counter and 8 timers. > + The free running counter can be used as a clocksouce and > + the timers can be used as clockevent. Each timer is capable of > + generating inividual interrupt. > + Both the features are enabled through the timer general config register. > + > + The parent node represents the common general configuration details and > + the child nodes represents the counter and timers. > + > +properties: There's no compatible, so this schema will never be applied. You need a compatible to identify what the block is. > + reg: > + description: General configuration register address and length. > + maxItems: 1 > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 Not really any reason for 64-bits of address space in the child nodes. Use a non-empty ranges. > + > + ranges: true > + > +required: > + - compatible > + - reg > + - "#address-cells" > + - "#size-cells" > + - ranges > + > +patternProperties: > + "^counter@[0-9a-f]+$": > + type: object > + description: Properties for Intel Keem Bay counter > + > + properties: > + compatible: > + enum: > + - intel,keembay-counter > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - clocks > + > + "^timer@[0-9a-f]+$": > + type: object > + description: Properties for Intel Keem Bay timer > + > + properties: > + compatible: > + enum: > + - intel,keembay-timer > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #define KEEM_BAY_A53_TIM > + > + soc { > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + > + gpt@20331000 { > + reg = <0x0 0x20331000 0x0 0xc>; > + #address-cells = <0x2>; > + #size-cells = <0x2>; > + ranges; > + > + counter@203300e8 { > + compatible = "intel,keembay-counter"; > + reg = <0x0 0x203300e8 0x0 0x8>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; Don't show status in examples. > + }; > + > + timer@20330010 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330010 0x0 0xc>; > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330020 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330020 0x0 0xc>; > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330030 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330030 0x0 0xc>; > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330040 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330040 0x0 0xc>; > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330050 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330050 0x0 0xc>; > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330060 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330060 0x0 0xc>; > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330070 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330070 0x0 0xc>; > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + > + timer@20330080 { > + compatible = "intel,keembay-timer"; > + reg = <0x0 0x20330080 0x0 0xc>; > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > + status = "okay"; > + }; > + }; > + }; > + > +... > -- > 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer 2021-06-02 19:21 ` Rob Herring @ 2021-06-03 11:31 ` Sanil, Shruthi 2021-06-08 5:45 ` Sanil, Shruthi 2021-06-08 6:13 ` Sanil, Shruthi 0 siblings, 2 replies; 9+ messages in thread From: Sanil, Shruthi @ 2021-06-03 11:31 UTC (permalink / raw) To: Rob Herring Cc: daniel.lezcano, tglx, linux-kernel, devicetree, andriy.shevchenko, kris.pan, mgross, Thokala, Srikanth, Raja Subramanian, Lakshmi Bai, Sangannavar, Mallikarjunappa Hi Rob, > -----Original Message----- > From: Rob Herring <robh@kernel.org> > Sent: Thursday, June 3, 2021 12:52 AM > To: Sanil, Shruthi <shruthi.sanil@intel.com> > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > mgross@linux.intel.com; Thokala, Srikanth <srikanth.thokala@intel.com>; > Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>; > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > Subject: Re: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem > Bay SoC Timer > > On Thu, May 27, 2021 at 12:09:05PM +0530, shruthi.sanil@intel.com wrote: > > From: Shruthi Sanil <shruthi.sanil@intel.com> > > > > Add Device Tree bindings for the Timer IP, which can be used as > > clocksource and clockevent device in the Intel Keem Bay SoC. > > > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > > --- > > .../bindings/timer/intel,keembay-timer.yaml | 180 ++++++++++++++++++ > > 1 file changed, 180 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > new file mode 100644 > > index 000000000000..e0152e19208f > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/timer/intel,keembay- > timer.yaml > > @@ -0,0 +1,180 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Intel Keem Bay SoC Timers > > + > > +maintainers: > > + - Shruthi Sanil <shruthi.sanil@intel.com> > > + > > +description: | > > + The Intel Keem Bay timer driver supports clocksource and clockevent > > + features for the timer IP used in Intel Keembay SoC. > > + The timer block supports 1 free running counter and 8 timers. > > + The free running counter can be used as a clocksouce and > > + the timers can be used as clockevent. Each timer is capable of > > + generating inividual interrupt. > > + Both the features are enabled through the timer general config register. > > + > > + The parent node represents the common general configuration details > > + and the child nodes represents the counter and timers. > > + > > +properties: > > There's no compatible, so this schema will never be applied. You need a > compatible to identify what the block is. > This is a parent block that has the common configuration register address defined which we would need during the initialization of the child nodes. This block in itself is not doing anything. We have this because, we have a common register that is required to be accessed during all the timers and counter initialization. The child nodes have the compatible string. I have validated this on the HW and see that the timer probes are being called and the timers are functional as expected. Please suggest if there is a better way to handle this scenario. > > + reg: > > + description: General configuration register address and length. > > + maxItems: 1 > > + > > + "#address-cells": > > + const: 2 > > + > > + "#size-cells": > > + const: 2 > > Not really any reason for 64-bits of address space in the child nodes. > Use a non-empty ranges. OK, I'll remove it. > > > + > > + ranges: true > > + > > +required: > > + - compatible > > + - reg > > + - "#address-cells" > > + - "#size-cells" > > + - ranges > > + > > +patternProperties: > > + "^counter@[0-9a-f]+$": > > + type: object > > + description: Properties for Intel Keem Bay counter > > + > > + properties: > > + compatible: > > + enum: > > + - intel,keembay-counter > > + > > + reg: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - clocks > > + > > + "^timer@[0-9a-f]+$": > > + type: object > > + description: Properties for Intel Keem Bay timer > > + > > + properties: > > + compatible: > > + enum: > > + - intel,keembay-timer > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + required: > > + - compatible > > + - reg > > + - interrupts > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #define KEEM_BAY_A53_TIM > > + > > + soc { > > + #address-cells = <0x2>; > > + #size-cells = <0x2>; > > + > > + gpt@20331000 { > > + reg = <0x0 0x20331000 0x0 0xc>; > > + #address-cells = <0x2>; > > + #size-cells = <0x2>; > > + ranges; > > + > > + counter@203300e8 { > > + compatible = "intel,keembay-counter"; > > + reg = <0x0 0x203300e8 0x0 0x8>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > Don't show status in examples. OK, I'll remove it. Thanks! Shruthi > > > + }; > > + > > + timer@20330010 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330010 0x0 0xc>; > > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330020 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330020 0x0 0xc>; > > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330030 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330030 0x0 0xc>; > > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330040 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330040 0x0 0xc>; > > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330050 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330050 0x0 0xc>; > > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330060 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330060 0x0 0xc>; > > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330070 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330070 0x0 0xc>; > > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + > > + timer@20330080 { > > + compatible = "intel,keembay-timer"; > > + reg = <0x0 0x20330080 0x0 0xc>; > > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > + status = "okay"; > > + }; > > + }; > > + }; > > + > > +... > > -- > > 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer 2021-06-03 11:31 ` Sanil, Shruthi @ 2021-06-08 5:45 ` Sanil, Shruthi 2021-06-08 6:13 ` Sanil, Shruthi 1 sibling, 0 replies; 9+ messages in thread From: Sanil, Shruthi @ 2021-06-08 5:45 UTC (permalink / raw) To: Rob Herring Cc: daniel.lezcano, tglx, linux-kernel, devicetree, andriy.shevchenko, kris.pan, mgross, Thokala, Srikanth, Raja Subramanian, Lakshmi Bai, Sangannavar, Mallikarjunappa Hi Rob, Could you please confirm if the existing approach is OK. This has been validated on Keem Bay evaluation HW and its working as expected. Also please suggest if we have a better way to handle this. Regards, Shruthi > -----Original Message----- > From: Sanil, Shruthi > Sent: Thursday, June 3, 2021 5:02 PM > To: 'Rob Herring' <robh@kernel.org> > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > mgross@linux.intel.com; Thokala, Srikanth <Srikanth.Thokala@intel.com>; > Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>; > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > Subject: RE: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem > Bay SoC Timer > > Hi Rob, > > > -----Original Message----- > > From: Rob Herring <robh@kernel.org> > > Sent: Thursday, June 3, 2021 12:52 AM > > To: Sanil, Shruthi <shruthi.sanil@intel.com> > > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > > kernel@vger.kernel.org; devicetree@vger.kernel.org; > > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > > mgross@linux.intel.com; Thokala, Srikanth > > <srikanth.thokala@intel.com>; Raja Subramanian, Lakshmi Bai > > <lakshmi.bai.raja.subramanian@intel.com>; > > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > > Subject: Re: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel > > Keem Bay SoC Timer > > > > On Thu, May 27, 2021 at 12:09:05PM +0530, shruthi.sanil@intel.com > wrote: > > > From: Shruthi Sanil <shruthi.sanil@intel.com> > > > > > > Add Device Tree bindings for the Timer IP, which can be used as > > > clocksource and clockevent device in the Intel Keem Bay SoC. > > > > > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > > > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > > > --- > > > .../bindings/timer/intel,keembay-timer.yaml | 180 > ++++++++++++++++++ > > > 1 file changed, 180 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > new file mode 100644 > > > index 000000000000..e0152e19208f > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/timer/intel,keembay- > > timer.yaml > > > @@ -0,0 +1,180 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Intel Keem Bay SoC Timers > > > + > > > +maintainers: > > > + - Shruthi Sanil <shruthi.sanil@intel.com> > > > + > > > +description: | > > > + The Intel Keem Bay timer driver supports clocksource and > > > +clockevent > > > + features for the timer IP used in Intel Keembay SoC. > > > + The timer block supports 1 free running counter and 8 timers. > > > + The free running counter can be used as a clocksouce and > > > + the timers can be used as clockevent. Each timer is capable of > > > + generating inividual interrupt. > > > + Both the features are enabled through the timer general config > register. > > > + > > > + The parent node represents the common general configuration > > > + details and the child nodes represents the counter and timers. > > > + > > > +properties: > > > > There's no compatible, so this schema will never be applied. You need > > a compatible to identify what the block is. > > > > This is a parent block that has the common configuration register address > defined which we would need during the initialization of the child nodes. > This block in itself is not doing anything. We have this because, we have a > common register that is required to be accessed during all the timers and > counter initialization. > The child nodes have the compatible string. > I have validated this on the HW and see that the timer probes are being > called and the timers are functional as expected. > Please suggest if there is a better way to handle this scenario. > > > > + reg: > > > + description: General configuration register address and length. > > > + maxItems: 1 > > > + > > > + "#address-cells": > > > + const: 2 > > > + > > > + "#size-cells": > > > + const: 2 > > > > Not really any reason for 64-bits of address space in the child nodes. > > Use a non-empty ranges. > > OK, I'll remove it. > > > > > > + > > > + ranges: true > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - "#address-cells" > > > + - "#size-cells" > > > + - ranges > > > + > > > +patternProperties: > > > + "^counter@[0-9a-f]+$": > > > + type: object > > > + description: Properties for Intel Keem Bay counter > > > + > > > + properties: > > > + compatible: > > > + enum: > > > + - intel,keembay-counter > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + clocks: > > > + maxItems: 1 > > > + > > > + required: > > > + - compatible > > > + - reg > > > + - clocks > > > + > > > + "^timer@[0-9a-f]+$": > > > + type: object > > > + description: Properties for Intel Keem Bay timer > > > + > > > + properties: > > > + compatible: > > > + enum: > > > + - intel,keembay-timer > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + maxItems: 1 > > > + > > > + required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - clocks > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > + #include <dt-bindings/interrupt-controller/irq.h> > > > + #define KEEM_BAY_A53_TIM > > > + > > > + soc { > > > + #address-cells = <0x2>; > > > + #size-cells = <0x2>; > > > + > > > + gpt@20331000 { > > > + reg = <0x0 0x20331000 0x0 0xc>; > > > + #address-cells = <0x2>; > > > + #size-cells = <0x2>; > > > + ranges; > > > + > > > + counter@203300e8 { > > > + compatible = "intel,keembay-counter"; > > > + reg = <0x0 0x203300e8 0x0 0x8>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > > Don't show status in examples. > > OK, I'll remove it. > > Thanks! > Shruthi > > > > > > + }; > > > + > > > + timer@20330010 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330010 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330020 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330020 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330030 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330030 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330040 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330040 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330050 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330050 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330060 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330060 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330070 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330070 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330080 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330080 0x0 0xc>; > > > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + }; > > > + }; > > > + > > > +... > > > -- > > > 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer 2021-06-03 11:31 ` Sanil, Shruthi 2021-06-08 5:45 ` Sanil, Shruthi @ 2021-06-08 6:13 ` Sanil, Shruthi 1 sibling, 0 replies; 9+ messages in thread From: Sanil, Shruthi @ 2021-06-08 6:13 UTC (permalink / raw) To: Rob Herring Cc: daniel.lezcano, tglx, linux-kernel, devicetree, andriy.shevchenko, kris.pan, mgross, Thokala, Srikanth, Raja Subramanian, Lakshmi Bai, Sangannavar, Mallikarjunappa > -----Original Message----- > From: Sanil, Shruthi > Sent: Thursday, June 3, 2021 5:02 PM > To: 'Rob Herring' <robh@kernel.org> > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > kernel@vger.kernel.org; devicetree@vger.kernel.org; > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > mgross@linux.intel.com; Thokala, Srikanth <Srikanth.Thokala@intel.com>; > Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>; > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > Subject: RE: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem > Bay SoC Timer > > Hi Rob, > > > -----Original Message----- > > From: Rob Herring <robh@kernel.org> > > Sent: Thursday, June 3, 2021 12:52 AM > > To: Sanil, Shruthi <shruthi.sanil@intel.com> > > Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; linux- > > kernel@vger.kernel.org; devicetree@vger.kernel.org; > > andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > > mgross@linux.intel.com; Thokala, Srikanth > > <srikanth.thokala@intel.com>; Raja Subramanian, Lakshmi Bai > > <lakshmi.bai.raja.subramanian@intel.com>; > > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > > Subject: Re: [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel > > Keem Bay SoC Timer > > > > On Thu, May 27, 2021 at 12:09:05PM +0530, shruthi.sanil@intel.com > wrote: > > > From: Shruthi Sanil <shruthi.sanil@intel.com> > > > > > > Add Device Tree bindings for the Timer IP, which can be used as > > > clocksource and clockevent device in the Intel Keem Bay SoC. > > > > > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > > > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > > > --- > > > .../bindings/timer/intel,keembay-timer.yaml | 180 > ++++++++++++++++++ > > > 1 file changed, 180 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > new file mode 100644 > > > index 000000000000..e0152e19208f > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/timer/intel,keembay- > > timer.yaml > > > @@ -0,0 +1,180 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Intel Keem Bay SoC Timers > > > + > > > +maintainers: > > > + - Shruthi Sanil <shruthi.sanil@intel.com> > > > + > > > +description: | > > > + The Intel Keem Bay timer driver supports clocksource and > > > +clockevent > > > + features for the timer IP used in Intel Keembay SoC. > > > + The timer block supports 1 free running counter and 8 timers. > > > + The free running counter can be used as a clocksouce and > > > + the timers can be used as clockevent. Each timer is capable of > > > + generating inividual interrupt. > > > + Both the features are enabled through the timer general config > register. > > > + > > > + The parent node represents the common general configuration > > > + details and the child nodes represents the counter and timers. > > > + > > > +properties: > > > > There's no compatible, so this schema will never be applied. You need > > a compatible to identify what the block is. > > > > This is a parent block that has the common configuration register address > defined which we would need during the initialization of the child nodes. > This block in itself is not doing anything. We have this because, we have a > common register that is required to be accessed during all the timers and > counter initialization. > The child nodes have the compatible string. > I have validated this on the HW and see that the timer probes are being > called and the timers are functional as expected. > Please suggest if there is a better way to handle this scenario. > Could you please confirm if the existing approach is OK. This has been validated on Keem Bay evaluation HW and its working as expected. Also please suggest if we have a better way to handle this. Thanks & Regards, Shruthi > > > + reg: > > > + description: General configuration register address and length. > > > + maxItems: 1 > > > + > > > + "#address-cells": > > > + const: 2 > > > + > > > + "#size-cells": > > > + const: 2 > > > > Not really any reason for 64-bits of address space in the child nodes. > > Use a non-empty ranges. > > OK, I'll remove it. > > > > > > + > > > + ranges: true > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - "#address-cells" > > > + - "#size-cells" > > > + - ranges > > > + > > > +patternProperties: > > > + "^counter@[0-9a-f]+$": > > > + type: object > > > + description: Properties for Intel Keem Bay counter > > > + > > > + properties: > > > + compatible: > > > + enum: > > > + - intel,keembay-counter > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + clocks: > > > + maxItems: 1 > > > + > > > + required: > > > + - compatible > > > + - reg > > > + - clocks > > > + > > > + "^timer@[0-9a-f]+$": > > > + type: object > > > + description: Properties for Intel Keem Bay timer > > > + > > > + properties: > > > + compatible: > > > + enum: > > > + - intel,keembay-timer > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + maxItems: 1 > > > + > > > + required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - clocks > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > + #include <dt-bindings/interrupt-controller/irq.h> > > > + #define KEEM_BAY_A53_TIM > > > + > > > + soc { > > > + #address-cells = <0x2>; > > > + #size-cells = <0x2>; > > > + > > > + gpt@20331000 { > > > + reg = <0x0 0x20331000 0x0 0xc>; > > > + #address-cells = <0x2>; > > > + #size-cells = <0x2>; > > > + ranges; > > > + > > > + counter@203300e8 { > > > + compatible = "intel,keembay-counter"; > > > + reg = <0x0 0x203300e8 0x0 0x8>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > > Don't show status in examples. > > OK, I'll remove it. > > Thanks! > Shruthi > > > > > > + }; > > > + > > > + timer@20330010 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330010 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x3 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330020 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330020 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x4 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330030 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330030 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330040 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330040 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x6 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330050 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330050 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x7 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330060 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330060 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x8 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330070 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330070 0x0 0xc>; > > > + interrupts = <GIC_SPI 0x9 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + > > > + timer@20330080 { > > > + compatible = "intel,keembay-timer"; > > > + reg = <0x0 0x20330080 0x0 0xc>; > > > + interrupts = <GIC_SPI 0xa IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; > > > + status = "okay"; > > > + }; > > > + }; > > > + }; > > > + > > > +... > > > -- > > > 2.17.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support 2021-05-27 6:39 [PATCH v3 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil 2021-05-27 6:39 ` [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil @ 2021-05-27 6:39 ` shruthi.sanil 2021-06-04 8:07 ` Daniel Lezcano 1 sibling, 1 reply; 9+ messages in thread From: shruthi.sanil @ 2021-05-27 6:39 UTC (permalink / raw) To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala, lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar, shruthi.sanil From: Shruthi Sanil <shruthi.sanil@intel.com> The Intel Keem Bay timer driver supports clocksource and clockevent features for the timer IP used in Intel Keem Bay SoC. The timer block supports 1 free running counter and 8 timers. The free running counter can be used as a clocksource and the timers can be used as clockevent. Each timer is capable of generating individual interrupt. Both the features are enabled through the timer general config register. Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> --- MAINTAINERS | 5 + drivers/clocksource/Kconfig | 11 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-keembay.c | 255 ++++++++++++++++++++++++++++ 4 files changed, 272 insertions(+) create mode 100644 drivers/clocksource/timer-keembay.c diff --git a/MAINTAINERS b/MAINTAINERS index 04babfa8fc76..73543ed60e84 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9278,6 +9278,11 @@ F: drivers/crypto/keembay/keembay-ocs-hcu-core.c F: drivers/crypto/keembay/ocs-hcu.c F: drivers/crypto/keembay/ocs-hcu.h +INTEL KEEM BAY TIMER SUPPORT +M: Shruthi Sanil <shruthi.sanil@intel.com> +S: Maintained +F: drivers/clocksource/timer-keembay.c + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler <tomas.winkler@intel.com> L: linux-kernel@vger.kernel.org diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 39aa21d01e05..08f491cf7f61 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -693,4 +693,15 @@ config MICROCHIP_PIT64B modes and high resolution. It is used as a clocksource and a clockevent. +config KEEMBAY_TIMER + bool "Intel Keem Bay timer" + depends on ARCH_KEEMBAY + select TIMER_OF + help + This option enables the support for the Intel Keem Bay + general purpose timer and free running counter driver. + Each timer can generate an individual interrupt and + supports oneshot and periodic modes. + The 64-bit counter can be used as a clock source. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index c17ee32a7151..ea319063ba47 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -88,3 +88,4 @@ obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o +obj-$(CONFIG_KEEMBAY_TIMER) += timer-keembay.o diff --git a/drivers/clocksource/timer-keembay.c b/drivers/clocksource/timer-keembay.c new file mode 100644 index 000000000000..e62187eeb4f6 --- /dev/null +++ b/drivers/clocksource/timer-keembay.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Keem Bay Timer driver + * + * Copyright (C) 2020 Intel Corporation + */ + +#include <linux/bitops.h> +#include <linux/idr.h> +#include <linux/interrupt.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/sizes.h> +#include <linux/slab.h> + +#include "timer-of.h" + +/* Timer register offset */ +#define TIM_CNT_VAL_OFFSET 0x0 +#define TIM_RELOAD_VAL_OFFSET 0x4 +#define TIM_CONFIG_OFFSET 0x8 + +/* Bit fields of timer general config register */ +#define TIM_CONFIG_PRESCALER_ENABLE BIT(2) +#define TIM_CONFIG_COUNTER_ENABLE BIT(0) + +/* Bit fields of timer config register */ +#define TIM_CONFIG_INTERRUPT_PENDING BIT(4) +#define TIM_CONFIG_INTERRUPT_ENABLE BIT(2) +#define TIM_CONFIG_RESTART BIT(1) +#define TIM_CONFIG_ENABLE BIT(0) + +#define TIM_GEN_MASK GENMASK(31, 12) +#define TIM_RATING 200 +#define TIM_CLKSRC_MASK_BITS 64 + +#define TIMER_NAME_SIZE 25 + +/* Provides a unique ID for each timer */ +static DEFINE_IDA(keembay_timer_ida); + +static inline void keembay_timer_enable(void __iomem *base, u32 flags) +{ + writel(TIM_CONFIG_ENABLE | flags, base + TIM_CONFIG_OFFSET); +} + +static inline void keembay_timer_disable(void __iomem *base) +{ + writel(0x0, base + TIM_CONFIG_OFFSET); +} + +static inline void keembay_timer_update_counter(void __iomem *base, u32 val) +{ + writel(val, base + TIM_CNT_VAL_OFFSET); + writel(val, base + TIM_RELOAD_VAL_OFFSET); +} + +static inline void keembay_timer_clear_pending_int(void __iomem *base) +{ + u32 val; + + val = readl(base + TIM_CONFIG_OFFSET); + val &= ~TIM_CONFIG_INTERRUPT_PENDING; + writel(val, base + TIM_CONFIG_OFFSET); +} + +static int keembay_timer_set_next_event(unsigned long evt, struct clock_event_device *ce) +{ + u32 flags = TIM_CONFIG_INTERRUPT_ENABLE; + struct timer_of *to = to_timer_of(ce); + void __iomem *tim_base = timer_of_base(to); + + keembay_timer_disable(tim_base); + keembay_timer_update_counter(tim_base, evt); + keembay_timer_enable(tim_base, flags); + + return 0; +} + +static int keembay_timer_periodic(struct clock_event_device *ce) +{ + u32 flags = TIM_CONFIG_INTERRUPT_ENABLE | TIM_CONFIG_RESTART; + struct timer_of *to = to_timer_of(ce); + void __iomem *tim_base = timer_of_base(to); + + keembay_timer_disable(tim_base); + keembay_timer_update_counter(tim_base, timer_of_period(to)); + keembay_timer_enable(tim_base, flags); + + return 0; +} + +static int keembay_timer_shutdown(struct clock_event_device *ce) +{ + struct timer_of *to = to_timer_of(ce); + + keembay_timer_disable(timer_of_base(to)); + + return 0; +} + +static irqreturn_t keembay_timer_isr(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + struct timer_of *to = to_timer_of(evt); + void __iomem *tim_base = timer_of_base(to); + u32 val; + + val = readl(tim_base + TIM_CONFIG_OFFSET); + + if (val & TIM_CONFIG_RESTART) { + /* Clear interrupt for periodic timer*/ + keembay_timer_clear_pending_int(tim_base); + } else { + /* Disable the timer for one shot timer */ + keembay_timer_disable(tim_base); + } + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static int __init keembay_clockevent_init(struct device_node *np) +{ + struct device_node *gpt_node = np->parent; + struct timer_of *keembay_ce_to; + void __iomem *gpt_base; + char *timer_name; + int timer_id; + int ret; + u32 val; + + gpt_base = of_iomap(gpt_node, 0); + if (!gpt_base) { + pr_err("%pOF: Failed to get general config base address\n", np); + return -ENXIO; + } + + /* Prescaler must be enabled for the timer to operate */ + val = readl(gpt_base + TIM_CONFIG_OFFSET); + if (!(val & TIM_CONFIG_PRESCALER_ENABLE)) { + pr_err("%pOF: Prescaler is not enabled\n", np); + ret = -ENODEV; + goto err_iounmap; + } + + keembay_ce_to = kzalloc(sizeof(*keembay_ce_to), GFP_KERNEL); + if (!keembay_ce_to) { + ret = -ENOMEM; + goto err_iounmap; + } + + timer_id = ida_alloc(&keembay_timer_ida, GFP_KERNEL); + if (timer_id < 0) { + ret = timer_id; + goto err_keembay_ce_to_free; + } + + timer_name = kasprintf(GFP_KERNEL, "keembay_timer%d", timer_id); + if (!timer_name) { + ret = -ENOMEM; + goto err_free_ida; + } + + keembay_ce_to->flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK; + keembay_ce_to->clkevt.name = timer_name; + keembay_ce_to->clkevt.cpumask = cpumask_of(0); + keembay_ce_to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ; + keembay_ce_to->clkevt.rating = TIM_RATING; + keembay_ce_to->clkevt.set_next_event = keembay_timer_set_next_event; + keembay_ce_to->clkevt.set_state_periodic = keembay_timer_periodic; + keembay_ce_to->clkevt.set_state_shutdown = keembay_timer_shutdown; + keembay_ce_to->of_irq.handler = keembay_timer_isr; + keembay_ce_to->of_irq.flags = IRQF_TIMER; + + ret = timer_of_init(np, keembay_ce_to); + if (ret) + goto err_timer_name_free; + + val = readl(gpt_base + TIM_RELOAD_VAL_OFFSET); + iounmap(gpt_base); + + keembay_ce_to->of_clk.rate = keembay_ce_to->of_clk.rate / (val + 1); + + clockevents_config_and_register(&keembay_ce_to->clkevt, + timer_of_rate(keembay_ce_to), + 1, + U32_MAX); + + return 0; + +err_timer_name_free: + kfree(timer_name); +err_free_ida: + ida_free(&keembay_timer_ida, timer_id); +err_keembay_ce_to_free: + kfree(keembay_ce_to); +err_iounmap: + iounmap(gpt_base); + + return ret; +} + +static struct timer_of keembay_cs_to = { + .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, +}; + +static u64 notrace keembay_clocksource_read(struct clocksource *cs) +{ + return lo_hi_readq(timer_of_base(&keembay_cs_to)); +} + +static struct clocksource keembay_counter = { + .name = "keembay_sys_counter", + .rating = TIM_RATING, + .read = keembay_clocksource_read, + .mask = CLOCKSOURCE_MASK(TIM_CLKSRC_MASK_BITS), + .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_SUSPEND_NONSTOP, +}; + +static int __init keembay_clocksource_init(struct device_node *np) +{ + struct device_node *gpt_node = np->parent; + void __iomem *gpt_base; + u32 val; + int ret; + + gpt_base = of_iomap(gpt_node, 0); + if (!gpt_base) { + pr_err("%pOF: Failed to get general config base address\n", np); + return -ENXIO; + } + + /* Free Running Counter must be enabled */ + val = readl(gpt_base + TIM_CONFIG_OFFSET); + iounmap(gpt_base); + if (!(val & TIM_CONFIG_COUNTER_ENABLE)) { + pr_err("%pOF: free running counter is not enabled\n", np); + return -ENODEV; + } + + ret = timer_of_init(np, &keembay_cs_to); + if (ret) + return ret; + + return clocksource_register_hz(&keembay_counter, timer_of_rate(&keembay_cs_to)); +} + +TIMER_OF_DECLARE(keembay_clockevent, "intel,keembay-timer", keembay_clockevent_init); +TIMER_OF_DECLARE(keembay_clocksource, "intel,keembay-counter", keembay_clocksource_init); -- 2.17.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support 2021-05-27 6:39 ` [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil @ 2021-06-04 8:07 ` Daniel Lezcano 2021-06-04 9:19 ` Sanil, Shruthi 0 siblings, 1 reply; 9+ messages in thread From: Daniel Lezcano @ 2021-06-04 8:07 UTC (permalink / raw) To: shruthi.sanil, tglx, robh+dt, linux-kernel, devicetree Cc: andriy.shevchenko, kris.pan, mgross, srikanth.thokala, lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar On 27/05/2021 08:39, shruthi.sanil@intel.com wrote: > From: Shruthi Sanil <shruthi.sanil@intel.com> > > The Intel Keem Bay timer driver supports clocksource and clockevent > features for the timer IP used in Intel Keem Bay SoC. > The timer block supports 1 free running counter and 8 timers. > The free running counter can be used as a clocksource and > the timers can be used as clockevent. Each timer is capable of > generating individual interrupt. > Both the features are enabled through the timer general config register. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > --- > MAINTAINERS | 5 + > drivers/clocksource/Kconfig | 11 ++ > drivers/clocksource/Makefile | 1 + > drivers/clocksource/timer-keembay.c | 255 ++++++++++++++++++++++++++++ > 4 files changed, 272 insertions(+) > create mode 100644 drivers/clocksource/timer-keembay.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 04babfa8fc76..73543ed60e84 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -9278,6 +9278,11 @@ F: drivers/crypto/keembay/keembay-ocs-hcu-core.c > F: drivers/crypto/keembay/ocs-hcu.c > F: drivers/crypto/keembay/ocs-hcu.h > > +INTEL KEEM BAY TIMER SUPPORT > +M: Shruthi Sanil <shruthi.sanil@intel.com> > +S: Maintained > +F: drivers/clocksource/timer-keembay.c > + > INTEL MANAGEMENT ENGINE (mei) > M: Tomas Winkler <tomas.winkler@intel.com> > L: linux-kernel@vger.kernel.org > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index 39aa21d01e05..08f491cf7f61 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -693,4 +693,15 @@ config MICROCHIP_PIT64B > modes and high resolution. It is used as a clocksource > and a clockevent. > > +config KEEMBAY_TIMER > + bool "Intel Keem Bay timer" > + depends on ARCH_KEEMBAY > + select TIMER_OF Please refer to the other timer option to see how we create silent option. We want the Kconfig's platform to select the timer, not the user except for compilation coverage or expert mode. > + help > + This option enables the support for the Intel Keem Bay > + general purpose timer and free running counter driver. > + Each timer can generate an individual interrupt and > + supports oneshot and periodic modes. > + The 64-bit counter can be used as a clock source. > + > endmenu Other than that, LGTM. Thanks -- Daniel -- <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog ^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support 2021-06-04 8:07 ` Daniel Lezcano @ 2021-06-04 9:19 ` Sanil, Shruthi 0 siblings, 0 replies; 9+ messages in thread From: Sanil, Shruthi @ 2021-06-04 9:19 UTC (permalink / raw) To: Daniel Lezcano, tglx, robh+dt, linux-kernel, devicetree Cc: andriy.shevchenko, kris.pan, mgross, Thokala, Srikanth, Raja Subramanian, Lakshmi Bai, Sangannavar, Mallikarjunappa Hi Daniel, > -----Original Message----- > From: Daniel Lezcano <daniel.lezcano@linaro.org> > Sent: Friday, June 4, 2021 1:37 PM > To: Sanil, Shruthi <shruthi.sanil@intel.com>; tglx@linutronix.de; > robh+dt@kernel.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org > Cc: andriy.shevchenko@linux.intel.com; kris.pan@linux.intel.com; > mgross@linux.intel.com; Thokala, Srikanth <srikanth.thokala@intel.com>; > Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>; > Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com> > Subject: Re: [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support > > On 27/05/2021 08:39, shruthi.sanil@intel.com wrote: > > From: Shruthi Sanil <shruthi.sanil@intel.com> > > > > The Intel Keem Bay timer driver supports clocksource and clockevent > > features for the timer IP used in Intel Keem Bay SoC. > > The timer block supports 1 free running counter and 8 timers. > > The free running counter can be used as a clocksource and the timers > > can be used as clockevent. Each timer is capable of generating > > individual interrupt. > > Both the features are enabled through the timer general config register. > > > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> > > Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com> > > --- > > MAINTAINERS | 5 + > > drivers/clocksource/Kconfig | 11 ++ > > drivers/clocksource/Makefile | 1 + > > drivers/clocksource/timer-keembay.c | 255 > > ++++++++++++++++++++++++++++ > > 4 files changed, 272 insertions(+) > > create mode 100644 drivers/clocksource/timer-keembay.c > > > > diff --git a/MAINTAINERS b/MAINTAINERS index > > 04babfa8fc76..73543ed60e84 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -9278,6 +9278,11 @@ F: drivers/crypto/keembay/keembay-ocs-hcu- > core.c > > F: drivers/crypto/keembay/ocs-hcu.c > > F: drivers/crypto/keembay/ocs-hcu.h > > > > +INTEL KEEM BAY TIMER SUPPORT > > +M: Shruthi Sanil <shruthi.sanil@intel.com> > > +S: Maintained > > +F: drivers/clocksource/timer-keembay.c > > + > > INTEL MANAGEMENT ENGINE (mei) > > M: Tomas Winkler <tomas.winkler@intel.com> > > L: linux-kernel@vger.kernel.org > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > > index 39aa21d01e05..08f491cf7f61 100644 > > --- a/drivers/clocksource/Kconfig > > +++ b/drivers/clocksource/Kconfig > > @@ -693,4 +693,15 @@ config MICROCHIP_PIT64B > > modes and high resolution. It is used as a clocksource > > and a clockevent. > > > > +config KEEMBAY_TIMER > > + bool "Intel Keem Bay timer" > > + depends on ARCH_KEEMBAY > > + select TIMER_OF > > Please refer to the other timer option to see how we create silent option. We > want the Kconfig's platform to select the timer, not the user except for > compilation coverage or expert mode. OK, I'll check and update accordingly. Thanks, Shruthi > > > + help > > + This option enables the support for the Intel Keem Bay > > + general purpose timer and free running counter driver. > > + Each timer can generate an individual interrupt and > > + supports oneshot and periodic modes. > > + The 64-bit counter can be used as a clock source. > > + > > endmenu > > Other than that, LGTM. > > Thanks > -- Daniel > > > -- > <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs > > Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | > <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro- > blog/> Blog ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-06-08 6:13 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-05-27 6:39 [PATCH v3 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil 2021-05-27 6:39 ` [PATCH v3 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil 2021-06-02 19:21 ` Rob Herring 2021-06-03 11:31 ` Sanil, Shruthi 2021-06-08 5:45 ` Sanil, Shruthi 2021-06-08 6:13 ` Sanil, Shruthi 2021-05-27 6:39 ` [PATCH v3 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil 2021-06-04 8:07 ` Daniel Lezcano 2021-06-04 9:19 ` Sanil, Shruthi
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