[SPDK] Re: DIF/DIX acceleration in SPDK

* [SPDK] Re: DIF/DIX acceleration in SPDK
@ 2020-06-12 21:34 Luse, Paul E
  0 siblings, 0 replies; 10+ messages in thread
From: Luse, Paul E @ 2020-06-12 21:34 UTC (permalink / raw)
  To: spdk

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Thanks Shuhei! After talking to Jim some more, I think for this release we’ll get the capability into the acceleration engine but if/how we use it through the rest of the SPDK stack is likely going to require enough experimentation that next release is a better target.  I’ll let you know when the capabilities are in there as I’m totally counting on your help to help make use of it when the time comes ☺

Thx
Paul

From: 松本周平 <shuheimatsumoto(a)gmail.com>
Sent: Friday, June 12, 2020 6:45 AM
To: Storage Performance Development Kit <spdk(a)lists.01.org>
Subject: [SPDK] Re: DIF/DIX acceleration in SPDK

Hi Paul,

Current NVMe-oF target and iSCSI target have used special SGL when reading from network or writing to network.
When reading from network, leave a metadata space per block by special SGL and then compute and fill DIF to metadata spaces.
When writing to network, compute and check DIF to metadata spaces, and then ignore a DIF space per block by special SGL.

Special SGL means that each SGL entry maps a single block and there is a metadata space between two SGL entries.

The major reason why we used special SGL was to avoid data copy between two buffers.

So, DIF check and DIF update will be helpful first.

The limitation that SGL is not supported will be acceptable first.
iSCSI target uses only a single contiguous buffer.
NVMe-oF target also can use only a single contiguous buffer by adjusting maximum IO size.

Another thing I want to share is that SPDK sock layer improved performance greatly recently, and this may conflict with
the current DIF implementation especially for the performance.

So in future, using DIF insert and DIF strip may be better for NVMe-TCP target and iSCSI target.
When NVMe-TCP target or iSCSI target use DIF insert and DIF strip, they prepare two buffers for each read or write, and copy with DIF insertion or strip.

So all DIF check, update, insert , and strip will be usable anyway.

One difficulty to emulate SGL by DSA is boundary.
To compute DIF for a single block which spans multiple SGL entries, it is necessary to compute CRC for the first partial block and then use the CRC as the seed value for the second partial block, and so on.

I don't think my feedback is enough, and so I'm fine for your any further question or feedback.

Thanks,
Shuhei

On Fri, Jun 12, 2020 at 12:46 AM Luse, Paul E <paul.e.luse(a)intel.com<mailto:paul.e.luse(a)intel.com>> wrote:
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Hi Everyone,

This is primarily for Shuhei but please feel free, anyone, to respond ☺

Adding support for Intel’s next generation offload engine is going well (Note, the feature is not available in HW yet, I’m using a simulator to do dev/test). Currently support exists, or is about to land on master, for:

Copy, fill, dual-cast, CRC32C, compare and the ability to submit batches of commands.

Currently these are only being used by a new tool in /examples/accel/perf but once they all land and I’ve added some more tests, we’ll start using them in SPDK modules – the most notable uses will be for CRC32C 9iscsi) and DIF/DIX throughout the stack.  There will be other uses (compare, fill, copy, etc) as well but those are the big ones.

I’ve just now started looking at DIF/DIX and have determined that using these within SPDK won’t be quite as straightforward as some of the others. I’ll explain what I’m thinking after briefly summering the DSA DIF/DIX functions (more detail is available in the public spec at https://software.intel.com/content/www/us/en/develop/download/intel-data-streaming-accelerator-preliminary-architecture-specification.html)

Note: there is no SGL support in any of these, all are single src and/or dst:

  *   DIF Check: The DIF Check operation computes the Data Integrity Field (DIF) on the source data and compares the computed DIF to the DIF contained in the source data.
  *   DIF Insert: The DIF Insert operation copies memory from the Source Address to the Destination Address, while computing the Data Integrity Field (DIF) on the source data and inserting the DIF into the output data.
  *   DIF Strip: The DIF Strip operation copies memory from the Source Address to the Destination Address, removing the Data Integrity Field (DIF). It optionally computes the DIF on the source data and compares the computed DIF to the DIF contained in the source data.
  *   DIF Update: The DIF Update operation copies memory from the Source Address to the Destination Address. It optionally computes the Data Integrity Field (DIF) on the source data and compares the computed DIF to the DIF contained in the data. It simultaneously computes the DIF on the source data using Destination DIF fields in the descriptor and inserts the computed DIF into the output data.

Upon initial review of the relatively complex implementation of DIF?DIX we have in SPDK I have the following observations that I’m hoping to get some feedback on:

  *   It looks like we require SGL in most if not all cases. I can go through them one by one but wanted to get an initial feel mainly from Shuhei on how lack of SGL support impacts our ability to use DIF?DIX offload w/DSA before I start adding support ☺
  *   With the exception of DIF Check, all of the DSA functions include a copy (I can only assume they figured a use case where they are moving data from a host buffer into a different memory subsystem in prep for DMA’ing to disk).  It looks like most if not all of our calculations are done on fixed buffers. I see a few copy functions in diff.c but I don’t see them used anywhere

I’m almost thinking the DSA functions are too “simple” for our current implementation but wonder if there’s some refactoring we can do to make use of them. I don’t know if the DSA CRC32C engine calculates the same exact CRC as the DIF/DIX functions but if so (I can verify) at a minum maybe use just accelerate the CRCs called from funcs within diff.c

Thoughts? We can chat in a community meeting soon too but email might be easier to get us all on the amge page first.

Thanks!!
Paul

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