* [PATCH 0/9] PSP cleanup
@ 2019-01-02 9:21 Evan Quan
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
*** BLURB HERE ***
Evan Quan (9):
drm/amdgpu: separate the PSP ring related APIs
drm/amdgpu: separate commonly used PSP APIs
drm/amdgpu: separate the xgmi related APIs
drm/amdgpu: separate the tmr related APIs
drm/amdgpu: separate the asd related APIs
drm/amdgpu: drop useless PSP APIs and structures
drm/amdgpu: check PSP support before adding the ip block
drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable
drm/amdgpu: move psp_funcs related to a more proper place
drivers/gpu/drm/amd/amdgpu/Makefile | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 504 +++-------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 93 +---
drivers/gpu/drm/amd/amdgpu/psp_asd.c | 86 ++++
drivers/gpu/drm/amd/amdgpu/psp_asd.h | 32 ++
drivers/gpu/drm/amd/amdgpu/psp_cmn.c | 289 +++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 84 ++++
drivers/gpu/drm/amd/amdgpu/psp_funcs.h | 98 +++++
drivers/gpu/drm/amd/amdgpu/psp_ring.c | 354 ++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_ring.h | 43 ++
drivers/gpu/drm/amd/amdgpu/psp_tmr.c | 84 ++++
drivers/gpu/drm/amd/amdgpu/psp_tmr.h | 32 ++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
drivers/gpu/drm/amd/amdgpu/psp_xgmi.c | 207 +++++++++
drivers/gpu/drm/amd/amdgpu/psp_xgmi.h | 33 ++
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +-
18 files changed, 1493 insertions(+), 1866 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_funcs.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/9] drm/amdgpu: separate the PSP ring related APIs
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 2/9] drm/amdgpu: separate commonly used PSP APIs Evan Quan
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
So that they can be shared among different PSP generations.
And there is no need to have one copy for each PSP generation.
Change-Id: I7a97f410ef5993b25f0ec3cfac4a293073d697c3
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 71 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 16 +-
drivers/gpu/drm/amd/amdgpu/psp_ring.c | 353 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_ring.h | 43 +++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 247 +----------------
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 278 +------------------
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 231 +---------------
8 files changed, 444 insertions(+), 798 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 007478905c7b..bdcf0d4338f8 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -90,7 +90,8 @@ amdgpu-y += \
amdgpu_psp.o \
psp_v3_1.o \
psp_v10_0.o \
- psp_v11_0.o
+ psp_v11_0.o \
+ psp_ring.o
# add SMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8189a90637f7..38398f0c10c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -33,6 +33,21 @@
#include "psp_v10_0.h"
#include "psp_v11_0.h"
+#define psp_ring_init(psp, type) \
+ (psp)->funcs->ring_init((psp), (type))
+#define psp_ring_create(psp, type) \
+ (psp)->funcs->ring_create((psp), (type))
+#define psp_ring_stop(psp, type) \
+ (psp)->funcs->ring_stop((psp), (type))
+#define psp_ring_destroy(psp, type) \
+ ((psp)->funcs->ring_destroy((psp), (type)))
+#define psp_prep_cmd_buf(ucode, cmd) \
+ (psp)->funcs->prep_cmd_buf((ucode), (cmd))
+#define psp_submit_cmd_buf(psp, ucode, cmd, fence_mc) \
+ (psp)->funcs->submit_cmd_buf((psp), (ucode), (cmd), (fence_mc))
+#define psp_support_vmr_ring(psp) \
+ ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
+
static void psp_set_funcs(struct amdgpu_device *adev);
static int psp_early_init(void *handle)
@@ -117,50 +132,6 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
return -ETIME;
}
-static int
-psp_cmd_submit_buf(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
-{
- int ret;
- int index;
-
- memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
-
- memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
-
- index = atomic_inc_return(&psp->fence_value);
- ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
- fence_mc_addr, index);
- if (ret) {
- atomic_dec(&psp->fence_value);
- return ret;
- }
-
- while (*((unsigned int *)psp->fence_buf) != index)
- msleep(1);
-
- /* the status field must be 0 after psp command completion */
- if (psp->cmd_buf_mem->resp.status) {
- if (ucode)
- DRM_ERROR("failed to load ucode id (%d) ",
- ucode->ucode_id);
- DRM_ERROR("psp command failed and response status is (%d)\n",
- psp->cmd_buf_mem->resp.status);
- return -EINVAL;
- }
-
- /* get xGMI session id from response buffer */
- cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
-
- if (ucode) {
- ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
- ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
- }
-
- return ret;
-}
-
static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
struct psp_gfx_cmd_resp *cmd,
uint64_t tmr_mc, uint32_t size)
@@ -206,7 +177,7 @@ static int psp_tmr_load(struct psp_context *psp)
DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
PSP_TMR_SIZE, psp->tmr_mc_addr);
- ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ ret = psp_submit_cmd_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr);
if (ret)
goto failed;
@@ -273,7 +244,7 @@ static int psp_asd_load(struct psp_context *psp)
psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
- ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ ret = psp_submit_cmd_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr);
kfree(cmd);
@@ -334,7 +305,7 @@ static int psp_xgmi_load(struct psp_context *psp)
psp->xgmi_context.xgmi_shared_mc_addr,
psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
- ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ ret = psp_submit_cmd_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr);
if (!ret) {
@@ -371,7 +342,7 @@ static int psp_xgmi_unload(struct psp_context *psp)
psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
- ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ ret = psp_submit_cmd_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr);
kfree(cmd);
@@ -407,7 +378,7 @@ int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
psp->xgmi_context.session_id);
- ret = psp_cmd_submit_buf(psp, NULL, cmd,
+ ret = psp_submit_cmd_buf(psp, NULL, cmd,
psp->fence_buf_mc_addr);
kfree(cmd);
@@ -526,7 +497,7 @@ static int psp_np_fw_load(struct psp_context *psp)
if (ret)
return ret;
- ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
+ ret = psp_submit_cmd_buf(psp, ucode, psp->cmd,
psp->fence_buf_mc_addr);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 3ee573b4016e..c94fa444f8b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -74,10 +74,9 @@ struct psp_funcs
enum psp_ring_type ring_type);
int (*ring_destroy)(struct psp_context *psp,
enum psp_ring_type ring_type);
- int (*cmd_submit)(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
- int index);
+ int (*submit_cmd_buf)(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr);
bool (*compare_sram_data)(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
@@ -176,13 +175,6 @@ struct psp_xgmi_topology_info {
struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
};
-#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
-#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
-#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
-#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
-#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
-#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
- (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
#define psp_compare_sram_data(psp, ucode, type) \
(psp)->funcs->compare_sram_data((psp), (ucode), (type))
#define psp_init_microcode(psp) \
@@ -193,8 +185,6 @@ struct psp_xgmi_topology_info {
((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
#define psp_smu_reload_quirk(psp) \
((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
-#define psp_support_vmr_ring(psp) \
- ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
#define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
#define psp_xgmi_get_node_id(psp, node_id) \
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_ring.c b/drivers/gpu/drm/amd/amdgpu/psp_ring.c
new file mode 100644
index 000000000000..c2f1ade51758
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_ring.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "psp_ring.h"
+#include "soc15_common.h"
+#include "mp/mp_11_0_offset.h"
+#include "mp/mp_11_0_sh_mask.h"
+
+int psp_ring_init_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ ring = &psp->km_ring;
+
+ ring->ring_type = ring_type;
+
+ /* allocate 4k Page of Local Frame Buffer memory for ring */
+ ring->ring_size = 0x1000;
+ ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &adev->firmware.rbuf,
+ &ring->ring_mem_mc_addr,
+ (void **)&ring->ring_mem);
+ if (ret) {
+ ring->ring_size = 0;
+ return ret;
+ }
+
+ return 0;
+}
+
+bool psp_ring_support_vmr(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+
+ if ((adev->asic_type == CHIP_VEGA20) &&
+ amdgpu_sriov_vf(adev) &&
+ psp->sos_fw_version > 0x80045)
+ return true;
+
+ return false;
+}
+
+int psp_ring_create_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ unsigned int psp_ring_reg = 0;
+ struct psp_ring *ring = &psp->km_ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ if (psp_ring_support_vmr(psp)) {
+ /* Write low address of the ring to C2PMSG_102 */
+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
+ /* Write high address of the ring to C2PMSG_103 */
+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
+
+ /* Write the ring initialization command to C2PMSG_101 */
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+ GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
+
+ /* there might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) in C2PMSG_101 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+ 0x80000000, 0x8000FFFF, false);
+
+ } else {
+ /* Write low address of the ring to C2PMSG_69 */
+ psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
+ /* Write high address of the ring to C2PMSG_70 */
+ psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
+ /* Write size of ring to C2PMSG_71 */
+ psp_ring_reg = ring->ring_size;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
+ /* Write the ring initialization command to C2PMSG_64 */
+ psp_ring_reg = ring_type;
+ psp_ring_reg = psp_ring_reg << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+ /* there might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) in C2PMSG_64 */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x80000000, 0x8000FFFF, false);
+ }
+
+ return ret;
+}
+
+int psp_ring_stop_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct amdgpu_device *adev = psp->adev;
+
+ /* Write the ring destroy command*/
+ if (psp_ring_support_vmr(psp))
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
+ GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
+ else
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
+ GFX_CTRL_CMD_ID_DESTROY_RINGS);
+
+ /* there might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ /* Wait for response flag (bit 31) */
+ if (psp_ring_support_vmr(psp))
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+ 0x80000000, 0x80000000, false);
+ else
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ 0x80000000, 0x80000000, false);
+
+ return ret;
+}
+
+int psp_ring_destroy_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type)
+{
+ int ret = 0;
+ struct psp_ring *ring = &psp->km_ring;
+ struct amdgpu_device *adev = psp->adev;
+
+ ret = psp_ring_stop_ring(psp, ring_type);
+ if (ret)
+ DRM_ERROR("Fail to stop psp ring\n");
+
+ amdgpu_bo_free_kernel(&adev->firmware.rbuf,
+ &ring->ring_mem_mc_addr,
+ (void **)&ring->ring_mem);
+
+ return ret;
+}
+
+static int
+psp_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
+{
+ switch (ucode->ucode_id) {
+ case AMDGPU_UCODE_ID_SDMA0:
+ *type = GFX_FW_TYPE_SDMA0;
+ break;
+ case AMDGPU_UCODE_ID_SDMA1:
+ *type = GFX_FW_TYPE_SDMA1;
+ break;
+ case AMDGPU_UCODE_ID_CP_CE:
+ *type = GFX_FW_TYPE_CP_CE;
+ break;
+ case AMDGPU_UCODE_ID_CP_PFP:
+ *type = GFX_FW_TYPE_CP_PFP;
+ break;
+ case AMDGPU_UCODE_ID_CP_ME:
+ *type = GFX_FW_TYPE_CP_ME;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC1:
+ *type = GFX_FW_TYPE_CP_MEC;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC1_JT:
+ *type = GFX_FW_TYPE_CP_MEC_ME1;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC2:
+ *type = GFX_FW_TYPE_CP_MEC;
+ break;
+ case AMDGPU_UCODE_ID_CP_MEC2_JT:
+ *type = GFX_FW_TYPE_CP_MEC_ME2;
+ break;
+ case AMDGPU_UCODE_ID_RLC_G:
+ *type = GFX_FW_TYPE_RLC_G;
+ break;
+ case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
+ *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
+ break;
+ case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
+ *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
+ break;
+ case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
+ *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
+ break;
+ case AMDGPU_UCODE_ID_SMC:
+ *type = GFX_FW_TYPE_SMU;
+ break;
+ case AMDGPU_UCODE_ID_UVD:
+ *type = GFX_FW_TYPE_UVD;
+ break;
+ case AMDGPU_UCODE_ID_UVD1:
+ *type = GFX_FW_TYPE_UVD1;
+ break;
+ case AMDGPU_UCODE_ID_VCE:
+ *type = GFX_FW_TYPE_VCE;
+ break;
+ case AMDGPU_UCODE_ID_VCN:
+ *type = GFX_FW_TYPE_VCN;
+ break;
+ case AMDGPU_UCODE_ID_DMCU_ERAM:
+ *type = GFX_FW_TYPE_DMCU_ERAM;
+ break;
+ case AMDGPU_UCODE_ID_DMCU_INTV:
+ *type = GFX_FW_TYPE_DMCU_ISR;
+ break;
+ case AMDGPU_UCODE_ID_MAXIMUM:
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int psp_ring_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd)
+{
+ int ret;
+ uint64_t fw_mem_mc_addr = ucode->mc_addr;
+
+ memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
+
+ cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
+ cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
+ cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
+ cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
+
+ ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
+ if (ret)
+ DRM_ERROR("Unknown firmware type\n");
+
+ return ret;
+}
+
+static int psp_cmd_submit(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
+ int index)
+{
+ unsigned int psp_write_ptr_reg = 0;
+ struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
+ struct psp_ring *ring = &psp->km_ring;
+ struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
+ struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
+ ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t ring_size_dw = ring->ring_size / 4;
+ uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
+
+ /* KM (GPCOM) prepare write pointer */
+ if (psp_ring_support_vmr(psp))
+ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
+ else
+ psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
+
+ /* Update KM RB frame pointer to new frame */
+ /* write_frame ptr increments by size of rb_frame in bytes */
+ /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
+ if ((psp_write_ptr_reg % ring_size_dw) == 0)
+ write_frame = ring_buffer_start;
+ else
+ write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
+ /* Check invalid write_frame ptr address */
+ if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
+ DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
+ ring_buffer_start, ring_buffer_end, write_frame);
+ DRM_ERROR("write_frame is pointing to address out of bounds\n");
+ return -EINVAL;
+ }
+
+ /* Initialize KM RB frame */
+ memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
+
+ /* Update KM RB frame */
+ write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+ write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+ write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+ write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
+ write_frame->fence_value = index;
+
+ /* Update the write Pointer in DWORDs */
+ psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
+ if (psp_ring_support_vmr(psp)) {
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
+ } else
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
+
+ return 0;
+}
+
+int
+psp_ring_submit_cmd_buf(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
+{
+ int ret;
+ int index;
+
+ memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
+
+ memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
+
+ index = atomic_inc_return(&psp->fence_value);
+ ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
+ fence_mc_addr, index);
+ if (ret) {
+ atomic_dec(&psp->fence_value);
+ return ret;
+ }
+
+ while (*((unsigned int *)psp->fence_buf) != index)
+ msleep(1);
+
+ /* the status field must be 0 after FW is loaded */
+ if (ucode && psp->cmd_buf_mem->resp.status) {
+ DRM_ERROR("failed loading with status (%d) and ucode id (%d)\n",
+ psp->cmd_buf_mem->resp.status, ucode->ucode_id);
+ return -EINVAL;
+ }
+
+ /* get xGMI session id from response buffer */
+ cmd->resp.session_id = psp->cmd_buf_mem->resp.session_id;
+
+ if (ucode) {
+ ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
+ ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_ring.h b/drivers/gpu/drm/amd/amdgpu/psp_ring.h
new file mode 100644
index 000000000000..ff7d988f175d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_ring.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __PSP_RING_H
+#define __PSP_RING_H
+
+#include "amdgpu_psp.h"
+
+int psp_ring_init_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+int psp_ring_create_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+int psp_ring_stop_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+int psp_ring_destroy_ring(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+int psp_ring_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd);
+int psp_ring_submit_cmd_buf(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr);
+bool psp_ring_support_vmr(struct psp_context *psp);
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index d78b4306a36f..700a766751fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -33,80 +33,12 @@
#include "mp/mp_10_0_offset.h"
#include "gc/gc_9_1_offset.h"
#include "sdma0/sdma0_4_1_offset.h"
+#include "psp_ring.h"
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
MODULE_FIRMWARE("amdgpu/raven2_asd.bin");
-static int
-psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
-{
- switch(ucode->ucode_id) {
- case AMDGPU_UCODE_ID_SDMA0:
- *type = GFX_FW_TYPE_SDMA0;
- break;
- case AMDGPU_UCODE_ID_SDMA1:
- *type = GFX_FW_TYPE_SDMA1;
- break;
- case AMDGPU_UCODE_ID_CP_CE:
- *type = GFX_FW_TYPE_CP_CE;
- break;
- case AMDGPU_UCODE_ID_CP_PFP:
- *type = GFX_FW_TYPE_CP_PFP;
- break;
- case AMDGPU_UCODE_ID_CP_ME:
- *type = GFX_FW_TYPE_CP_ME;
- break;
- case AMDGPU_UCODE_ID_CP_MEC1:
- *type = GFX_FW_TYPE_CP_MEC;
- break;
- case AMDGPU_UCODE_ID_CP_MEC1_JT:
- *type = GFX_FW_TYPE_CP_MEC_ME1;
- break;
- case AMDGPU_UCODE_ID_CP_MEC2:
- *type = GFX_FW_TYPE_CP_MEC;
- break;
- case AMDGPU_UCODE_ID_CP_MEC2_JT:
- *type = GFX_FW_TYPE_CP_MEC_ME2;
- break;
- case AMDGPU_UCODE_ID_RLC_G:
- *type = GFX_FW_TYPE_RLC_G;
- break;
- case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
- *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
- break;
- case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
- *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
- break;
- case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
- *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
- break;
- case AMDGPU_UCODE_ID_SMC:
- *type = GFX_FW_TYPE_SMU;
- break;
- case AMDGPU_UCODE_ID_UVD:
- *type = GFX_FW_TYPE_UVD;
- break;
- case AMDGPU_UCODE_ID_VCE:
- *type = GFX_FW_TYPE_VCE;
- break;
- case AMDGPU_UCODE_ID_VCN:
- *type = GFX_FW_TYPE_VCN;
- break;
- case AMDGPU_UCODE_ID_DMCU_ERAM:
- *type = GFX_FW_TYPE_DMCU_ERAM;
- break;
- case AMDGPU_UCODE_ID_DMCU_INTV:
- *type = GFX_FW_TYPE_DMCU_ISR;
- break;
- case AMDGPU_UCODE_ID_MAXIMUM:
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
static int psp_v10_0_init_microcode(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@@ -158,171 +90,6 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
return err;
}
-static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
- struct psp_gfx_cmd_resp *cmd)
-{
- int ret;
- uint64_t fw_mem_mc_addr = ucode->mc_addr;
-
- memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
-
- cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
- cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
-
- ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
- if (ret)
- DRM_ERROR("Unknown firmware type\n");
-
- return ret;
-}
-
-static int psp_v10_0_ring_init(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct psp_ring *ring;
- struct amdgpu_device *adev = psp->adev;
-
- ring = &psp->km_ring;
-
- ring->ring_type = ring_type;
-
- /* allocate 4k Page of Local Frame Buffer memory for ring */
- ring->ring_size = 0x1000;
- ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &adev->firmware.rbuf,
- &ring->ring_mem_mc_addr,
- (void **)&ring->ring_mem);
- if (ret) {
- ring->ring_size = 0;
- return ret;
- }
-
- return 0;
-}
-
-static int psp_v10_0_ring_create(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- unsigned int psp_ring_reg = 0;
- struct psp_ring *ring = &psp->km_ring;
- struct amdgpu_device *adev = psp->adev;
-
- /* Write low address of the ring to C2PMSG_69 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_70 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
- /* Write size of ring to C2PMSG_71 */
- psp_ring_reg = ring->ring_size;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
- /* Write the ring initialization command to C2PMSG_64 */
- psp_ring_reg = ring_type;
- psp_ring_reg = psp_ring_reg << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-
- /* There might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x8000FFFF, false);
-
- return ret;
-}
-
-static int psp_v10_0_ring_stop(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- unsigned int psp_ring_reg = 0;
- struct amdgpu_device *adev = psp->adev;
-
- /* Write the ring destroy command to C2PMSG_64 */
- psp_ring_reg = 3 << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-
- /* There might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x80000000, false);
-
- return ret;
-}
-
-static int psp_v10_0_ring_destroy(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct psp_ring *ring = &psp->km_ring;
- struct amdgpu_device *adev = psp->adev;
-
- ret = psp_v10_0_ring_stop(psp, ring_type);
- if (ret)
- DRM_ERROR("Fail to stop psp ring\n");
-
- amdgpu_bo_free_kernel(&adev->firmware.rbuf,
- &ring->ring_mem_mc_addr,
- (void **)&ring->ring_mem);
-
- return ret;
-}
-
-static int psp_v10_0_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
- int index)
-{
- unsigned int psp_write_ptr_reg = 0;
- struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
- struct psp_ring *ring = &psp->km_ring;
- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
- struct amdgpu_device *adev = psp->adev;
- uint32_t ring_size_dw = ring->ring_size / 4;
- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
- /* KM (GPCOM) prepare write pointer */
- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
- /* Update KM RB frame pointer to new frame */
- if ((psp_write_ptr_reg % ring_size_dw) == 0)
- write_frame = ring_buffer_start;
- else
- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
- /* Check invalid write_frame ptr address */
- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
- ring_buffer_start, ring_buffer_end, write_frame);
- DRM_ERROR("write_frame is pointing to address out of bounds\n");
- return -EINVAL;
- }
-
- /* Initialize KM RB frame */
- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
- /* Update KM RB frame */
- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
- write_frame->fence_value = index;
-
- /* Update the write Pointer in DWORDs */
- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
- return 0;
-}
-
static int
psp_v10_0_sram_map(struct amdgpu_device *adev,
unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -454,12 +221,12 @@ static int psp_v10_0_mode1_reset(struct psp_context *psp)
static const struct psp_funcs psp_v10_0_funcs = {
.init_microcode = psp_v10_0_init_microcode,
- .prep_cmd_buf = psp_v10_0_prep_cmd_buf,
- .ring_init = psp_v10_0_ring_init,
- .ring_create = psp_v10_0_ring_create,
- .ring_stop = psp_v10_0_ring_stop,
- .ring_destroy = psp_v10_0_ring_destroy,
- .cmd_submit = psp_v10_0_cmd_submit,
+ .ring_init = psp_ring_init_ring,
+ .ring_create = psp_ring_create_ring,
+ .ring_stop = psp_ring_stop_ring,
+ .ring_destroy = psp_ring_destroy_ring,
+ .prep_cmd_buf = psp_ring_prep_cmd_buf,
+ .submit_cmd_buf = psp_ring_submit_cmd_buf,
.compare_sram_data = psp_v10_0_compare_sram_data,
.mode1_reset = psp_v10_0_mode1_reset,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0c6e7f9b143f..43487d97a0cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -32,6 +32,7 @@
#include "gc/gc_9_0_offset.h"
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h"
+#include "psp_ring.h"
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
@@ -40,60 +41,6 @@ MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
/* address block */
#define smnMP1_FIRMWARE_FLAGS 0x3010024
-static int
-psp_v11_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
-{
- switch (ucode->ucode_id) {
- case AMDGPU_UCODE_ID_SDMA0:
- *type = GFX_FW_TYPE_SDMA0;
- break;
- case AMDGPU_UCODE_ID_SDMA1:
- *type = GFX_FW_TYPE_SDMA1;
- break;
- case AMDGPU_UCODE_ID_CP_CE:
- *type = GFX_FW_TYPE_CP_CE;
- break;
- case AMDGPU_UCODE_ID_CP_PFP:
- *type = GFX_FW_TYPE_CP_PFP;
- break;
- case AMDGPU_UCODE_ID_CP_ME:
- *type = GFX_FW_TYPE_CP_ME;
- break;
- case AMDGPU_UCODE_ID_CP_MEC1:
- *type = GFX_FW_TYPE_CP_MEC;
- break;
- case AMDGPU_UCODE_ID_CP_MEC1_JT:
- *type = GFX_FW_TYPE_CP_MEC_ME1;
- break;
- case AMDGPU_UCODE_ID_CP_MEC2:
- *type = GFX_FW_TYPE_CP_MEC;
- break;
- case AMDGPU_UCODE_ID_CP_MEC2_JT:
- *type = GFX_FW_TYPE_CP_MEC_ME2;
- break;
- case AMDGPU_UCODE_ID_RLC_G:
- *type = GFX_FW_TYPE_RLC_G;
- break;
- case AMDGPU_UCODE_ID_SMC:
- *type = GFX_FW_TYPE_SMU;
- break;
- case AMDGPU_UCODE_ID_UVD:
- *type = GFX_FW_TYPE_UVD;
- break;
- case AMDGPU_UCODE_ID_VCE:
- *type = GFX_FW_TYPE_VCE;
- break;
- case AMDGPU_UCODE_ID_UVD1:
- *type = GFX_FW_TYPE_UVD1;
- break;
- case AMDGPU_UCODE_ID_MAXIMUM:
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
static int psp_v11_0_init_microcode(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@@ -267,215 +214,6 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
return ret;
}
-static int psp_v11_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
- struct psp_gfx_cmd_resp *cmd)
-{
- int ret;
- uint64_t fw_mem_mc_addr = ucode->mc_addr;
-
- memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
-
- cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
- cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
-
- ret = psp_v11_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
- if (ret)
- DRM_ERROR("Unknown firmware type\n");
-
- return ret;
-}
-
-static int psp_v11_0_ring_init(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct psp_ring *ring;
- struct amdgpu_device *adev = psp->adev;
-
- ring = &psp->km_ring;
-
- ring->ring_type = ring_type;
-
- /* allocate 4k Page of Local Frame Buffer memory for ring */
- ring->ring_size = 0x1000;
- ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &adev->firmware.rbuf,
- &ring->ring_mem_mc_addr,
- (void **)&ring->ring_mem);
- if (ret) {
- ring->ring_size = 0;
- return ret;
- }
-
- return 0;
-}
-
-static bool psp_v11_0_support_vmr_ring(struct psp_context *psp)
-{
- if (amdgpu_sriov_vf(psp->adev) && psp->sos_fw_version > 0x80045)
- return true;
- return false;
-}
-
-static int psp_v11_0_ring_create(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- unsigned int psp_ring_reg = 0;
- struct psp_ring *ring = &psp->km_ring;
- struct amdgpu_device *adev = psp->adev;
-
- if (psp_v11_0_support_vmr_ring(psp)) {
- /* Write low address of the ring to C2PMSG_102 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_103 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
-
- /* Write the ring initialization command to C2PMSG_101 */
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
- GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) in C2PMSG_101 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
- 0x80000000, 0x8000FFFF, false);
-
- } else {
- /* Write low address of the ring to C2PMSG_69 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_70 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
- /* Write size of ring to C2PMSG_71 */
- psp_ring_reg = ring->ring_size;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
- /* Write the ring initialization command to C2PMSG_64 */
- psp_ring_reg = ring_type;
- psp_ring_reg = psp_ring_reg << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x8000FFFF, false);
- }
-
- return ret;
-}
-
-static int psp_v11_0_ring_stop(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct amdgpu_device *adev = psp->adev;
-
- /* Write the ring destroy command*/
- if (psp_v11_0_support_vmr_ring(psp))
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
- GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
- else
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
- GFX_CTRL_CMD_ID_DESTROY_RINGS);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) */
- if (psp_v11_0_support_vmr_ring(psp))
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
- 0x80000000, 0x80000000, false);
- else
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x80000000, false);
-
- return ret;
-}
-
-static int psp_v11_0_ring_destroy(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct psp_ring *ring = &psp->km_ring;
- struct amdgpu_device *adev = psp->adev;
-
- ret = psp_v11_0_ring_stop(psp, ring_type);
- if (ret)
- DRM_ERROR("Fail to stop psp ring\n");
-
- amdgpu_bo_free_kernel(&adev->firmware.rbuf,
- &ring->ring_mem_mc_addr,
- (void **)&ring->ring_mem);
-
- return ret;
-}
-
-static int psp_v11_0_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
- int index)
-{
- unsigned int psp_write_ptr_reg = 0;
- struct psp_gfx_rb_frame *write_frame = psp->km_ring.ring_mem;
- struct psp_ring *ring = &psp->km_ring;
- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
- struct amdgpu_device *adev = psp->adev;
- uint32_t ring_size_dw = ring->ring_size / 4;
- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
- /* KM (GPCOM) prepare write pointer */
- if (psp_v11_0_support_vmr_ring(psp))
- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
- else
- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
- /* Update KM RB frame pointer to new frame */
- /* write_frame ptr increments by size of rb_frame in bytes */
- /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
- if ((psp_write_ptr_reg % ring_size_dw) == 0)
- write_frame = ring_buffer_start;
- else
- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
- /* Check invalid write_frame ptr address */
- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
- ring_buffer_start, ring_buffer_end, write_frame);
- DRM_ERROR("write_frame is pointing to address out of bounds\n");
- return -EINVAL;
- }
-
- /* Initialize KM RB frame */
- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
- /* Update KM RB frame */
- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
- write_frame->fence_value = index;
-
- /* Update the write Pointer in DWORDs */
- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
- if (psp_v11_0_support_vmr_ring(psp)) {
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_write_ptr_reg);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
- } else
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
- return 0;
-}
-
static int
psp_v11_0_sram_map(struct amdgpu_device *adev,
unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -753,19 +491,19 @@ static const struct psp_funcs psp_v11_0_funcs = {
.init_microcode = psp_v11_0_init_microcode,
.bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
.bootloader_load_sos = psp_v11_0_bootloader_load_sos,
- .prep_cmd_buf = psp_v11_0_prep_cmd_buf,
- .ring_init = psp_v11_0_ring_init,
- .ring_create = psp_v11_0_ring_create,
- .ring_stop = psp_v11_0_ring_stop,
- .ring_destroy = psp_v11_0_ring_destroy,
- .cmd_submit = psp_v11_0_cmd_submit,
+ .ring_init = psp_ring_init_ring,
+ .ring_create = psp_ring_create_ring,
+ .ring_stop = psp_ring_stop_ring,
+ .ring_destroy = psp_ring_destroy_ring,
+ .prep_cmd_buf = psp_ring_prep_cmd_buf,
+ .submit_cmd_buf = psp_ring_submit_cmd_buf,
+ .support_vmr_ring = psp_ring_support_vmr,
.compare_sram_data = psp_v11_0_compare_sram_data,
.mode1_reset = psp_v11_0_mode1_reset,
.xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
.xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
.xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
.xgmi_get_node_id = psp_v11_0_xgmi_get_node_id,
- .support_vmr_ring = psp_v11_0_support_vmr_ring,
};
void psp_v11_0_set_psp_funcs(struct psp_context *psp)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 79694ff16969..b74dd556a573 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -36,6 +36,7 @@
#include "gc/gc_9_0_offset.h"
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_6_1_offset.h"
+#include "psp_ring.h"
MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
@@ -47,57 +48,6 @@ MODULE_FIRMWARE("amdgpu/vega12_asd.bin");
static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554};
-static int
-psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
-{
- switch(ucode->ucode_id) {
- case AMDGPU_UCODE_ID_SDMA0:
- *type = GFX_FW_TYPE_SDMA0;
- break;
- case AMDGPU_UCODE_ID_SDMA1:
- *type = GFX_FW_TYPE_SDMA1;
- break;
- case AMDGPU_UCODE_ID_CP_CE:
- *type = GFX_FW_TYPE_CP_CE;
- break;
- case AMDGPU_UCODE_ID_CP_PFP:
- *type = GFX_FW_TYPE_CP_PFP;
- break;
- case AMDGPU_UCODE_ID_CP_ME:
- *type = GFX_FW_TYPE_CP_ME;
- break;
- case AMDGPU_UCODE_ID_CP_MEC1:
- *type = GFX_FW_TYPE_CP_MEC;
- break;
- case AMDGPU_UCODE_ID_CP_MEC1_JT:
- *type = GFX_FW_TYPE_CP_MEC_ME1;
- break;
- case AMDGPU_UCODE_ID_CP_MEC2:
- *type = GFX_FW_TYPE_CP_MEC;
- break;
- case AMDGPU_UCODE_ID_CP_MEC2_JT:
- *type = GFX_FW_TYPE_CP_MEC_ME2;
- break;
- case AMDGPU_UCODE_ID_RLC_G:
- *type = GFX_FW_TYPE_RLC_G;
- break;
- case AMDGPU_UCODE_ID_SMC:
- *type = GFX_FW_TYPE_SMU;
- break;
- case AMDGPU_UCODE_ID_UVD:
- *type = GFX_FW_TYPE_UVD;
- break;
- case AMDGPU_UCODE_ID_VCE:
- *type = GFX_FW_TYPE_VCE;
- break;
- case AMDGPU_UCODE_ID_MAXIMUM:
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
static int psp_v3_1_init_microcode(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@@ -277,173 +227,6 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
return ret;
}
-static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
- struct psp_gfx_cmd_resp *cmd)
-{
- int ret;
- uint64_t fw_mem_mc_addr = ucode->mc_addr;
-
- memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
-
- cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
- cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
- cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
-
- ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
- if (ret)
- DRM_ERROR("Unknown firmware type\n");
-
- return ret;
-}
-
-static int psp_v3_1_ring_init(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct psp_ring *ring;
- struct amdgpu_device *adev = psp->adev;
-
- ring = &psp->km_ring;
-
- ring->ring_type = ring_type;
-
- /* allocate 4k Page of Local Frame Buffer memory for ring */
- ring->ring_size = 0x1000;
- ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &adev->firmware.rbuf,
- &ring->ring_mem_mc_addr,
- (void **)&ring->ring_mem);
- if (ret) {
- ring->ring_size = 0;
- return ret;
- }
-
- return 0;
-}
-
-static int psp_v3_1_ring_create(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- unsigned int psp_ring_reg = 0;
- struct psp_ring *ring = &psp->km_ring;
- struct amdgpu_device *adev = psp->adev;
-
- /* Write low address of the ring to C2PMSG_69 */
- psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
- /* Write high address of the ring to C2PMSG_70 */
- psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
- /* Write size of ring to C2PMSG_71 */
- psp_ring_reg = ring->ring_size;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
- /* Write the ring initialization command to C2PMSG_64 */
- psp_ring_reg = ring_type;
- psp_ring_reg = psp_ring_reg << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x8000FFFF, false);
-
- return ret;
-}
-
-static int psp_v3_1_ring_stop(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- unsigned int psp_ring_reg = 0;
- struct amdgpu_device *adev = psp->adev;
-
- /* Write the ring destroy command to C2PMSG_64 */
- psp_ring_reg = 3 << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- /* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
- 0x80000000, 0x80000000, false);
-
- return ret;
-}
-
-static int psp_v3_1_ring_destroy(struct psp_context *psp,
- enum psp_ring_type ring_type)
-{
- int ret = 0;
- struct psp_ring *ring = &psp->km_ring;
- struct amdgpu_device *adev = psp->adev;
-
- ret = psp_v3_1_ring_stop(psp, ring_type);
- if (ret)
- DRM_ERROR("Fail to stop psp ring\n");
-
- amdgpu_bo_free_kernel(&adev->firmware.rbuf,
- &ring->ring_mem_mc_addr,
- (void **)&ring->ring_mem);
-
- return ret;
-}
-
-static int psp_v3_1_cmd_submit(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
- int index)
-{
- unsigned int psp_write_ptr_reg = 0;
- struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
- struct psp_ring *ring = &psp->km_ring;
- struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
- struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
- ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
- struct amdgpu_device *adev = psp->adev;
- uint32_t ring_size_dw = ring->ring_size / 4;
- uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
-
- /* KM (GPCOM) prepare write pointer */
- psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
-
- /* Update KM RB frame pointer to new frame */
- /* write_frame ptr increments by size of rb_frame in bytes */
- /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
- if ((psp_write_ptr_reg % ring_size_dw) == 0)
- write_frame = ring_buffer_start;
- else
- write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
- /* Check invalid write_frame ptr address */
- if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
- DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
- ring_buffer_start, ring_buffer_end, write_frame);
- DRM_ERROR("write_frame is pointing to address out of bounds\n");
- return -EINVAL;
- }
-
- /* Initialize KM RB frame */
- memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
-
- /* Update KM RB frame */
- write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
- write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
- write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
- write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
- write_frame->fence_value = index;
-
- /* Update the write Pointer in DWORDs */
- psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
-
- return 0;
-}
-
static int
psp_v3_1_sram_map(struct amdgpu_device *adev,
unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
@@ -615,12 +398,12 @@ static const struct psp_funcs psp_v3_1_funcs = {
.init_microcode = psp_v3_1_init_microcode,
.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
- .prep_cmd_buf = psp_v3_1_prep_cmd_buf,
- .ring_init = psp_v3_1_ring_init,
- .ring_create = psp_v3_1_ring_create,
- .ring_stop = psp_v3_1_ring_stop,
- .ring_destroy = psp_v3_1_ring_destroy,
- .cmd_submit = psp_v3_1_cmd_submit,
+ .ring_init = psp_ring_init_ring,
+ .ring_create = psp_ring_create_ring,
+ .ring_stop = psp_ring_stop_ring,
+ .ring_destroy = psp_ring_destroy_ring,
+ .prep_cmd_buf = psp_ring_prep_cmd_buf,
+ .submit_cmd_buf = psp_ring_submit_cmd_buf,
.compare_sram_data = psp_v3_1_compare_sram_data,
.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
.mode1_reset = psp_v3_1_mode1_reset,
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/9] drm/amdgpu: separate commonly used PSP APIs
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-01-02 9:21 ` [PATCH 1/9] drm/amdgpu: separate the PSP ring related APIs Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 3/9] drm/amdgpu: separate the xgmi related APIs Evan Quan
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
So that they can be shared in PSP widely.
Change-Id: Icec5d23db2c1f8241f6bdff371e6cde65ffdb101
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 36 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 16 --
drivers/gpu/drm/amd/amdgpu/psp_cmn.c | 289 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 41 ++++
drivers/gpu/drm/amd/amdgpu/psp_ring.c | 9 +-
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 126 +----------
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 250 +-------------------
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 243 +-------------------
9 files changed, 366 insertions(+), 647 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index bdcf0d4338f8..fe27d6038da9 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -91,7 +91,8 @@ amdgpu-y += \
psp_v3_1.o \
psp_v10_0.o \
psp_v11_0.o \
- psp_ring.o
+ psp_ring.o \
+ psp_cmn.o
# add SMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 38398f0c10c9..d1ccc6ea7607 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -47,6 +47,20 @@
(psp)->funcs->submit_cmd_buf((psp), (ucode), (cmd), (fence_mc))
#define psp_support_vmr_ring(psp) \
((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
+#define psp_compare_sram_data(psp, ucode, type) \
+ (psp)->funcs->compare_sram_data((psp), (ucode), (type))
+#define psp_init_microcode(psp) \
+ ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
+#define psp_bootloader_load_sysdrv(psp) \
+ ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
+#define psp_bootloader_load_sos(psp) \
+ ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
+#define psp_smu_reload_quirk(psp) \
+ ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
+#define psp_mode1_reset(psp) \
+ ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
+#define amdgpu_psp_check_fw_loading_status(adev, i) \
+ (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
static void psp_set_funcs(struct amdgpu_device *adev);
@@ -110,28 +124,6 @@ static int psp_sw_fini(void *handle)
return 0;
}
-int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
- uint32_t reg_val, uint32_t mask, bool check_changed)
-{
- uint32_t val;
- int i;
- struct amdgpu_device *adev = psp->adev;
-
- for (i = 0; i < adev->usec_timeout; i++) {
- val = RREG32(reg_index);
- if (check_changed) {
- if (val != reg_val)
- return 0;
- } else {
- if ((val & mask) == reg_val)
- return 0;
- }
- udelay(1);
- }
-
- return -ETIME;
-}
-
static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
struct psp_gfx_cmd_resp *cmd,
uint64_t tmr_mc, uint32_t size)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index c94fa444f8b7..f4438a5077b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -175,18 +175,6 @@ struct psp_xgmi_topology_info {
struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
};
-#define psp_compare_sram_data(psp, ucode, type) \
- (psp)->funcs->compare_sram_data((psp), (ucode), (type))
-#define psp_init_microcode(psp) \
- ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
-#define psp_bootloader_load_sysdrv(psp) \
- ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
-#define psp_bootloader_load_sos(psp) \
- ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
-#define psp_smu_reload_quirk(psp) \
- ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
-#define psp_mode1_reset(psp) \
- ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
#define psp_xgmi_get_node_id(psp, node_id) \
((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
#define psp_xgmi_get_hive_id(psp, hive_id) \
@@ -198,13 +186,9 @@ struct psp_xgmi_topology_info {
((psp)->funcs->xgmi_set_topology_info ? \
(psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
-#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
-
extern const struct amd_ip_funcs psp_ip_funcs;
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
-extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
- uint32_t field_val, uint32_t mask, bool check_changed);
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_cmn.c b/drivers/gpu/drm/amd/amdgpu/psp_cmn.c
new file mode 100644
index 000000000000..6a614c7e3b70
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_cmn.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "psp_cmn.h"
+#include "soc15_common.h"
+#include "mp/mp_11_0_offset.h"
+#include "mp/mp_11_0_sh_mask.h"
+#include "gc/gc_9_2_1_offset.h"
+#include "sdma0/sdma0_4_2_offset.h"
+
+int psp_cmn_wait_for(struct psp_context *psp, uint32_t reg_index,
+ uint32_t reg_val, uint32_t mask, bool check_changed)
+{
+ uint32_t val;
+ int i;
+ struct amdgpu_device *adev = psp->adev;
+
+ for (i = 0; i < adev->usec_timeout; i++) {
+ val = RREG32(reg_index);
+ if (check_changed) {
+ if (val != reg_val)
+ return 0;
+ } else {
+ if ((val & mask) == reg_val)
+ return 0;
+ }
+ udelay(1);
+ }
+
+ return -ETIME;
+}
+
+int psp_cmn_mode1_reset(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t offset;
+ int ret;
+
+ offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
+
+ ret = psp_cmn_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
+ if (ret) {
+ DRM_ERROR("psp is not working correctly before mode1 reset!\n");
+ return -EINVAL;
+ }
+
+ /*send the mode 1 reset command*/
+ WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
+
+ msleep(500);
+
+ offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
+
+ ret = psp_cmn_wait_for(psp, offset, 0x80000000, 0x80000000, false);
+ if (ret) {
+ DRM_ERROR("psp mode 1 reset failed!\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+psp_cmn_sram_map(struct amdgpu_device *adev,
+ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
+ unsigned int *sram_data_reg_offset,
+ enum AMDGPU_UCODE_ID ucode_id)
+{
+ int ret = 0;
+
+ switch(ucode_id) {
+/* TODO: needs to confirm */
+#if 0
+ case AMDGPU_UCODE_ID_SMC:
+ *sram_offset = 0;
+ *sram_addr_reg_offset = 0;
+ *sram_data_reg_offset = 0;
+ break;
+#endif
+
+ case AMDGPU_UCODE_ID_CP_CE:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_PFP:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_ME:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_MEC1:
+ *sram_offset = 0x10000;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_CP_MEC2:
+ *sram_offset = 0x10000;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_RLC_G:
+ *sram_offset = 0x2000;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
+ break;
+
+ case AMDGPU_UCODE_ID_SDMA0:
+ *sram_offset = 0x0;
+ *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
+ *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
+ break;
+
+/* TODO: needs to confirm */
+#if 0
+ case AMDGPU_UCODE_ID_SDMA1:
+ *sram_offset = ;
+ *sram_addr_reg_offset = ;
+ break;
+
+ case AMDGPU_UCODE_ID_UVD:
+ *sram_offset = ;
+ *sram_addr_reg_offset = ;
+ break;
+
+ case AMDGPU_UCODE_ID_VCE:
+ *sram_offset = ;
+ *sram_addr_reg_offset = ;
+ break;
+#endif
+
+ case AMDGPU_UCODE_ID_MAXIMUM:
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+bool psp_cmn_compare_sram_data(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ enum AMDGPU_UCODE_ID ucode_type)
+{
+ int err = 0;
+ unsigned int fw_sram_reg_val = 0;
+ unsigned int fw_sram_addr_reg_offset = 0;
+ unsigned int fw_sram_data_reg_offset = 0;
+ unsigned int ucode_size;
+ uint32_t *ucode_mem = NULL;
+ struct amdgpu_device *adev = psp->adev;
+
+ err = psp_cmn_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
+ &fw_sram_data_reg_offset, ucode_type);
+ if (err)
+ return false;
+
+ WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
+
+ ucode_size = ucode->ucode_size;
+ ucode_mem = (uint32_t *)ucode->kaddr;
+ while (!ucode_size) {
+ fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
+
+ if (*ucode_mem != fw_sram_reg_val)
+ return false;
+
+ ucode_mem++;
+ /* 4 bytes */
+ ucode_size -= 4;
+ }
+
+ return true;
+}
+
+int psp_cmn_bootloader_load_sysdrv(struct psp_context *psp)
+{
+ int ret;
+ uint32_t psp_gfxdrv_command_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t sol_reg;
+
+ /* Check sOS sign of life register to confirm sys driver and sOS
+ * are already been loaded.
+ */
+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+ if (sol_reg) {
+ psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
+ printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
+ return 0;
+ }
+
+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x80000000, 0x80000000, false);
+ if (ret)
+ return ret;
+
+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+ /* Copy PSP System Driver binary to memory */
+ memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
+
+ /* Provide the sys driver to bootloader */
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+ (uint32_t)(psp->fw_pri_mc_addr >> 20));
+ psp_gfxdrv_command_reg = 1 << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
+ psp_gfxdrv_command_reg);
+
+ /* there might be handshake issue with hardware which needs delay */
+ mdelay(20);
+
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x80000000, 0x80000000, false);
+
+ return ret;
+}
+
+int psp_cmn_bootloader_load_sos(struct psp_context *psp)
+{
+ int ret;
+ unsigned int psp_gfxdrv_command_reg = 0;
+ struct amdgpu_device *adev = psp->adev;
+ uint32_t sol_reg;
+
+ /* Check sOS sign of life register to confirm sys driver and sOS
+ * are already been loaded.
+ */
+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+ if (sol_reg)
+ return 0;
+
+ /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+ 0x80000000, 0x80000000, false);
+ if (ret)
+ return ret;
+
+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+
+ /* Copy Secure OS binary to PSP memory */
+ memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
+
+ /* Provide the PSP secure OS to bootloader */
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
+ (uint32_t)(psp->fw_pri_mc_addr >> 20));
+ psp_gfxdrv_command_reg = 2 << 16;
+ WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
+ psp_gfxdrv_command_reg);
+
+ /* there might be handshake issue with hardware which needs delay */
+ mdelay(20);
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
+ RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
+ 0, true);
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_cmn.h b/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
new file mode 100644
index 000000000000..a1c0ad0bce72
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PSP_CMN_H
+#define __PSP_CMN_H
+
+#include "amdgpu_psp.h"
+
+int psp_cmn_mode1_reset(struct psp_context *psp);
+
+bool psp_cmn_compare_sram_data(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ enum AMDGPU_UCODE_ID ucode_type);
+
+int psp_cmn_bootloader_load_sysdrv(struct psp_context *psp);
+
+int psp_cmn_bootloader_load_sos(struct psp_context *psp);
+
+int psp_cmn_wait_for(struct psp_context *psp, uint32_t reg_index,
+ uint32_t reg_val, uint32_t mask, bool check_changed);
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_ring.c b/drivers/gpu/drm/amd/amdgpu/psp_ring.c
index c2f1ade51758..fa59e57fb11e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_ring.c
@@ -24,6 +24,7 @@
#include "soc15_common.h"
#include "mp/mp_11_0_offset.h"
#include "mp/mp_11_0_sh_mask.h"
+#include "psp_cmn.h"
int psp_ring_init_ring(struct psp_context *psp,
enum psp_ring_type ring_type)
@@ -87,7 +88,7 @@ int psp_ring_create_ring(struct psp_context *psp,
mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_101 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0x80000000, 0x8000FFFF, false);
} else {
@@ -109,7 +110,7 @@ int psp_ring_create_ring(struct psp_context *psp,
mdelay(20);
/* Wait for response flag (bit 31) in C2PMSG_64 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x8000FFFF, false);
}
@@ -135,10 +136,10 @@ int psp_ring_stop_ring(struct psp_context *psp,
/* Wait for response flag (bit 31) */
if (psp_ring_support_vmr(psp))
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
0x80000000, 0x80000000, false);
else
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+ ret = psp_cmn_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x80000000, false);
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 700a766751fa..87d9560a52ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -34,6 +34,7 @@
#include "gc/gc_9_1_offset.h"
#include "sdma0/sdma0_4_1_offset.h"
#include "psp_ring.h"
+#include "psp_cmn.h"
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
@@ -90,129 +91,6 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
return err;
}
-static int
-psp_v10_0_sram_map(struct amdgpu_device *adev,
- unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
- unsigned int *sram_data_reg_offset,
- enum AMDGPU_UCODE_ID ucode_id)
-{
- int ret = 0;
-
- switch(ucode_id) {
-/* TODO: needs to confirm */
-#if 0
- case AMDGPU_UCODE_ID_SMC:
- *sram_offset = 0;
- *sram_addr_reg_offset = 0;
- *sram_data_reg_offset = 0;
- break;
-#endif
-
- case AMDGPU_UCODE_ID_CP_CE:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_PFP:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_ME:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_MEC1:
- *sram_offset = 0x10000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_MEC2:
- *sram_offset = 0x10000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_RLC_G:
- *sram_offset = 0x2000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_SDMA0:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
- break;
-
-/* TODO: needs to confirm */
-#if 0
- case AMDGPU_UCODE_ID_SDMA1:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-
- case AMDGPU_UCODE_ID_UVD:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-
- case AMDGPU_UCODE_ID_VCE:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-#endif
-
- case AMDGPU_UCODE_ID_MAXIMUM:
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- enum AMDGPU_UCODE_ID ucode_type)
-{
- int err = 0;
- unsigned int fw_sram_reg_val = 0;
- unsigned int fw_sram_addr_reg_offset = 0;
- unsigned int fw_sram_data_reg_offset = 0;
- unsigned int ucode_size;
- uint32_t *ucode_mem = NULL;
- struct amdgpu_device *adev = psp->adev;
-
- err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
- &fw_sram_data_reg_offset, ucode_type);
- if (err)
- return false;
-
- WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
-
- ucode_size = ucode->ucode_size;
- ucode_mem = (uint32_t *)ucode->kaddr;
- while (!ucode_size) {
- fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
-
- if (*ucode_mem != fw_sram_reg_val)
- return false;
-
- ucode_mem++;
- /* 4 bytes */
- ucode_size -= 4;
- }
-
- return true;
-}
-
-
static int psp_v10_0_mode1_reset(struct psp_context *psp)
{
DRM_INFO("psp mode 1 reset not supported now! \n");
@@ -227,7 +105,7 @@ static const struct psp_funcs psp_v10_0_funcs = {
.ring_destroy = psp_ring_destroy_ring,
.prep_cmd_buf = psp_ring_prep_cmd_buf,
.submit_cmd_buf = psp_ring_submit_cmd_buf,
- .compare_sram_data = psp_v10_0_compare_sram_data,
+ .compare_sram_data = psp_cmn_compare_sram_data,
.mode1_reset = psp_v10_0_mode1_reset,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 43487d97a0cd..1dc62ec4e64b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -33,6 +33,7 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h"
#include "psp_ring.h"
+#include "psp_cmn.h"
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
@@ -129,247 +130,6 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
return err;
}
-static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
-{
- int ret;
- uint32_t psp_gfxdrv_command_reg = 0;
- struct amdgpu_device *adev = psp->adev;
- uint32_t sol_reg;
-
- /* Check sOS sign of life register to confirm sys driver and sOS
- * are already been loaded.
- */
- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
- if (sol_reg) {
- psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
- printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
- return 0;
- }
-
- /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
- 0x80000000, 0x80000000, false);
- if (ret)
- return ret;
-
- memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
- /* Copy PSP System Driver binary to memory */
- memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
-
- /* Provide the sys driver to bootloader */
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
- (uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 1 << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
- psp_gfxdrv_command_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
- 0x80000000, 0x80000000, false);
-
- return ret;
-}
-
-static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
-{
- int ret;
- unsigned int psp_gfxdrv_command_reg = 0;
- struct amdgpu_device *adev = psp->adev;
- uint32_t sol_reg;
-
- /* Check sOS sign of life register to confirm sys driver and sOS
- * are already been loaded.
- */
- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
- if (sol_reg)
- return 0;
-
- /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
- 0x80000000, 0x80000000, false);
- if (ret)
- return ret;
-
- memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
- /* Copy Secure OS binary to PSP memory */
- memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
-
- /* Provide the PSP secure OS to bootloader */
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
- (uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 2 << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
- psp_gfxdrv_command_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
- RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
- 0, true);
-
- return ret;
-}
-
-static int
-psp_v11_0_sram_map(struct amdgpu_device *adev,
- unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
- unsigned int *sram_data_reg_offset,
- enum AMDGPU_UCODE_ID ucode_id)
-{
- int ret = 0;
-
- switch (ucode_id) {
-/* TODO: needs to confirm */
-#if 0
- case AMDGPU_UCODE_ID_SMC:
- *sram_offset = 0;
- *sram_addr_reg_offset = 0;
- *sram_data_reg_offset = 0;
- break;
-#endif
-
- case AMDGPU_UCODE_ID_CP_CE:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_PFP:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_ME:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_MEC1:
- *sram_offset = 0x10000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_MEC2:
- *sram_offset = 0x10000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_RLC_G:
- *sram_offset = 0x2000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_SDMA0:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
- break;
-
-/* TODO: needs to confirm */
-#if 0
- case AMDGPU_UCODE_ID_SDMA1:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-
- case AMDGPU_UCODE_ID_UVD:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-
- case AMDGPU_UCODE_ID_VCE:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-#endif
-
- case AMDGPU_UCODE_ID_MAXIMUM:
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static bool psp_v11_0_compare_sram_data(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- enum AMDGPU_UCODE_ID ucode_type)
-{
- int err = 0;
- unsigned int fw_sram_reg_val = 0;
- unsigned int fw_sram_addr_reg_offset = 0;
- unsigned int fw_sram_data_reg_offset = 0;
- unsigned int ucode_size;
- uint32_t *ucode_mem = NULL;
- struct amdgpu_device *adev = psp->adev;
-
- err = psp_v11_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
- &fw_sram_data_reg_offset, ucode_type);
- if (err)
- return false;
-
- WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
-
- ucode_size = ucode->ucode_size;
- ucode_mem = (uint32_t *)ucode->kaddr;
- while (ucode_size) {
- fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
-
- if (*ucode_mem != fw_sram_reg_val)
- return false;
-
- ucode_mem++;
- /* 4 bytes */
- ucode_size -= 4;
- }
-
- return true;
-}
-
-static int psp_v11_0_mode1_reset(struct psp_context *psp)
-{
- int ret;
- uint32_t offset;
- struct amdgpu_device *adev = psp->adev;
-
- offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
-
- ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
-
- if (ret) {
- DRM_INFO("psp is not working correctly before mode1 reset!\n");
- return -EINVAL;
- }
-
- /*send the mode 1 reset command*/
- WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
-
- msleep(500);
-
- offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
-
- ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
-
- if (ret) {
- DRM_INFO("psp mode 1 reset failed!\n");
- return -EINVAL;
- }
-
- DRM_INFO("psp mode1 reset succeed \n");
-
- return 0;
-}
-
/* TODO: Fill in follow functions once PSP firmware interface for XGMI is ready.
* For now, return success and hack the hive_id so high level code can
* start testing
@@ -489,8 +249,6 @@ static int psp_v11_0_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id
static const struct psp_funcs psp_v11_0_funcs = {
.init_microcode = psp_v11_0_init_microcode,
- .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
- .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
.ring_init = psp_ring_init_ring,
.ring_create = psp_ring_create_ring,
.ring_stop = psp_ring_stop_ring,
@@ -498,8 +256,10 @@ static const struct psp_funcs psp_v11_0_funcs = {
.prep_cmd_buf = psp_ring_prep_cmd_buf,
.submit_cmd_buf = psp_ring_submit_cmd_buf,
.support_vmr_ring = psp_ring_support_vmr,
- .compare_sram_data = psp_v11_0_compare_sram_data,
- .mode1_reset = psp_v11_0_mode1_reset,
+ .bootloader_load_sysdrv = psp_cmn_bootloader_load_sysdrv,
+ .bootloader_load_sos = psp_cmn_bootloader_load_sos,
+ .compare_sram_data = psp_cmn_compare_sram_data,
+ .mode1_reset = psp_cmn_mode1_reset,
.xgmi_get_topology_info = psp_v11_0_xgmi_get_topology_info,
.xgmi_set_topology_info = psp_v11_0_xgmi_set_topology_info,
.xgmi_get_hive_id = psp_v11_0_xgmi_get_hive_id,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index b74dd556a573..a013c3ae114b 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -37,6 +37,7 @@
#include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_6_1_offset.h"
#include "psp_ring.h"
+#include "psp_cmn.h"
MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
@@ -119,47 +120,6 @@ static int psp_v3_1_init_microcode(struct psp_context *psp)
return err;
}
-static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
-{
- int ret;
- uint32_t psp_gfxdrv_command_reg = 0;
- struct amdgpu_device *adev = psp->adev;
- uint32_t sol_reg;
-
- /* Check sOS sign of life register to confirm sys driver and sOS
- * are already been loaded.
- */
- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
- if (sol_reg)
- return 0;
-
- /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
- 0x80000000, 0x80000000, false);
- if (ret)
- return ret;
-
- memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
- /* Copy PSP System Driver binary to memory */
- memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size);
-
- /* Provide the sys driver to bootloader */
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
- (uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 1 << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
- psp_gfxdrv_command_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
-
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
- 0x80000000, 0x80000000, false);
-
- return ret;
-}
-
static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
{
int i;
@@ -181,45 +141,14 @@ static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver)
static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
{
- int ret;
- unsigned int psp_gfxdrv_command_reg = 0;
struct amdgpu_device *adev = psp->adev;
- uint32_t sol_reg, ver;
-
- /* Check sOS sign of life register to confirm sys driver and sOS
- * are already been loaded.
- */
- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
- if (sol_reg) {
- psp->sos_fw_version = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
- printk("sos fw version = 0x%x.\n", psp->sos_fw_version);
- return 0;
- }
+ uint32_t ver;
+ int ret;
- /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
- 0x80000000, 0x80000000, false);
+ ret = psp_cmn_bootloader_load_sos(psp);
if (ret)
return ret;
- memset(psp->fw_pri_buf, 0, PSP_1_MEG);
-
- /* Copy Secure OS binary to PSP memory */
- memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size);
-
- /* Provide the PSP secure OS to bootloader */
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
- (uint32_t)(psp->fw_pri_mc_addr >> 20));
- psp_gfxdrv_command_reg = 2 << 16;
- WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
- psp_gfxdrv_command_reg);
-
- /* there might be handshake issue with hardware which needs delay */
- mdelay(20);
- ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
- RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
- 0, true);
-
ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
if (!psp_v3_1_match_version(adev, ver))
DRM_WARN("SOS version doesn't match\n");
@@ -227,128 +156,6 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
return ret;
}
-static int
-psp_v3_1_sram_map(struct amdgpu_device *adev,
- unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
- unsigned int *sram_data_reg_offset,
- enum AMDGPU_UCODE_ID ucode_id)
-{
- int ret = 0;
-
- switch(ucode_id) {
-/* TODO: needs to confirm */
-#if 0
- case AMDGPU_UCODE_ID_SMC:
- *sram_offset = 0;
- *sram_addr_reg_offset = 0;
- *sram_data_reg_offset = 0;
- break;
-#endif
-
- case AMDGPU_UCODE_ID_CP_CE:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_PFP:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_ME:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_MEC1:
- *sram_offset = 0x10000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_CP_MEC2:
- *sram_offset = 0x10000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_RLC_G:
- *sram_offset = 0x2000;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
- break;
-
- case AMDGPU_UCODE_ID_SDMA0:
- *sram_offset = 0x0;
- *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
- *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
- break;
-
-/* TODO: needs to confirm */
-#if 0
- case AMDGPU_UCODE_ID_SDMA1:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-
- case AMDGPU_UCODE_ID_UVD:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-
- case AMDGPU_UCODE_ID_VCE:
- *sram_offset = ;
- *sram_addr_reg_offset = ;
- break;
-#endif
-
- case AMDGPU_UCODE_ID_MAXIMUM:
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static bool psp_v3_1_compare_sram_data(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- enum AMDGPU_UCODE_ID ucode_type)
-{
- int err = 0;
- unsigned int fw_sram_reg_val = 0;
- unsigned int fw_sram_addr_reg_offset = 0;
- unsigned int fw_sram_data_reg_offset = 0;
- unsigned int ucode_size;
- uint32_t *ucode_mem = NULL;
- struct amdgpu_device *adev = psp->adev;
-
- err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
- &fw_sram_data_reg_offset, ucode_type);
- if (err)
- return false;
-
- WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
-
- ucode_size = ucode->ucode_size;
- ucode_mem = (uint32_t *)ucode->kaddr;
- while (ucode_size) {
- fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
-
- if (*ucode_mem != fw_sram_reg_val)
- return false;
-
- ucode_mem++;
- /* 4 bytes */
- ucode_size -= 4;
- }
-
- return true;
-}
-
static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@@ -360,53 +167,19 @@ static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
}
-static int psp_v3_1_mode1_reset(struct psp_context *psp)
-{
- int ret;
- uint32_t offset;
- struct amdgpu_device *adev = psp->adev;
-
- offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
-
- ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
-
- if (ret) {
- DRM_INFO("psp is not working correctly before mode1 reset!\n");
- return -EINVAL;
- }
-
- /*send the mode 1 reset command*/
- WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
-
- msleep(500);
-
- offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
-
- ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
-
- if (ret) {
- DRM_INFO("psp mode 1 reset failed!\n");
- return -EINVAL;
- }
-
- DRM_INFO("psp mode1 reset succeed \n");
-
- return 0;
-}
-
static const struct psp_funcs psp_v3_1_funcs = {
.init_microcode = psp_v3_1_init_microcode,
- .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
- .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
.ring_init = psp_ring_init_ring,
.ring_create = psp_ring_create_ring,
.ring_stop = psp_ring_stop_ring,
.ring_destroy = psp_ring_destroy_ring,
.prep_cmd_buf = psp_ring_prep_cmd_buf,
.submit_cmd_buf = psp_ring_submit_cmd_buf,
- .compare_sram_data = psp_v3_1_compare_sram_data,
+ .bootloader_load_sysdrv = psp_cmn_bootloader_load_sysdrv,
+ .bootloader_load_sos = psp_v3_1_bootloader_load_sos,
+ .compare_sram_data = psp_cmn_compare_sram_data,
.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
- .mode1_reset = psp_v3_1_mode1_reset,
+ .mode1_reset = psp_cmn_mode1_reset,
};
void psp_v3_1_set_psp_funcs(struct psp_context *psp)
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/9] drm/amdgpu: separate the xgmi related APIs
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-01-02 9:21 ` [PATCH 1/9] drm/amdgpu: separate the PSP ring related APIs Evan Quan
2019-01-02 9:21 ` [PATCH 2/9] drm/amdgpu: separate commonly used PSP APIs Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 4/9] drm/amdgpu: separate the tmr " Evan Quan
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
As they are logic independently from other APIs of amdgpu_psp.c.
Change-Id: Idb9d81e15ad4d37e93b95682a07194a94c4849d6
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 182 +--------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 -
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/psp_xgmi.c | 207 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_xgmi.h | 33 ++++
6 files changed, 244 insertions(+), 183 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index fe27d6038da9..30a705db0ef5 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -92,7 +92,8 @@ amdgpu-y += \
psp_v10_0.o \
psp_v11_0.o \
psp_ring.o \
- psp_cmn.o
+ psp_cmn.o \
+ psp_xgmi.o
# add SMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index d1ccc6ea7607..c33ced8371c3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -32,6 +32,7 @@
#include "psp_v3_1.h"
#include "psp_v10_0.h"
#include "psp_v11_0.h"
+#include "psp_xgmi.h"
#define psp_ring_init(psp, type) \
(psp)->funcs->ring_init((psp), (type))
@@ -244,187 +245,6 @@ static int psp_asd_load(struct psp_context *psp)
return ret;
}
-static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
- uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
- uint32_t xgmi_ta_size, uint32_t shared_size)
-{
- cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
- cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
- cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
- cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
-
- cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
- cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
- cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
-}
-
-static int psp_xgmi_init_shared_buf(struct psp_context *psp)
-{
- int ret;
-
- /*
- * Allocate 16k memory aligned to 4k from Frame Buffer (local
- * physical) for xgmi ta <-> Driver
- */
- ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
- PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
- &psp->xgmi_context.xgmi_shared_bo,
- &psp->xgmi_context.xgmi_shared_mc_addr,
- &psp->xgmi_context.xgmi_shared_buf);
-
- return ret;
-}
-
-static int psp_xgmi_load(struct psp_context *psp)
-{
- int ret;
- struct psp_gfx_cmd_resp *cmd;
-
- /*
- * TODO: bypass the loading in sriov for now
- */
- if (amdgpu_sriov_vf(psp->adev))
- return 0;
-
- cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
- if (!cmd)
- return -ENOMEM;
-
- memset(psp->fw_pri_buf, 0, PSP_1_MEG);
- memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
-
- psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
- psp->xgmi_context.xgmi_shared_mc_addr,
- psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
-
- ret = psp_submit_cmd_buf(psp, NULL, cmd,
- psp->fence_buf_mc_addr);
-
- if (!ret) {
- psp->xgmi_context.initialized = 1;
- psp->xgmi_context.session_id = cmd->resp.session_id;
- }
-
- kfree(cmd);
-
- return ret;
-}
-
-static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
- uint32_t xgmi_session_id)
-{
- cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
- cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
-}
-
-static int psp_xgmi_unload(struct psp_context *psp)
-{
- int ret;
- struct psp_gfx_cmd_resp *cmd;
-
- /*
- * TODO: bypass the unloading in sriov for now
- */
- if (amdgpu_sriov_vf(psp->adev))
- return 0;
-
- cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
- if (!cmd)
- return -ENOMEM;
-
- psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
-
- ret = psp_submit_cmd_buf(psp, NULL, cmd,
- psp->fence_buf_mc_addr);
-
- kfree(cmd);
-
- return ret;
-}
-
-static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
- uint32_t ta_cmd_id,
- uint32_t xgmi_session_id)
-{
- cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
- cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
- cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
- /* Note: cmd_invoke_cmd.buf is not used for now */
-}
-
-int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
-{
- int ret;
- struct psp_gfx_cmd_resp *cmd;
-
- /*
- * TODO: bypass the loading in sriov for now
- */
- if (amdgpu_sriov_vf(psp->adev))
- return 0;
-
- cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
- if (!cmd)
- return -ENOMEM;
-
- psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
- psp->xgmi_context.session_id);
-
- ret = psp_submit_cmd_buf(psp, NULL, cmd,
- psp->fence_buf_mc_addr);
-
- kfree(cmd);
-
- return ret;
-}
-
-static int psp_xgmi_terminate(struct psp_context *psp)
-{
- int ret;
-
- if (!psp->xgmi_context.initialized)
- return 0;
-
- ret = psp_xgmi_unload(psp);
- if (ret)
- return ret;
-
- psp->xgmi_context.initialized = 0;
-
- /* free xgmi shared memory */
- amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
- &psp->xgmi_context.xgmi_shared_mc_addr,
- &psp->xgmi_context.xgmi_shared_buf);
-
- return 0;
-}
-
-static int psp_xgmi_initialize(struct psp_context *psp)
-{
- struct ta_xgmi_shared_memory *xgmi_cmd;
- int ret;
-
- if (!psp->xgmi_context.initialized) {
- ret = psp_xgmi_init_shared_buf(psp);
- if (ret)
- return ret;
- }
-
- /* Load XGMI TA */
- ret = psp_xgmi_load(psp);
- if (ret)
- return ret;
-
- /* Initialize XGMI session */
- xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
- memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
- xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
-
- ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
-
- return ret;
-}
-
static int psp_hw_start(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index f4438a5077b6..d65691b988fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -193,7 +193,6 @@ extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
int psp_gpu_reset(struct amdgpu_device *adev);
-int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1dc62ec4e64b..b5c6057dd6ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -34,6 +34,7 @@
#include "nbio/nbio_7_4_offset.h"
#include "psp_ring.h"
#include "psp_cmn.h"
+#include "psp_xgmi.h"
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_xgmi.c b/drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
new file mode 100644
index 000000000000..b3eb93391a46
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "psp_xgmi.h"
+#include "psp_ring.h"
+
+static void psp_prep_xgmi_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ uint64_t xgmi_ta_mc, uint64_t xgmi_mc_shared,
+ uint32_t xgmi_ta_size, uint32_t shared_size)
+{
+ cmd->cmd_id = GFX_CMD_ID_LOAD_TA;
+ cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(xgmi_ta_mc);
+ cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(xgmi_ta_mc);
+ cmd->cmd.cmd_load_ta.app_len = xgmi_ta_size;
+
+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(xgmi_mc_shared);
+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(xgmi_mc_shared);
+ cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
+}
+
+static int psp_xgmi_init_shared_buf(struct psp_context *psp)
+{
+ int ret;
+
+ /*
+ * Allocate 16k memory aligned to 4k from Frame Buffer (local
+ * physical) for xgmi ta <-> Driver
+ */
+ ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+ &psp->xgmi_context.xgmi_shared_bo,
+ &psp->xgmi_context.xgmi_shared_mc_addr,
+ &psp->xgmi_context.xgmi_shared_buf);
+
+ return ret;
+}
+
+static int psp_xgmi_load(struct psp_context *psp)
+{
+ int ret;
+ struct psp_gfx_cmd_resp *cmd;
+
+ /*
+ * TODO: bypass the loading in sriov for now
+ */
+ if (amdgpu_sriov_vf(psp->adev))
+ return 0;
+
+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+ memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
+
+ psp_prep_xgmi_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
+ psp->xgmi_context.xgmi_shared_mc_addr,
+ psp->ta_xgmi_ucode_size, PSP_XGMI_SHARED_MEM_SIZE);
+
+ ret = psp_ring_submit_cmd_buf(psp, NULL, cmd,
+ psp->fence_buf_mc_addr);
+
+ if (!ret) {
+ psp->xgmi_context.initialized = 1;
+ psp->xgmi_context.session_id = cmd->resp.session_id;
+ }
+
+ kfree(cmd);
+
+ return ret;
+}
+
+static void psp_prep_xgmi_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ uint32_t xgmi_session_id)
+{
+ cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
+ cmd->cmd.cmd_unload_ta.session_id = xgmi_session_id;
+}
+
+static int psp_xgmi_unload(struct psp_context *psp)
+{
+ int ret;
+ struct psp_gfx_cmd_resp *cmd;
+
+ /*
+ * TODO: bypass the unloading in sriov for now
+ */
+ if (amdgpu_sriov_vf(psp->adev))
+ return 0;
+
+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ psp_prep_xgmi_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
+
+ ret = psp_ring_submit_cmd_buf(psp, NULL, cmd,
+ psp->fence_buf_mc_addr);
+
+ kfree(cmd);
+
+ return ret;
+}
+
+static void psp_prep_xgmi_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ uint32_t ta_cmd_id,
+ uint32_t xgmi_session_id)
+{
+ cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
+ cmd->cmd.cmd_invoke_cmd.session_id = xgmi_session_id;
+ cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
+ /* Note: cmd_invoke_cmd.buf is not used for now */
+}
+
+int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
+{
+ int ret;
+ struct psp_gfx_cmd_resp *cmd;
+
+ /*
+ * TODO: bypass the loading in sriov for now
+ */
+ if (amdgpu_sriov_vf(psp->adev))
+ return 0;
+
+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ psp_prep_xgmi_ta_invoke_cmd_buf(cmd, ta_cmd_id,
+ psp->xgmi_context.session_id);
+
+ ret = psp_ring_submit_cmd_buf(psp, NULL, cmd,
+ psp->fence_buf_mc_addr);
+
+ kfree(cmd);
+
+ return ret;
+}
+
+int psp_xgmi_terminate(struct psp_context *psp)
+{
+ int ret;
+
+ if (!psp->xgmi_context.initialized)
+ return 0;
+
+ ret = psp_xgmi_unload(psp);
+ if (ret)
+ return ret;
+
+ psp->xgmi_context.initialized = 0;
+
+ /* free xgmi shared memory */
+ amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
+ &psp->xgmi_context.xgmi_shared_mc_addr,
+ &psp->xgmi_context.xgmi_shared_buf);
+
+ return 0;
+}
+
+int psp_xgmi_initialize(struct psp_context *psp)
+{
+ struct ta_xgmi_shared_memory *xgmi_cmd;
+ int ret;
+
+ if (!psp->xgmi_context.initialized) {
+ ret = psp_xgmi_init_shared_buf(psp);
+ if (ret)
+ return ret;
+ }
+
+ /* Load XGMI TA */
+ ret = psp_xgmi_load(psp);
+ if (ret)
+ return ret;
+
+ /* Initialize XGMI session */
+ xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
+ memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
+ xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
+
+ ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
+
+ return ret;
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_xgmi.h b/drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
new file mode 100644
index 000000000000..fb56cbf22c66
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PSP_XGMI_H
+#define __PSP_XGMI_H
+
+#include "amdgpu_psp.h"
+
+int psp_xgmi_initialize(struct psp_context *psp);
+int psp_xgmi_terminate(struct psp_context *psp);
+int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
+
+#endif
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/9] drm/amdgpu: separate the tmr related APIs
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 3/9] drm/amdgpu: separate the xgmi related APIs Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 5/9] drm/amdgpu: separate the asd " Evan Quan
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
As they are logic independently from other APIs of amdgpu_psp.c.
Change-Id: I3c8014caca8250bef6439e857bea1b64b6c1930a
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 60 +-----------------
drivers/gpu/drm/amd/amdgpu/psp_tmr.c | 84 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_tmr.h | 32 ++++++++++
4 files changed, 119 insertions(+), 60 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 30a705db0ef5..99895c6fcd95 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -93,7 +93,8 @@ amdgpu-y += \
psp_v11_0.o \
psp_ring.o \
psp_cmn.o \
- psp_xgmi.o
+ psp_xgmi.o \
+ psp_tmr.o
# add SMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c33ced8371c3..2007e8948cbc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -33,6 +33,7 @@
#include "psp_v10_0.h"
#include "psp_v11_0.h"
#include "psp_xgmi.h"
+#include "psp_tmr.h"
#define psp_ring_init(psp, type) \
(psp)->funcs->ring_init((psp), (type))
@@ -125,65 +126,6 @@ static int psp_sw_fini(void *handle)
return 0;
}
-static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
- struct psp_gfx_cmd_resp *cmd,
- uint64_t tmr_mc, uint32_t size)
-{
- if (psp_support_vmr_ring(psp))
- cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
- else
- cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
- cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
- cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
- cmd->cmd.cmd_setup_tmr.buf_size = size;
-}
-
-/* Set up Trusted Memory Region */
-static int psp_tmr_init(struct psp_context *psp)
-{
- int ret;
-
- /*
- * Allocate 3M memory aligned to 1M from Frame Buffer (local
- * physical).
- *
- * Note: this memory need be reserved till the driver
- * uninitializes.
- */
- ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
- AMDGPU_GEM_DOMAIN_VRAM,
- &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
-
- return ret;
-}
-
-static int psp_tmr_load(struct psp_context *psp)
-{
- int ret;
- struct psp_gfx_cmd_resp *cmd;
-
- cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
- if (!cmd)
- return -ENOMEM;
-
- psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
- DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
- PSP_TMR_SIZE, psp->tmr_mc_addr);
-
- ret = psp_submit_cmd_buf(psp, NULL, cmd,
- psp->fence_buf_mc_addr);
- if (ret)
- goto failed;
-
- kfree(cmd);
-
- return 0;
-
-failed:
- kfree(cmd);
- return ret;
-}
-
static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
uint64_t asd_mc, uint64_t asd_mc_shared,
uint32_t size, uint32_t shared_size)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_tmr.c b/drivers/gpu/drm/amd/amdgpu/psp_tmr.c
new file mode 100644
index 000000000000..fd5fa167a56d
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_tmr.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "psp_tmr.h"
+#include "psp_ring.h"
+
+static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
+ struct psp_gfx_cmd_resp *cmd,
+ uint64_t tmr_mc, uint32_t size)
+{
+ if (psp_ring_support_vmr(psp))
+ cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
+ else
+ cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
+ cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
+ cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
+ cmd->cmd.cmd_setup_tmr.buf_size = size;
+}
+
+/* Set up Trusted Memory Region */
+int psp_tmr_init(struct psp_context *psp)
+{
+ int ret;
+
+ /*
+ * Allocate 3M memory aligned to 1M from Frame Buffer (local
+ * physical).
+ *
+ * Note: this memory need be reserved till the driver
+ * uninitializes.
+ */
+ ret = amdgpu_bo_create_kernel(psp->adev, PSP_TMR_SIZE, 0x100000,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
+
+ return ret;
+}
+
+int psp_tmr_load(struct psp_context *psp)
+{
+ int ret;
+ struct psp_gfx_cmd_resp *cmd;
+
+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, PSP_TMR_SIZE);
+ DRM_INFO("reserve 0x%x from 0x%llx for PSP TMR SIZE\n",
+ PSP_TMR_SIZE, psp->tmr_mc_addr);
+
+ ret = psp_ring_submit_cmd_buf(psp, NULL, cmd,
+ psp->fence_buf_mc_addr);
+ if (ret)
+ goto failed;
+
+ kfree(cmd);
+
+ return 0;
+
+failed:
+ kfree(cmd);
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_tmr.h b/drivers/gpu/drm/amd/amdgpu/psp_tmr.h
new file mode 100644
index 000000000000..35328dd122c6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_tmr.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PSP_TMR_H
+#define __PSP_TMR_H
+
+#include "amdgpu_psp.h"
+
+int psp_tmr_init(struct psp_context *psp);
+int psp_tmr_load(struct psp_context *psp);
+
+#endif
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/9] drm/amdgpu: separate the asd related APIs
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 4/9] drm/amdgpu: separate the tmr " Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 6/9] drm/amdgpu: drop useless PSP APIs and structures Evan Quan
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
As they are logic independently from other APIs of amdgpu_psp.c.
Change-Id: If10aa695214f8df0744a67ee9eb0524d2c5a1ec1
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 62 +-----------------
drivers/gpu/drm/amd/amdgpu/psp_asd.c | 86 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_asd.h | 32 +++++++++
4 files changed, 121 insertions(+), 62 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 99895c6fcd95..ebef9d2cdd61 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -94,7 +94,8 @@ amdgpu-y += \
psp_ring.o \
psp_cmn.o \
psp_xgmi.o \
- psp_tmr.o
+ psp_tmr.o \
+ psp_asd.o
# add SMC block
amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2007e8948cbc..2528fbcad275 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -34,6 +34,7 @@
#include "psp_v11_0.h"
#include "psp_xgmi.h"
#include "psp_tmr.h"
+#include "psp_asd.h"
#define psp_ring_init(psp, type) \
(psp)->funcs->ring_init((psp), (type))
@@ -126,67 +127,6 @@ static int psp_sw_fini(void *handle)
return 0;
}
-static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
- uint64_t asd_mc, uint64_t asd_mc_shared,
- uint32_t size, uint32_t shared_size)
-{
- cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
- cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
- cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
- cmd->cmd.cmd_load_ta.app_len = size;
-
- cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
- cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
- cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
-}
-
-static int psp_asd_init(struct psp_context *psp)
-{
- int ret;
-
- /*
- * Allocate 16k memory aligned to 4k from Frame Buffer (local
- * physical) for shared ASD <-> Driver
- */
- ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
- PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
- &psp->asd_shared_bo,
- &psp->asd_shared_mc_addr,
- &psp->asd_shared_buf);
-
- return ret;
-}
-
-static int psp_asd_load(struct psp_context *psp)
-{
- int ret;
- struct psp_gfx_cmd_resp *cmd;
-
- /* If PSP version doesn't match ASD version, asd loading will be failed.
- * add workaround to bypass it for sriov now.
- * TODO: add version check to make it common
- */
- if (amdgpu_sriov_vf(psp->adev))
- return 0;
-
- cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
- if (!cmd)
- return -ENOMEM;
-
- memset(psp->fw_pri_buf, 0, PSP_1_MEG);
- memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
-
- psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
- psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
-
- ret = psp_submit_cmd_buf(psp, NULL, cmd,
- psp->fence_buf_mc_addr);
-
- kfree(cmd);
-
- return ret;
-}
-
static int psp_hw_start(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_asd.c b/drivers/gpu/drm/amd/amdgpu/psp_asd.c
new file mode 100644
index 000000000000..16263b901a2b
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_asd.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "psp_asd.h"
+#include "psp_ring.h"
+
+static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
+ uint64_t asd_mc, uint64_t asd_mc_shared,
+ uint32_t size, uint32_t shared_size)
+{
+ cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
+ cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
+ cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
+ cmd->cmd.cmd_load_ta.app_len = size;
+
+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
+ cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
+ cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
+}
+
+int psp_asd_init(struct psp_context *psp)
+{
+ int ret;
+
+ /*
+ * Allocate 16k memory aligned to 4k from Frame Buffer (local
+ * physical) for shared ASD <-> Driver
+ */
+ ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
+ PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+ &psp->asd_shared_bo,
+ &psp->asd_shared_mc_addr,
+ &psp->asd_shared_buf);
+
+ return ret;
+}
+
+int psp_asd_load(struct psp_context *psp)
+{
+ int ret;
+ struct psp_gfx_cmd_resp *cmd;
+
+ /* If PSP version doesn't match ASD version, asd loading will be failed.
+ * add workaround to bypass it for sriov now.
+ * TODO: add version check to make it common
+ */
+ if (amdgpu_sriov_vf(psp->adev))
+ return 0;
+
+ cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ memset(psp->fw_pri_buf, 0, PSP_1_MEG);
+ memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
+
+ psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
+ psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
+
+ ret = psp_ring_submit_cmd_buf(psp, NULL, cmd,
+ psp->fence_buf_mc_addr);
+
+ kfree(cmd);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_asd.h b/drivers/gpu/drm/amd/amdgpu/psp_asd.h
new file mode 100644
index 000000000000..8858488f4beb
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_asd.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PSP_ASD_H
+#define __PSP_ASD_H
+
+#include "amdgpu_psp.h"
+
+int psp_asd_init(struct psp_context *psp);
+int psp_asd_load(struct psp_context *psp);
+
+#endif
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/9] drm/amdgpu: drop useless PSP APIs and structures
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 5/9] drm/amdgpu: separate the asd " Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 7/9] drm/amdgpu: check PSP support before adding the ip block Evan Quan
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
Drop those useless APIs and structures.
Change-Id: I1350c0e7ec0b990a1178a0ce92f61e56dc8851b5
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 66 +++++++++----------------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 --
2 files changed, 22 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2528fbcad275..f1ffe04b8c0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -62,19 +62,6 @@
((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
#define psp_mode1_reset(psp) \
((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
-#define amdgpu_psp_check_fw_loading_status(adev, i) \
- (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
-
-static void psp_set_funcs(struct amdgpu_device *adev);
-
-static int psp_early_init(void *handle)
-{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- psp_set_funcs(adev);
-
- return 0;
-}
static int psp_sw_init(void *handle)
{
@@ -166,6 +153,26 @@ static int psp_hw_start(struct psp_context *psp)
return 0;
}
+static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
+ enum AMDGPU_UCODE_ID ucode_type)
+{
+ struct amdgpu_firmware_info *ucode = NULL;
+
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ DRM_INFO("firmware is not loaded by PSP\n");
+ return true;
+ }
+
+ if (!adev->firmware.fw_size)
+ return false;
+
+ ucode = &adev->firmware.ucode[ucode_type];
+ if (!ucode->fw || !ucode->ucode_size)
+ return false;
+
+ return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
+}
+
static int psp_np_fw_load(struct psp_context *psp)
{
int i, ret;
@@ -198,7 +205,7 @@ static int psp_np_fw_load(struct psp_context *psp)
#if 0
/* check if firmware loaded sucessfully */
- if (!amdgpu_psp_check_fw_loading_status(adev, i))
+ if (!psp_check_fw_loading_status(adev, i))
return -EINVAL;
#endif
}
@@ -413,25 +420,6 @@ int psp_gpu_reset(struct amdgpu_device *adev)
return psp_mode1_reset(&adev->psp);
}
-static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
- enum AMDGPU_UCODE_ID ucode_type)
-{
- struct amdgpu_firmware_info *ucode = NULL;
-
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- DRM_INFO("firmware is not loaded by PSP\n");
- return true;
- }
-
- if (!adev->firmware.fw_size)
- return false;
-
- ucode = &adev->firmware.ucode[ucode_type];
- if (!ucode->fw || !ucode->ucode_size)
- return false;
-
- return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
-}
static int psp_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
@@ -447,7 +435,7 @@ static int psp_set_powergating_state(void *handle,
const struct amd_ip_funcs psp_ip_funcs = {
.name = "psp",
- .early_init = psp_early_init,
+ .early_init = NULL,
.late_init = NULL,
.sw_init = psp_sw_init,
.sw_fini = psp_sw_fini,
@@ -463,16 +451,6 @@ const struct amd_ip_funcs psp_ip_funcs = {
.set_powergating_state = psp_set_powergating_state,
};
-static const struct amdgpu_psp_funcs psp_funcs = {
- .check_fw_loading_status = psp_check_fw_loading_status,
-};
-
-static void psp_set_funcs(struct amdgpu_device *adev)
-{
- if (NULL == adev->firmware.funcs)
- adev->firmware.funcs = &psp_funcs;
-}
-
const struct amdgpu_ip_block_version psp_v3_1_ip_block =
{
.type = AMD_IP_BLOCK_TYPE_PSP,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index d65691b988fa..16900d4c8034 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -157,11 +157,6 @@ struct psp_context
struct psp_xgmi_context xgmi_context;
};
-struct amdgpu_psp_funcs {
- bool (*check_fw_loading_status)(struct amdgpu_device *adev,
- enum AMDGPU_UCODE_ID);
-};
-
#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
struct psp_xgmi_node_info {
uint64_t node_id;
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 7/9] drm/amdgpu: check PSP support before adding the ip block
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (5 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 6/9] drm/amdgpu: drop useless PSP APIs and structures Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 8/9] drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable Evan Quan
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
So that we do not need to check this in every internal function.
Change-Id: I5f2665cf60a57b6ae8d04a645f633daf377ae28c
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 24 ------------------------
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 ++++++++-----
2 files changed, 8 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index f1ffe04b8c0f..bf51686bdd0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -86,9 +86,6 @@ static int psp_sw_init(void *handle)
psp->adev = adev;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
- return 0;
-
ret = psp_init_microcode(psp);
if (ret) {
DRM_ERROR("Failed to load psp firmware!\n");
@@ -102,9 +99,6 @@ static int psp_sw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
- return 0;
-
release_firmware(adev->psp.sos_fw);
adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw);
@@ -158,11 +152,6 @@ static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
{
struct amdgpu_firmware_info *ucode = NULL;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- DRM_INFO("firmware is not loaded by PSP\n");
- return true;
- }
-
if (!adev->firmware.fw_size)
return false;
@@ -296,10 +285,6 @@ static int psp_hw_init(void *handle)
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
- return 0;
-
mutex_lock(&adev->firmware.mutex);
/*
* This sequence is just used on hw_init only once, no need on
@@ -329,9 +314,6 @@ static int psp_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
- return 0;
-
if (adev->gmc.xgmi.num_physical_nodes > 1 &&
psp->xgmi_context.initialized == 1)
psp_xgmi_terminate(psp);
@@ -360,9 +342,6 @@ static int psp_suspend(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
- return 0;
-
if (adev->gmc.xgmi.num_physical_nodes > 1 &&
psp->xgmi_context.initialized == 1) {
ret = psp_xgmi_terminate(psp);
@@ -387,9 +366,6 @@ static int psp_resume(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct psp_context *psp = &adev->psp;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
- return 0;
-
DRM_INFO("PSP is resuming...\n");
mutex_lock(&adev->firmware.mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index d5b3f821b8f0..9f162a8a7d9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -535,10 +535,12 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
- if (adev->asic_type == CHIP_VEGA20)
- amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
- else
- amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
+ if (adev->asic_type == CHIP_VEGA20)
+ amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ else
+ amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
+ }
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
if (!amdgpu_sriov_vf(adev))
@@ -560,7 +562,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
- amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
+ if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+ amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 8/9] drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (6 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 7/9] drm/amdgpu: check PSP support before adding the ip block Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 9:21 ` [PATCH 9/9] drm/amdgpu: move psp_funcs related to a more proper place Evan Quan
2019-01-02 10:01 ` [PATCH 0/9] PSP cleanup Christian König
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
As not every generation can support all these PSP sub modules.
Change-Id: I866884e6453a37ff844427eb2d6fd56a91058ebe
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 41 +++++++++++++++++++------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 14 ++++++++-
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 6 ++++
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 8 +++++
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 6 ++++
5 files changed, 64 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index bf51686bdd0f..ecfbf618652a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -32,9 +32,6 @@
#include "psp_v3_1.h"
#include "psp_v10_0.h"
#include "psp_v11_0.h"
-#include "psp_xgmi.h"
-#include "psp_tmr.h"
-#include "psp_asd.h"
#define psp_ring_init(psp, type) \
(psp)->funcs->ring_init((psp), (type))
@@ -50,6 +47,30 @@
(psp)->funcs->submit_cmd_buf((psp), (ucode), (cmd), (fence_mc))
#define psp_support_vmr_ring(psp) \
((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
+#define psp_init_asd(psp) \
+ ((psp)->funcs->asd_init ? (psp)->funcs->asd_init((psp)) : 0)
+#define psp_load_asd(psp) \
+ ((psp)->funcs->asd_load ? (psp)->funcs->asd_load((psp)) : 0)
+#define psp_unload_asd(psp) \
+ ((psp)->funcs->asd_unload ? (psp)->funcs->asd_unload((psp)) : 0)
+#define psp_destory_asd(psp) \
+ ((psp)->funcs->asd_destory ? (psp)->funcs->asd_destory((psp)) : 0)
+#define psp_init_tmr(psp) \
+ ((psp)->funcs->tmr_init ? (psp)->funcs->tmr_init((psp)) : 0)
+#define psp_load_tmr(psp) \
+ ((psp)->funcs->tmr_load ? (psp)->funcs->tmr_load((psp)) : 0)
+#define psp_unload_tmr(psp) \
+ ((psp)->funcs->tmr_unload ? (psp)->funcs->tmr_unload((psp)) : 0)
+#define psp_destory_tmr(psp) \
+ ((psp)->funcs->tmr_destory ? (psp)->funcs->tmr_destory((psp)) : 0)
+#define psp_init_xgmi(psp) \
+ ((psp)->funcs->xgmi_init ? (psp)->funcs->xgmi_init((psp)) : 0)
+#define psp_load_xgmi(psp) \
+ ((psp)->funcs->xgmi_load ? (psp)->funcs->xgmi_load((psp)) : 0)
+#define psp_unload_xgmi(psp) \
+ ((psp)->funcs->xgmi_unload ? (psp)->funcs->xgmi_unload((psp)) : 0)
+#define psp_destory_xgmi(psp) \
+ ((psp)->funcs->xgmi_destory ? (psp)->funcs->xgmi_destory((psp)) : 0)
#define psp_compare_sram_data(psp, ucode, type) \
(psp)->funcs->compare_sram_data((psp), (ucode), (type))
#define psp_init_microcode(psp) \
@@ -127,16 +148,16 @@ static int psp_hw_start(struct psp_context *psp)
if (ret)
return ret;
- ret = psp_tmr_load(psp);
+ ret = psp_load_tmr(psp);
if (ret)
return ret;
- ret = psp_asd_load(psp);
+ ret = psp_load_asd(psp);
if (ret)
return ret;
if (adev->gmc.xgmi.num_physical_nodes > 1) {
- ret = psp_xgmi_initialize(psp);
+ ret = psp_init_xgmi(psp);
/* Warning the XGMI seesion initialize failure
* Instead of stop driver initialization
*/
@@ -245,11 +266,11 @@ static int psp_load_fw(struct amdgpu_device *adev)
if (ret)
goto failed_mem;
- ret = psp_tmr_init(psp);
+ ret = psp_init_tmr(psp);
if (ret)
goto failed_mem;
- ret = psp_asd_init(psp);
+ ret = psp_init_asd(psp);
if (ret)
goto failed_mem;
@@ -316,7 +337,7 @@ static int psp_hw_fini(void *handle)
if (adev->gmc.xgmi.num_physical_nodes > 1 &&
psp->xgmi_context.initialized == 1)
- psp_xgmi_terminate(psp);
+ psp_destory_xgmi(psp);
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
@@ -344,7 +365,7 @@ static int psp_suspend(void *handle)
if (adev->gmc.xgmi.num_physical_nodes > 1 &&
psp->xgmi_context.initialized == 1) {
- ret = psp_xgmi_terminate(psp);
+ ret = psp_destory_xgmi(psp);
if (ret) {
DRM_ERROR("Failed to terminate xgmi ta\n");
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 16900d4c8034..4cc7fd3224f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -77,6 +77,19 @@ struct psp_funcs
int (*submit_cmd_buf)(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr);
+ bool (*support_vmr_ring)(struct psp_context *psp);
+ int (*asd_init)(struct psp_context *psp);
+ int (*asd_load)(struct psp_context *psp);
+ int (*asd_unload)(struct psp_context *psp);
+ int (*asd_destory)(struct psp_context *psp);
+ int (*tmr_init)(struct psp_context *psp);
+ int (*tmr_load)(struct psp_context *psp);
+ int (*tmr_unload)(struct psp_context *psp);
+ int (*tmr_destory)(struct psp_context *psp);
+ int (*xgmi_init)(struct psp_context *psp);
+ int (*xgmi_load)(struct psp_context *psp);
+ int (*xgmi_unload)(struct psp_context *psp);
+ int (*xgmi_destory)(struct psp_context *psp);
bool (*compare_sram_data)(struct psp_context *psp,
struct amdgpu_firmware_info *ucode,
enum AMDGPU_UCODE_ID ucode_type);
@@ -88,7 +101,6 @@ struct psp_funcs
struct psp_xgmi_topology_info *topology);
int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
struct psp_xgmi_topology_info *topology);
- bool (*support_vmr_ring)(struct psp_context *psp);
};
struct psp_xgmi_context {
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 87d9560a52ce..a469ff952045 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -35,6 +35,8 @@
#include "sdma0/sdma0_4_1_offset.h"
#include "psp_ring.h"
#include "psp_cmn.h"
+#include "psp_asd.h"
+#include "psp_tmr.h"
MODULE_FIRMWARE("amdgpu/raven_asd.bin");
MODULE_FIRMWARE("amdgpu/picasso_asd.bin");
@@ -105,6 +107,10 @@ static const struct psp_funcs psp_v10_0_funcs = {
.ring_destroy = psp_ring_destroy_ring,
.prep_cmd_buf = psp_ring_prep_cmd_buf,
.submit_cmd_buf = psp_ring_submit_cmd_buf,
+ .asd_init = psp_asd_init,
+ .asd_load = psp_asd_load,
+ .tmr_init = psp_tmr_init,
+ .tmr_load = psp_tmr_load,
.compare_sram_data = psp_cmn_compare_sram_data,
.mode1_reset = psp_v10_0_mode1_reset,
};
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index b5c6057dd6ed..68ce4ccceec7 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -35,6 +35,8 @@
#include "psp_ring.h"
#include "psp_cmn.h"
#include "psp_xgmi.h"
+#include "psp_asd.h"
+#include "psp_tmr.h"
MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
@@ -257,6 +259,12 @@ static const struct psp_funcs psp_v11_0_funcs = {
.prep_cmd_buf = psp_ring_prep_cmd_buf,
.submit_cmd_buf = psp_ring_submit_cmd_buf,
.support_vmr_ring = psp_ring_support_vmr,
+ .asd_init = psp_asd_init,
+ .asd_load = psp_asd_load,
+ .tmr_init = psp_tmr_init,
+ .tmr_load = psp_tmr_load,
+ .xgmi_init = psp_xgmi_initialize,
+ .xgmi_destory = psp_xgmi_terminate,
.bootloader_load_sysdrv = psp_cmn_bootloader_load_sysdrv,
.bootloader_load_sos = psp_cmn_bootloader_load_sos,
.compare_sram_data = psp_cmn_compare_sram_data,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index a013c3ae114b..8bcbc6bb9333 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -38,6 +38,8 @@
#include "nbio/nbio_6_1_offset.h"
#include "psp_ring.h"
#include "psp_cmn.h"
+#include "psp_asd.h"
+#include "psp_tmr.h"
MODULE_FIRMWARE("amdgpu/vega10_sos.bin");
MODULE_FIRMWARE("amdgpu/vega10_asd.bin");
@@ -175,6 +177,10 @@ static const struct psp_funcs psp_v3_1_funcs = {
.ring_destroy = psp_ring_destroy_ring,
.prep_cmd_buf = psp_ring_prep_cmd_buf,
.submit_cmd_buf = psp_ring_submit_cmd_buf,
+ .asd_init = psp_asd_init,
+ .asd_load = psp_asd_load,
+ .tmr_init = psp_tmr_init,
+ .tmr_load = psp_tmr_load,
.bootloader_load_sysdrv = psp_cmn_bootloader_load_sysdrv,
.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
.compare_sram_data = psp_cmn_compare_sram_data,
--
2.20.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 9/9] drm/amdgpu: move psp_funcs related to a more proper place
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (7 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 8/9] drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable Evan Quan
@ 2019-01-02 9:21 ` Evan Quan
2019-01-02 10:01 ` [PATCH 0/9] PSP cleanup Christian König
9 siblings, 0 replies; 14+ messages in thread
From: Evan Quan @ 2019-01-02 9:21 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, Evan Quan, hawking.zhang-5C7GfCeVMHo
As there is no need to expose these through amdgpu_psp.h.
So, it's better to make them PSP internal used only.
Change-Id: I571be7aae8807f11a6d594be7762306b56403f82
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 96 +++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 73 +++---------------
drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 43 +++++++++++
drivers/gpu/drm/amd/amdgpu/psp_funcs.h | 98 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 2 +-
7 files changed, 197 insertions(+), 119 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_funcs.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index ecfbf618652a..3b46334fa849 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -32,57 +32,8 @@
#include "psp_v3_1.h"
#include "psp_v10_0.h"
#include "psp_v11_0.h"
-
-#define psp_ring_init(psp, type) \
- (psp)->funcs->ring_init((psp), (type))
-#define psp_ring_create(psp, type) \
- (psp)->funcs->ring_create((psp), (type))
-#define psp_ring_stop(psp, type) \
- (psp)->funcs->ring_stop((psp), (type))
-#define psp_ring_destroy(psp, type) \
- ((psp)->funcs->ring_destroy((psp), (type)))
-#define psp_prep_cmd_buf(ucode, cmd) \
- (psp)->funcs->prep_cmd_buf((ucode), (cmd))
-#define psp_submit_cmd_buf(psp, ucode, cmd, fence_mc) \
- (psp)->funcs->submit_cmd_buf((psp), (ucode), (cmd), (fence_mc))
-#define psp_support_vmr_ring(psp) \
- ((psp)->funcs->support_vmr_ring ? (psp)->funcs->support_vmr_ring((psp)) : false)
-#define psp_init_asd(psp) \
- ((psp)->funcs->asd_init ? (psp)->funcs->asd_init((psp)) : 0)
-#define psp_load_asd(psp) \
- ((psp)->funcs->asd_load ? (psp)->funcs->asd_load((psp)) : 0)
-#define psp_unload_asd(psp) \
- ((psp)->funcs->asd_unload ? (psp)->funcs->asd_unload((psp)) : 0)
-#define psp_destory_asd(psp) \
- ((psp)->funcs->asd_destory ? (psp)->funcs->asd_destory((psp)) : 0)
-#define psp_init_tmr(psp) \
- ((psp)->funcs->tmr_init ? (psp)->funcs->tmr_init((psp)) : 0)
-#define psp_load_tmr(psp) \
- ((psp)->funcs->tmr_load ? (psp)->funcs->tmr_load((psp)) : 0)
-#define psp_unload_tmr(psp) \
- ((psp)->funcs->tmr_unload ? (psp)->funcs->tmr_unload((psp)) : 0)
-#define psp_destory_tmr(psp) \
- ((psp)->funcs->tmr_destory ? (psp)->funcs->tmr_destory((psp)) : 0)
-#define psp_init_xgmi(psp) \
- ((psp)->funcs->xgmi_init ? (psp)->funcs->xgmi_init((psp)) : 0)
-#define psp_load_xgmi(psp) \
- ((psp)->funcs->xgmi_load ? (psp)->funcs->xgmi_load((psp)) : 0)
-#define psp_unload_xgmi(psp) \
- ((psp)->funcs->xgmi_unload ? (psp)->funcs->xgmi_unload((psp)) : 0)
-#define psp_destory_xgmi(psp) \
- ((psp)->funcs->xgmi_destory ? (psp)->funcs->xgmi_destory((psp)) : 0)
-#define psp_compare_sram_data(psp, ucode, type) \
- (psp)->funcs->compare_sram_data((psp), (ucode), (type))
-#define psp_init_microcode(psp) \
- ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
-#define psp_bootloader_load_sysdrv(psp) \
- ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
-#define psp_bootloader_load_sos(psp) \
- ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
-#define psp_smu_reload_quirk(psp) \
- ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
-#define psp_mode1_reset(psp) \
- ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
+#include "psp_cmn.h"
+#include "psp_funcs.h"
static int psp_sw_init(void *handle)
{
@@ -417,7 +368,6 @@ int psp_gpu_reset(struct amdgpu_device *adev)
return psp_mode1_reset(&adev->psp);
}
-
static int psp_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
@@ -430,6 +380,48 @@ static int psp_set_powergating_state(void *handle,
return 0;
}
+int psp_xgmi_get_topology_info(struct psp_context *psp,
+ int number_devices, struct psp_xgmi_topology_info *topology)
+{
+ const struct psp_funcs *funcs = (const struct psp_funcs *)(psp->priv);
+
+ if (!funcs->xgmi_get_topology_info)
+ return -EINVAL;
+
+ return funcs->xgmi_get_topology_info(psp, number_devices, topology);
+}
+
+int psp_xgmi_set_topology_info(struct psp_context *psp,
+ int number_devices, struct psp_xgmi_topology_info *topology)
+{
+ const struct psp_funcs *funcs = (const struct psp_funcs *)(psp->priv);
+
+ if (!funcs->xgmi_set_topology_info)
+ return -EINVAL;
+
+ return funcs->xgmi_set_topology_info(psp, number_devices, topology);
+}
+
+int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
+{
+ const struct psp_funcs *funcs = (const struct psp_funcs *)(psp->priv);
+
+ if (!funcs->xgmi_get_hive_id)
+ return -EINVAL;
+
+ return funcs->xgmi_get_hive_id(psp, hive_id);
+}
+
+int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
+{
+ const struct psp_funcs *funcs = (const struct psp_funcs *)(psp->priv);
+
+ if (!funcs->xgmi_get_node_id)
+ return -EINVAL;
+
+ return funcs->xgmi_get_node_id(psp, node_id);
+}
+
const struct amd_ip_funcs psp_ip_funcs = {
.name = "psp",
.early_init = NULL,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 4cc7fd3224f4..4a981defb321 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -35,10 +35,7 @@
#define PSP_XGMI_SHARED_MEM_SIZE 0x4000
#define PSP_1_MEG 0x100000
#define PSP_TMR_SIZE 0x400000
-
-struct psp_context;
-struct psp_xgmi_node_info;
-struct psp_xgmi_topology_info;
+#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
enum psp_ring_type
{
@@ -60,49 +57,6 @@ struct psp_ring
uint32_t ring_size;
};
-struct psp_funcs
-{
- int (*init_microcode)(struct psp_context *psp);
- int (*bootloader_load_sysdrv)(struct psp_context *psp);
- int (*bootloader_load_sos)(struct psp_context *psp);
- int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
- struct psp_gfx_cmd_resp *cmd);
- int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
- int (*ring_create)(struct psp_context *psp,
- enum psp_ring_type ring_type);
- int (*ring_stop)(struct psp_context *psp,
- enum psp_ring_type ring_type);
- int (*ring_destroy)(struct psp_context *psp,
- enum psp_ring_type ring_type);
- int (*submit_cmd_buf)(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr);
- bool (*support_vmr_ring)(struct psp_context *psp);
- int (*asd_init)(struct psp_context *psp);
- int (*asd_load)(struct psp_context *psp);
- int (*asd_unload)(struct psp_context *psp);
- int (*asd_destory)(struct psp_context *psp);
- int (*tmr_init)(struct psp_context *psp);
- int (*tmr_load)(struct psp_context *psp);
- int (*tmr_unload)(struct psp_context *psp);
- int (*tmr_destory)(struct psp_context *psp);
- int (*xgmi_init)(struct psp_context *psp);
- int (*xgmi_load)(struct psp_context *psp);
- int (*xgmi_unload)(struct psp_context *psp);
- int (*xgmi_destory)(struct psp_context *psp);
- bool (*compare_sram_data)(struct psp_context *psp,
- struct amdgpu_firmware_info *ucode,
- enum AMDGPU_UCODE_ID ucode_type);
- bool (*smu_reload_quirk)(struct psp_context *psp);
- int (*mode1_reset)(struct psp_context *psp);
- int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
- int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
- int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
- struct psp_xgmi_topology_info *topology);
- int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
- struct psp_xgmi_topology_info *topology);
-};
-
struct psp_xgmi_context {
uint8_t initialized;
uint32_t session_id;
@@ -117,7 +71,7 @@ struct psp_context
struct psp_ring km_ring;
struct psp_gfx_cmd_resp *cmd;
- const struct psp_funcs *funcs;
+ const void *priv;
/* firmware buffer */
struct amdgpu_bo *fw_pri_bo;
@@ -169,7 +123,6 @@ struct psp_context
struct psp_xgmi_context xgmi_context;
};
-#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
struct psp_xgmi_node_info {
uint64_t node_id;
uint8_t num_hops;
@@ -182,24 +135,16 @@ struct psp_xgmi_topology_info {
struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES];
};
-#define psp_xgmi_get_node_id(psp, node_id) \
- ((psp)->funcs->xgmi_get_node_id ? (psp)->funcs->xgmi_get_node_id((psp), (node_id)) : -EINVAL)
-#define psp_xgmi_get_hive_id(psp, hive_id) \
- ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp), (hive_id)) : -EINVAL)
-#define psp_xgmi_get_topology_info(psp, num_device, topology) \
- ((psp)->funcs->xgmi_get_topology_info ? \
- (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL)
-#define psp_xgmi_set_topology_info(psp, num_device, topology) \
- ((psp)->funcs->xgmi_set_topology_info ? \
- (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL)
-
-extern const struct amd_ip_funcs psp_ip_funcs;
-
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
-
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
+extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
int psp_gpu_reset(struct amdgpu_device *adev);
-extern const struct amdgpu_ip_block_version psp_v11_0_ip_block;
+int psp_xgmi_get_topology_info(struct psp_context *psp,
+ int number_devices, struct psp_xgmi_topology_info *topology);
+int psp_xgmi_set_topology_info(struct psp_context *psp,
+ int number_devices, struct psp_xgmi_topology_info *topology);
+int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id);
+int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_cmn.h b/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
index a1c0ad0bce72..e298fd3b2231 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_cmn.h
@@ -26,6 +26,49 @@
#include "amdgpu_psp.h"
+struct psp_funcs
+{
+ int (*init_microcode)(struct psp_context *psp);
+ int (*bootloader_load_sysdrv)(struct psp_context *psp);
+ int (*bootloader_load_sos)(struct psp_context *psp);
+ int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd);
+ int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
+ int (*ring_create)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+ int (*ring_stop)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+ int (*ring_destroy)(struct psp_context *psp,
+ enum psp_ring_type ring_type);
+ int (*submit_cmd_buf)(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr);
+ bool (*support_vmr_ring)(struct psp_context *psp);
+ int (*asd_init)(struct psp_context *psp);
+ int (*asd_load)(struct psp_context *psp);
+ int (*asd_unload)(struct psp_context *psp);
+ int (*asd_destory)(struct psp_context *psp);
+ int (*tmr_init)(struct psp_context *psp);
+ int (*tmr_load)(struct psp_context *psp);
+ int (*tmr_unload)(struct psp_context *psp);
+ int (*tmr_destory)(struct psp_context *psp);
+ int (*xgmi_init)(struct psp_context *psp);
+ int (*xgmi_load)(struct psp_context *psp);
+ int (*xgmi_unload)(struct psp_context *psp);
+ int (*xgmi_destory)(struct psp_context *psp);
+ bool (*compare_sram_data)(struct psp_context *psp,
+ struct amdgpu_firmware_info *ucode,
+ enum AMDGPU_UCODE_ID ucode_type);
+ bool (*smu_reload_quirk)(struct psp_context *psp);
+ int (*mode1_reset)(struct psp_context *psp);
+ int (*xgmi_get_node_id)(struct psp_context *psp, uint64_t *node_id);
+ int (*xgmi_get_hive_id)(struct psp_context *psp, uint64_t *hive_id);
+ int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices,
+ struct psp_xgmi_topology_info *topology);
+ int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices,
+ struct psp_xgmi_topology_info *topology);
+};
+
int psp_cmn_mode1_reset(struct psp_context *psp);
bool psp_cmn_compare_sram_data(struct psp_context *psp,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_funcs.h b/drivers/gpu/drm/amd/amdgpu/psp_funcs.h
new file mode 100644
index 000000000000..397b4b25a202
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/psp_funcs.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PSP_FUNCS_H
+#define __PSP_FUNCS_H
+
+#include "psp_cmn.h"
+
+#define psp_ring_init(psp, type) \
+ ((const struct psp_funcs *)((psp)->priv))->ring_init((psp), (type))
+#define psp_ring_create(psp, type) \
+ ((const struct psp_funcs *)((psp)->priv))->ring_create((psp), (type))
+#define psp_ring_stop(psp, type) \
+ ((const struct psp_funcs *)((psp)->priv))->ring_stop((psp), (type))
+#define psp_ring_destroy(psp, type) \
+ ((const struct psp_funcs *)((psp)->priv))->ring_destroy((psp), (type))
+#define psp_prep_cmd_buf(ucode, cmd) \
+ ((const struct psp_funcs *)((psp)->priv))->prep_cmd_buf((ucode), (cmd))
+#define psp_submit_cmd_buf(psp, ucode, cmd, fence_mc) \
+ ((const struct psp_funcs *)((psp)->priv))->submit_cmd_buf((psp), (ucode), (cmd), (fence_mc))
+#define psp_support_vmr_ring(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->support_vmr_ring ? \
+ ((const struct psp_funcs *)((psp)->priv))->support_vmr_ring((psp)) : false)
+#define psp_init_asd(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->asd_init ? \
+ ((const struct psp_funcs *)((psp)->priv))->asd_init((psp)) : 0)
+#define psp_load_asd(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->asd_load ? \
+ ((const struct psp_funcs *)((psp)->priv))->asd_load((psp)) : 0)
+#define psp_unload_asd(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->asd_unload ? \
+ ((const struct psp_funcs *)((psp)->priv))->asd_unload((psp)) : 0)
+#define psp_destory_asd(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->asd_destory ? \
+ ((const struct psp_funcs *)((psp)->priv))->asd_destory((psp)) : 0)
+#define psp_init_tmr(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->tmr_init ? \
+ ((const struct psp_funcs *)((psp)->priv))->tmr_init((psp)) : 0)
+#define psp_load_tmr(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->tmr_load ? \
+ ((const struct psp_funcs *)((psp)->priv))->tmr_load((psp)) : 0)
+#define psp_unload_tmr(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->tmr_unload ? \
+ ((const struct psp_funcs *)((psp)->priv))->tmr_unload((psp)) : 0)
+#define psp_destory_tmr(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->tmr_destory ? \
+ ((const struct psp_funcs *)((psp)->priv))->tmr_destory((psp)) : 0)
+#define psp_init_xgmi(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->xgmi_init ? \
+ ((const struct psp_funcs *)((psp)->priv))->xgmi_init((psp)) : 0)
+#define psp_load_xgmi(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->xgmi_load ? \
+ ((const struct psp_funcs *)((psp)->priv))->xgmi_load((psp)) : 0)
+#define psp_unload_xgmi(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->xgmi_unload ? \
+ ((const struct psp_funcs *)((psp)->priv))->xgmi_unload((psp)) : 0)
+#define psp_destory_xgmi(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->xgmi_destory ? \
+ ((const struct psp_funcs *)((psp)->priv))->xgmi_destory((psp)) : 0)
+#define psp_compare_sram_data(psp, ucode, type) \
+ ((const struct psp_funcs *)((psp)->priv))->compare_sram_data((psp), (ucode), (type))
+#define psp_init_microcode(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->init_microcode ? \
+ ((const struct psp_funcs *)((psp)->priv))->init_microcode((psp)) : 0)
+#define psp_bootloader_load_sysdrv(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->bootloader_load_sysdrv ? \
+ ((const struct psp_funcs *)((psp)->priv))->bootloader_load_sysdrv((psp)) : 0)
+#define psp_bootloader_load_sos(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->bootloader_load_sos ? \
+ ((const struct psp_funcs *)((psp)->priv))->bootloader_load_sos((psp)) : 0)
+#define psp_smu_reload_quirk(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->smu_reload_quirk ? \
+ ((const struct psp_funcs *)((psp)->priv))->smu_reload_quirk((psp)) : false)
+#define psp_mode1_reset(psp) \
+ (((const struct psp_funcs *)((psp)->priv))->mode1_reset ? \
+ ((const struct psp_funcs *)((psp)->priv))->mode1_reset((psp)) : false)
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index a469ff952045..7588b73af4a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -117,5 +117,5 @@ static const struct psp_funcs psp_v10_0_funcs = {
void psp_v10_0_set_psp_funcs(struct psp_context *psp)
{
- psp->funcs = &psp_v10_0_funcs;
+ psp->priv = (const void *)&psp_v10_0_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 68ce4ccceec7..c963dcc63d71 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -277,5 +277,5 @@ static const struct psp_funcs psp_v11_0_funcs = {
void psp_v11_0_set_psp_funcs(struct psp_context *psp)
{
- psp->funcs = &psp_v11_0_funcs;
+ psp->priv = (const void *)&psp_v11_0_funcs;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 8bcbc6bb9333..39beb8d589b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -190,5 +190,5 @@ static const struct psp_funcs psp_v3_1_funcs = {
void psp_v3_1_set_psp_funcs(struct psp_context *psp)
{
- psp->funcs = &psp_v3_1_funcs;
+ psp->priv = (const void *)&psp_v3_1_funcs;
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 0/9] PSP cleanup
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (8 preceding siblings ...)
2019-01-02 9:21 ` [PATCH 9/9] drm/amdgpu: move psp_funcs related to a more proper place Evan Quan
@ 2019-01-02 10:01 ` Christian König
[not found] ` <070000a9-9abf-1c23-9294-03e8ff6041dd-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
9 siblings, 1 reply; 14+ messages in thread
From: Christian König @ 2019-01-02 10:01 UTC (permalink / raw)
To: Evan Quan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: alexander.deucher-5C7GfCeVMHo, feifei.xu-5C7GfCeVMHo,
ray.huang-5C7GfCeVMHo, hawking.zhang-5C7GfCeVMHo
The general idea looks good, but can we change the file and symbol
naming a bit?
So far we have named all non-ip version related functions amdgpu_* and
ip related functions ip_version.
E.g. following this xgmi functions should go into amdgpu_xgmi.c and not
psp_xgmi.c
Christian.
Am 02.01.19 um 10:21 schrieb Evan Quan:
> *** BLURB HERE ***
>
> Evan Quan (9):
> drm/amdgpu: separate the PSP ring related APIs
> drm/amdgpu: separate commonly used PSP APIs
> drm/amdgpu: separate the xgmi related APIs
> drm/amdgpu: separate the tmr related APIs
> drm/amdgpu: separate the asd related APIs
> drm/amdgpu: drop useless PSP APIs and structures
> drm/amdgpu: check PSP support before adding the ip block
> drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable
> drm/amdgpu: move psp_funcs related to a more proper place
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 7 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 504 +++-------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 93 +---
> drivers/gpu/drm/amd/amdgpu/psp_asd.c | 86 ++++
> drivers/gpu/drm/amd/amdgpu/psp_asd.h | 32 ++
> drivers/gpu/drm/amd/amdgpu/psp_cmn.c | 289 +++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 84 ++++
> drivers/gpu/drm/amd/amdgpu/psp_funcs.h | 98 +++++
> drivers/gpu/drm/amd/amdgpu/psp_ring.c | 354 ++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_ring.h | 43 ++
> drivers/gpu/drm/amd/amdgpu/psp_tmr.c | 84 ++++
> drivers/gpu/drm/amd/amdgpu/psp_tmr.h | 32 ++
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
> drivers/gpu/drm/amd/amdgpu/psp_xgmi.c | 207 +++++++++
> drivers/gpu/drm/amd/amdgpu/psp_xgmi.h | 33 ++
> drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +-
> 18 files changed, 1493 insertions(+), 1866 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_funcs.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
>
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/9] PSP cleanup
[not found] ` <070000a9-9abf-1c23-9294-03e8ff6041dd-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2019-01-02 10:21 ` Zhang, Hawking
[not found] ` <BYAPR12MB2632A5BB82C2FCE97AF9E7ECFC8C0-ZGDeBxoHBPk+ukJnzp2+RQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 14+ messages in thread
From: Zhang, Hawking @ 2019-01-02 10:21 UTC (permalink / raw)
To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Koenig, Christian
Cc: Deucher, Alexander, Xu, Feifei, Huang, Ray
[-- Attachment #1.1: Type: text/plain, Size: 3514 bytes --]
I'd prefer to keep the old structures: common interfaces in amdgpu_psp.c/.h, and IP specific ones in IP specific file.
No matter it's something related to ASD,TMR, or XGMI.etc, all of these are just communication/handshake jobs between driver and psp fw. Driver plays messenger role with several psp cmd that are shared among ASIC generations. a unified amdgpu_psp.c file is good enough to hold all the common stuffs.
Regards,
Hawking
________________________________
From: Christian K?nig <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Wednesday, January 2, 2019 6:01:56 PM
To: Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander; Xu, Feifei; Huang, Ray; Zhang, Hawking
Subject: Re: [PATCH 0/9] PSP cleanup
The general idea looks good, but can we change the file and symbol
naming a bit?
So far we have named all non-ip version related functions amdgpu_* and
ip related functions ip_version.
E.g. following this xgmi functions should go into amdgpu_xgmi.c and not
psp_xgmi.c
Christian.
Am 02.01.19 um 10:21 schrieb Evan Quan:
> *** BLURB HERE ***
>
> Evan Quan (9):
> drm/amdgpu: separate the PSP ring related APIs
> drm/amdgpu: separate commonly used PSP APIs
> drm/amdgpu: separate the xgmi related APIs
> drm/amdgpu: separate the tmr related APIs
> drm/amdgpu: separate the asd related APIs
> drm/amdgpu: drop useless PSP APIs and structures
> drm/amdgpu: check PSP support before adding the ip block
> drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable
> drm/amdgpu: move psp_funcs related to a more proper place
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 7 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 504 +++-------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 93 +---
> drivers/gpu/drm/amd/amdgpu/psp_asd.c | 86 ++++
> drivers/gpu/drm/amd/amdgpu/psp_asd.h | 32 ++
> drivers/gpu/drm/amd/amdgpu/psp_cmn.c | 289 +++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 84 ++++
> drivers/gpu/drm/amd/amdgpu/psp_funcs.h | 98 +++++
> drivers/gpu/drm/amd/amdgpu/psp_ring.c | 354 ++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_ring.h | 43 ++
> drivers/gpu/drm/amd/amdgpu/psp_tmr.c | 84 ++++
> drivers/gpu/drm/amd/amdgpu/psp_tmr.h | 32 ++
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
> drivers/gpu/drm/amd/amdgpu/psp_xgmi.c | 207 +++++++++
> drivers/gpu/drm/amd/amdgpu/psp_xgmi.h | 33 ++
> drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +-
> 18 files changed, 1493 insertions(+), 1866 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_funcs.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/9] PSP cleanup
[not found] ` <BYAPR12MB2632A5BB82C2FCE97AF9E7ECFC8C0-ZGDeBxoHBPk+ukJnzp2+RQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-01-02 11:59 ` Christian König
[not found] ` <e458fa2c-b541-e757-6a7e-34fbc2e3b8fc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 14+ messages in thread
From: Christian König @ 2019-01-02 11:59 UTC (permalink / raw)
To: Zhang, Hawking, Quan, Evan,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Koenig, Christian
Cc: Deucher, Alexander, Xu, Feifei, Huang, Ray
[-- Attachment #1.1: Type: text/plain, Size: 4662 bytes --]
> I'd prefer to keep the old structures: common interfaces in
> amdgpu_psp.c/.h, and IP specific ones in IP specific file.
>
That works for me as well.
Key take away from the change overview is this:
> > drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
> > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
> > drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
That looks like we can move a good bunch of the per IP specific code
into the common interface. And that is something I really like to see.
No strong opinion if the common code should go into amdgpu_psp.c/h,
amdgpu_xgmi.c/h or amdgpu_psp_xgmi.c/h.
The only restriction I have is that we should just stick with the
existing naming convention.
Christian.
Am 02.01.19 um 11:21 schrieb Zhang, Hawking:
>
> I'd prefer to keep the old structures: common interfaces in
> amdgpu_psp.c/.h, and IP specific ones in IP specific file.
>
>
> No matter it's something related to ASD,TMR, or XGMI.etc, all of these
> are just communication/handshake jobs between driver and psp fw.
> Driver plays messenger role with several psp cmd that are shared among
> ASIC generations. a unified amdgpu_psp.c file is good enough to hold
> all the common stuffs.
>
>
> Regards,
> Hawking
>
> ------------------------------------------------------------------------
> *From:* Christian König <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> *Sent:* Wednesday, January 2, 2019 6:01:56 PM
> *To:* Quan, Evan; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Cc:* Deucher, Alexander; Xu, Feifei; Huang, Ray; Zhang, Hawking
> *Subject:* Re: [PATCH 0/9] PSP cleanup
> The general idea looks good, but can we change the file and symbol
> naming a bit?
>
> So far we have named all non-ip version related functions amdgpu_* and
> ip related functions ip_version.
>
> E.g. following this xgmi functions should go into amdgpu_xgmi.c and not
> psp_xgmi.c
>
> Christian.
>
> Am 02.01.19 um 10:21 schrieb Evan Quan:
> > *** BLURB HERE ***
> >
> > Evan Quan (9):
> > drm/amdgpu: separate the PSP ring related APIs
> > drm/amdgpu: separate commonly used PSP APIs
> > drm/amdgpu: separate the xgmi related APIs
> > drm/amdgpu: separate the tmr related APIs
> > drm/amdgpu: separate the asd related APIs
> > drm/amdgpu: drop useless PSP APIs and structures
> > drm/amdgpu: check PSP support before adding the ip block
> > drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable
> > drm/amdgpu: move psp_funcs related to a more proper place
> >
> > drivers/gpu/drm/amd/amdgpu/Makefile | 7 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 504 +++-------------------
> > drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 93 +---
> > drivers/gpu/drm/amd/amdgpu/psp_asd.c | 86 ++++
> > drivers/gpu/drm/amd/amdgpu/psp_asd.h | 32 ++
> > drivers/gpu/drm/amd/amdgpu/psp_cmn.c | 289 +++++++++++++
> > drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 84 ++++
> > drivers/gpu/drm/amd/amdgpu/psp_funcs.h | 98 +++++
> > drivers/gpu/drm/amd/amdgpu/psp_ring.c | 354 ++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/psp_ring.h | 43 ++
> > drivers/gpu/drm/amd/amdgpu/psp_tmr.c | 84 ++++
> > drivers/gpu/drm/amd/amdgpu/psp_tmr.h | 32 ++
> > drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
> > drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
> > drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
> > drivers/gpu/drm/amd/amdgpu/psp_xgmi.c | 207 +++++++++
> > drivers/gpu/drm/amd/amdgpu/psp_xgmi.h | 33 ++
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +-
> > 18 files changed, 1493 insertions(+), 1866 deletions(-)
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_funcs.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.h
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
> > create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
> >
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 0/9] PSP cleanup
[not found] ` <e458fa2c-b541-e757-6a7e-34fbc2e3b8fc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2019-01-02 12:50 ` Zhang, Hawking
0 siblings, 0 replies; 14+ messages in thread
From: Zhang, Hawking @ 2019-01-02 12:50 UTC (permalink / raw)
To: Koenig, Christian, Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander, Xu, Feifei, Huang, Ray
[-- Attachment #1.1: Type: text/plain, Size: 7514 bytes --]
Yep, We are in progress to move IP specific code into common interfaces. For instance, psp_vXX_get_fw_type/psp_vXX_prep_cmd_buf should be common interfaces, instead of IP specific ones. We’ll see that soon.
And I agree with you that we should stick with the existing naming style. And that’s why I have concern we created some unnecessary files like psp_asd.c/psp_tmr.c/psp_xgmi.c/psp_cmn.c.etc. All of these are just play with common psp gfx cmd. The interfaces are limited and actually do similar jobs.
For ASD, it is common for all the ASICs since from vega10. Although not all the ASICs really used ASD fw, the fact is we’ve already upstreamed ASD fw for vega series and onwards. Therefore, below interfaces seems unnecessary.
+psp_load_asd(psp) \
+ ((psp)->funcs->asd_load ? (psp)->funcs->asd_load((psp)) : 0) #define
+psp_unload_asd(psp) \
+ ((psp)->funcs->asd_unload ? (psp)->funcs->asd_unload((psp)) : 0)
+#define psp_destory_asd(psp) \
+ ((psp)->funcs->asd_destory ? (psp)->funcs->asd_destory((psp)) : 0)
Similar case for TMR. Therefore below interfaces seems unnecessary.
+#define psp_init_tmr(psp) \
+ ((psp)->funcs->tmr_init ? (psp)->funcs->tmr_init((psp)) : 0) #define
+psp_load_tmr(psp) \
+ ((psp)->funcs->tmr_load ? (psp)->funcs->tmr_load((psp)) : 0) #define
+psp_unload_tmr(psp) \
+ ((psp)->funcs->tmr_unload ? (psp)->funcs->tmr_unload((psp)) : 0)
+#define psp_destory_tmr(psp) \
+ ((psp)->funcs->tmr_destory ? (psp)->funcs->tmr_destory((psp)) : 0)
For XGMI, we can use either the “supported” flags in amdgpu_xgmi or num_physical_nodes to decide whether to load the TA or not. Therefore, below interfaces seems unnecessary.
+#define psp_init_xgmi(psp) \
+ ((psp)->funcs->xgmi_init ? (psp)->funcs->xgmi_init((psp)) : 0)
+#define psp_load_xgmi(psp) \
+ ((psp)->funcs->xgmi_load ? (psp)->funcs->xgmi_load((psp)) : 0)
+#define psp_unload_xgmi(psp) \
+ ((psp)->funcs->xgmi_unload ? (psp)->funcs->xgmi_unload((psp)) : 0)
+#define psp_destory_xgmi(psp) \
+ ((psp)->funcs->xgmi_destory ? (psp)->funcs->xgmi_destory((psp)) : 0)
For the upcoming functionalities that need to play with TA ucode, they share exactly the same TA cmd with xgmi. Do we really need to separate them into different psp_xxx source files?
In sum, I’d prefer to stick with the old structures: common interfaces in amdgpu_psp.c/.h, and IP specific ones in IP specific file.
Regards,
Hawking
From: Christian König <ckoenig.leichtzumerken@gmail.com>
Sent: 2019年1月2日 20:00
To: Zhang, Hawking <Hawking.Zhang@amd.com>; Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org; Koenig, Christian <Christian.Koenig@amd.com>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Huang, Ray <Ray.Huang@amd.com>
Subject: Re: [PATCH 0/9] PSP cleanup
I'd prefer to keep the old structures: common interfaces in amdgpu_psp.c/.h, and IP specific ones in IP specific file.
That works for me as well.
Key take away from the change overview is this:
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
That looks like we can move a good bunch of the per IP specific code into the common interface. And that is something I really like to see.
No strong opinion if the common code should go into amdgpu_psp.c/h, amdgpu_xgmi.c/h or amdgpu_psp_xgmi.c/h.
The only restriction I have is that we should just stick with the existing naming convention.
Christian.
Am 02.01.19 um 11:21 schrieb Zhang, Hawking:
I'd prefer to keep the old structures: common interfaces in amdgpu_psp.c/.h, and IP specific ones in IP specific file.
No matter it's something related to ASD,TMR, or XGMI.etc, all of these are just communication/handshake jobs between driver and psp fw. Driver plays messenger role with several psp cmd that are shared among ASIC generations. a unified amdgpu_psp.c file is good enough to hold all the common stuffs.
Regards,
Hawking
[X]
From: Christian König <ckoenig.leichtzumerken@gmail.com><mailto:ckoenig.leichtzumerken@gmail.com>
Sent: Wednesday, January 2, 2019 6:01:56 PM
To: Quan, Evan; amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander; Xu, Feifei; Huang, Ray; Zhang, Hawking
Subject: Re: [PATCH 0/9] PSP cleanup
The general idea looks good, but can we change the file and symbol
naming a bit?
So far we have named all non-ip version related functions amdgpu_* and
ip related functions ip_version.
E.g. following this xgmi functions should go into amdgpu_xgmi.c and not
psp_xgmi.c
Christian.
Am 02.01.19 um 10:21 schrieb Evan Quan:
> *** BLURB HERE ***
>
> Evan Quan (9):
> drm/amdgpu: separate the PSP ring related APIs
> drm/amdgpu: separate commonly used PSP APIs
> drm/amdgpu: separate the xgmi related APIs
> drm/amdgpu: separate the tmr related APIs
> drm/amdgpu: separate the asd related APIs
> drm/amdgpu: drop useless PSP APIs and structures
> drm/amdgpu: check PSP support before adding the ip block
> drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable
> drm/amdgpu: move psp_funcs related to a more proper place
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 7 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 504 +++-------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 93 +---
> drivers/gpu/drm/amd/amdgpu/psp_asd.c | 86 ++++
> drivers/gpu/drm/amd/amdgpu/psp_asd.h | 32 ++
> drivers/gpu/drm/amd/amdgpu/psp_cmn.c | 289 +++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_cmn.h | 84 ++++
> drivers/gpu/drm/amd/amdgpu/psp_funcs.h | 98 +++++
> drivers/gpu/drm/amd/amdgpu/psp_ring.c | 354 ++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/psp_ring.h | 43 ++
> drivers/gpu/drm/amd/amdgpu/psp_tmr.c | 84 ++++
> drivers/gpu/drm/amd/amdgpu/psp_tmr.h | 32 ++
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 381 +----------------
> drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 539 +-----------------------
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 480 +--------------------
> drivers/gpu/drm/amd/amdgpu/psp_xgmi.c | 207 +++++++++
> drivers/gpu/drm/amd/amdgpu/psp_xgmi.h | 33 ++
> drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +-
> 18 files changed, 1493 insertions(+), 1866 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_asd.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_cmn.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_funcs.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_ring.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_tmr.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_xgmi.h
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-01-02 12:50 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-02 9:21 [PATCH 0/9] PSP cleanup Evan Quan
[not found] ` <20190102092141.2196-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-01-02 9:21 ` [PATCH 1/9] drm/amdgpu: separate the PSP ring related APIs Evan Quan
2019-01-02 9:21 ` [PATCH 2/9] drm/amdgpu: separate commonly used PSP APIs Evan Quan
2019-01-02 9:21 ` [PATCH 3/9] drm/amdgpu: separate the xgmi related APIs Evan Quan
2019-01-02 9:21 ` [PATCH 4/9] drm/amdgpu: separate the tmr " Evan Quan
2019-01-02 9:21 ` [PATCH 5/9] drm/amdgpu: separate the asd " Evan Quan
2019-01-02 9:21 ` [PATCH 6/9] drm/amdgpu: drop useless PSP APIs and structures Evan Quan
2019-01-02 9:21 ` [PATCH 7/9] drm/amdgpu: check PSP support before adding the ip block Evan Quan
2019-01-02 9:21 ` [PATCH 8/9] drm/amdgpu: make PSP sub modules(ASD/XGMI/TMR) support configurable Evan Quan
2019-01-02 9:21 ` [PATCH 9/9] drm/amdgpu: move psp_funcs related to a more proper place Evan Quan
2019-01-02 10:01 ` [PATCH 0/9] PSP cleanup Christian König
[not found] ` <070000a9-9abf-1c23-9294-03e8ff6041dd-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-01-02 10:21 ` Zhang, Hawking
[not found] ` <BYAPR12MB2632A5BB82C2FCE97AF9E7ECFC8C0-ZGDeBxoHBPk+ukJnzp2+RQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-01-02 11:59 ` Christian König
[not found] ` <e458fa2c-b541-e757-6a7e-34fbc2e3b8fc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-01-02 12:50 ` Zhang, Hawking
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