[PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add firmware checking

[PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add firmware checking

[Emily Deng]

Refine the patch 1, and the lock about invalidate_lock.

Unify bare metal and sriov, and add firmware checking for
reg write and reg wait unify command.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 59 ++++++++++++++++++++++++++++++++-
 2 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 53e9e2a..f172e92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -274,6 +274,8 @@ struct amdgpu_gfx {
 	uint32_t			rlc_srls_feature_version;
 	uint32_t			mec_feature_version;
 	uint32_t			mec2_feature_version;
+	bool				mec_fw_write_wait;
+	bool				me_fw_write_wait;
 	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
 	unsigned			num_gfx_rings;
 	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 4e1e1a0..0cba430 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -482,6 +482,59 @@ static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 }
 
+static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
+{
+	adev->gfx.me_fw_write_wait = false;
+	adev->gfx.mec_fw_write_wait = false;
+
+	switch (adev->asic_type) {
+	case CHIP_VEGA10:
+		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
+		    (adev->gfx.me_feature_version >= 42) &&
+		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
+		    (adev->gfx.pfp_feature_version >= 42))
+			adev->gfx.me_fw_write_wait = true;
+
+		if ((adev->gfx.mec_fw_version >=  0x00000193) &&
+		    (adev->gfx.mec_feature_version >= 42))
+			adev->gfx.mec_fw_write_wait = true;
+		break;
+	case CHIP_VEGA12:
+		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
+		    (adev->gfx.me_feature_version >= 44) &&
+		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
+		    (adev->gfx.pfp_feature_version >= 44))
+			adev->gfx.me_fw_write_wait = true;
+
+		if ((adev->gfx.mec_fw_version >=  0x00000196) &&
+		    (adev->gfx.mec_feature_version >= 44))
+			adev->gfx.mec_fw_write_wait = true;
+		break;
+	case CHIP_VEGA20:
+		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
+		    (adev->gfx.me_feature_version >= 44) &&
+		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
+		    (adev->gfx.pfp_feature_version >= 44))
+			adev->gfx.me_fw_write_wait = true;
+
+		if ((adev->gfx.mec_fw_version >=  0x00000197) &&
+		    (adev->gfx.mec_feature_version >= 44))
+			adev->gfx.mec_fw_write_wait = true;
+		break;
+	case CHIP_RAVEN:
+		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
+		    (adev->gfx.me_feature_version >= 42) &&
+		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
+		    (adev->gfx.pfp_feature_version >= 42))
+			adev->gfx.me_fw_write_wait = true;
+
+		if ((adev->gfx.mec_fw_version >=  0x00000192) &&
+		    (adev->gfx.mec_feature_version >= 42))
+			adev->gfx.mec_fw_write_wait = true;
+		break;
+	}
+}
+
 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 {
 	const char *chip_name;
@@ -716,6 +769,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 	}
 
 out:
+	gfx_v9_0_check_fw_write_wait(adev);
 	if (err) {
 		dev_err(adev->dev,
 			"gfx9: Failed to load firmware \"%s\"\n",
@@ -4353,8 +4407,11 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
 						  uint32_t ref, uint32_t mask)
 {
 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
+	struct amdgpu_device *adev = ring->adev;
+	bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
+		adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
 
-	if (amdgpu_sriov_vf(ring->adev))
+	if (fw_version_ok)
 		gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
 				      ref, mask, 0x20);
 	else
-- 
2.7.4

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[PATCH v2 2/2] drm/amdgpu: use kiq to do invalidate tlb

[Emily Deng]

To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.

v2:
Refine the invalidate lock position.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h      |  4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c |  3 --
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 74 +++++++++++++++++++++++++++++---
 3 files changed, 71 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 6265b88..19ef7711 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -212,6 +212,10 @@ enum amdgpu_kiq_irq {
 	AMDGPU_CP_KIQ_IRQ_LAST
 };
 
+#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */
+#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */
+#define MAX_KIQ_REG_TRY 20
+
 int amdgpu_device_ip_set_clockgating_state(void *dev,
 					   enum amd_ip_block_type block_type,
 					   enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 21adb1b6..3885636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -22,9 +22,6 @@
  */
 
 #include "amdgpu.h"
-#define MAX_KIQ_REG_WAIT	5000 /* in usecs, 5ms */
-#define MAX_KIQ_REG_BAILOUT_INTERVAL	5 /* in msecs, 5ms */
-#define MAX_KIQ_REG_TRY 20
 
 uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index ed467de..0bf8439 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -311,6 +311,58 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
 	return req;
 }
 
+signed long  amdgpu_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
+						  uint32_t reg0, uint32_t reg1,
+						  uint32_t ref, uint32_t mask)
+{
+	signed long r, cnt = 0;
+	unsigned long flags;
+	uint32_t seq;
+	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+	struct amdgpu_ring *ring = &kiq->ring;
+
+	if (!ring->ready)
+		return -EINVAL;
+
+	spin_lock_irqsave(&kiq->ring_lock, flags);
+
+	amdgpu_ring_alloc(ring, 32);
+	amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
+					    ref, mask);
+	amdgpu_fence_emit_polling(ring, &seq);
+	amdgpu_ring_commit(ring);
+	spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+	r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+	/* don't wait anymore for gpu reset case because this way may
+	 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+	 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+	 * never return if we keep waiting in virt_kiq_rreg, which cause
+	 * gpu_recover() hang there.
+	 *
+	 * also don't wait anymore for IRQ context
+	 * */
+	if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+		goto failed_kiq;
+
+	might_sleep();
+
+	while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+		msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+	}
+
+	if (cnt > MAX_KIQ_REG_TRY)
+		goto failed_kiq;
+
+	return 0;
+
+failed_kiq:
+	pr_err("failed to invalidate tlb with kiq\n");
+	return r;
+}
+
 /*
  * GART
  * VMID 0 is the physical GPU addresses as used by the kernel.
@@ -332,13 +384,19 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 	/* Use register 17 for GART */
 	const unsigned eng = 17;
 	unsigned i, j;
-
-	spin_lock(&adev->gmc.invalidate_lock);
+	int r;
 
 	for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
 		struct amdgpu_vmhub *hub = &adev->vmhub[i];
 		u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
 
+		r = amdgpu_kiq_reg_write_reg_wait(adev, hub->vm_inv_eng0_req + eng,
+			hub->vm_inv_eng0_ack + eng, tmp, 1 << vmid);
+		if (!r)
+			continue;
+
+		spin_lock(&adev->gmc.invalidate_lock);
+
 		WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
 
 		/* Busy wait for ACK.*/
@@ -349,8 +407,10 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 				break;
 			cpu_relax();
 		}
-		if (j < 100)
+		if (j < 100) {
+			spin_unlock(&adev->gmc.invalidate_lock);
 			continue;
+		}
 
 		/* Wait for ACK with a delay.*/
 		for (j = 0; j < adev->usec_timeout; j++) {
@@ -360,13 +420,13 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev,
 				break;
 			udelay(1);
 		}
-		if (j < adev->usec_timeout)
+		if (j < adev->usec_timeout) {
+			spin_unlock(&adev->gmc.invalidate_lock);
 			continue;
-
+		}
+		spin_unlock(&adev->gmc.invalidate_lock);
 		DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 	}
-
-	spin_unlock(&adev->gmc.invalidate_lock);
 }
 
 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
-- 
2.7.4

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Re: [PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add firmware checking

[Christian König]

Am 17.08.2018 um 07:40 schrieb Emily Deng:
> Refine the patch 1, and the lock about invalidate_lock.
>
> Unify bare metal and sriov, and add firmware checking for
> reg write and reg wait unify command.
>
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>

Acked-by: Christian König <christian.koenig@amd.com> for this one 
because I can't verify the firmware numbers.

Reviewed-by: Christian König <christian.koenig@amd.com> for patch #2.

I can give the two patches a testing on bare metal Vega10 and Raven 
later today if nobody beats me on this.

Thanks for the patience, that looks *much* better now that we have an 
unified code path,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 ++
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 59 ++++++++++++++++++++++++++++++++-
>   2 files changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> index 53e9e2a..f172e92 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> @@ -274,6 +274,8 @@ struct amdgpu_gfx {
>   	uint32_t			rlc_srls_feature_version;
>   	uint32_t			mec_feature_version;
>   	uint32_t			mec2_feature_version;
> +	bool				mec_fw_write_wait;
> +	bool				me_fw_write_wait;
>   	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
>   	unsigned			num_gfx_rings;
>   	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 4e1e1a0..0cba430 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -482,6 +482,59 @@ static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
>   			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
>   }
>   
> +static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
> +{
> +	adev->gfx.me_fw_write_wait = false;
> +	adev->gfx.mec_fw_write_wait = false;
> +
> +	switch (adev->asic_type) {
> +	case CHIP_VEGA10:
> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> +		    (adev->gfx.me_feature_version >= 42) &&
> +		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
> +		    (adev->gfx.pfp_feature_version >= 42))
> +			adev->gfx.me_fw_write_wait = true;
> +
> +		if ((adev->gfx.mec_fw_version >=  0x00000193) &&
> +		    (adev->gfx.mec_feature_version >= 42))
> +			adev->gfx.mec_fw_write_wait = true;
> +		break;
> +	case CHIP_VEGA12:
> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> +		    (adev->gfx.me_feature_version >= 44) &&
> +		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
> +		    (adev->gfx.pfp_feature_version >= 44))
> +			adev->gfx.me_fw_write_wait = true;
> +
> +		if ((adev->gfx.mec_fw_version >=  0x00000196) &&
> +		    (adev->gfx.mec_feature_version >= 44))
> +			adev->gfx.mec_fw_write_wait = true;
> +		break;
> +	case CHIP_VEGA20:
> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> +		    (adev->gfx.me_feature_version >= 44) &&
> +		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
> +		    (adev->gfx.pfp_feature_version >= 44))
> +			adev->gfx.me_fw_write_wait = true;
> +
> +		if ((adev->gfx.mec_fw_version >=  0x00000197) &&
> +		    (adev->gfx.mec_feature_version >= 44))
> +			adev->gfx.mec_fw_write_wait = true;
> +		break;
> +	case CHIP_RAVEN:
> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> +		    (adev->gfx.me_feature_version >= 42) &&
> +		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
> +		    (adev->gfx.pfp_feature_version >= 42))
> +			adev->gfx.me_fw_write_wait = true;
> +
> +		if ((adev->gfx.mec_fw_version >=  0x00000192) &&
> +		    (adev->gfx.mec_feature_version >= 42))
> +			adev->gfx.mec_fw_write_wait = true;
> +		break;
> +	}
> +}
> +
>   static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>   {
>   	const char *chip_name;
> @@ -716,6 +769,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>   	}
>   
>   out:
> +	gfx_v9_0_check_fw_write_wait(adev);
>   	if (err) {
>   		dev_err(adev->dev,
>   			"gfx9: Failed to load firmware \"%s\"\n",
> @@ -4353,8 +4407,11 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
>   						  uint32_t ref, uint32_t mask)
>   {
>   	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> +	struct amdgpu_device *adev = ring->adev;
> +	bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
> +		adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
>   
> -	if (amdgpu_sriov_vf(ring->adev))
> +	if (fw_version_ok)
>   		gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
>   				      ref, mask, 0x20);
>   	else

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RE: [PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add firmware checking

[Deng, Emily]

>-----Original Message-----
>From: Christian König <ckoenig.leichtzumerken@gmail.com>
>Sent: Friday, August 17, 2018 3:23 PM
>To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add
>firmware checking
>
>Am 17.08.2018 um 07:40 schrieb Emily Deng:
>> Refine the patch 1, and the lock about invalidate_lock.
>>
>> Unify bare metal and sriov, and add firmware checking for reg write
>> and reg wait unify command.
>>
>> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
>
>Acked-by: Christian König <christian.koenig@amd.com> for this one because I
>can't verify the firmware numbers.
>
>Reviewed-by: Christian König <christian.koenig@amd.com> for patch #2.
>
>I can give the two patches a testing on bare metal Vega10 and Raven later today
>if nobody beats me on this.
>
>Thanks for the patience, that looks *much* better now that we have an unified
>code path, Christian.
Also thanks your help to review these, I am waiting the test result on bare metal from you or someone else, and then push the patches.
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 ++
>>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 59
>++++++++++++++++++++++++++++++++-
>>   2 files changed, 60 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> index 53e9e2a..f172e92 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
>> @@ -274,6 +274,8 @@ struct amdgpu_gfx {
>>   	uint32_t			rlc_srls_feature_version;
>>   	uint32_t			mec_feature_version;
>>   	uint32_t			mec2_feature_version;
>> +	bool				mec_fw_write_wait;
>> +	bool				me_fw_write_wait;
>>   	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
>>   	unsigned			num_gfx_rings;
>>   	struct amdgpu_ring
>	compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 4e1e1a0..0cba430 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -482,6 +482,59 @@ static void gfx_v9_0_init_rlc_ext_microcode(struct
>amdgpu_device *adev)
>>   			le32_to_cpu(rlc_hdr-
>>reg_list_format_direct_reg_list_length);
>>   }
>>
>> +static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
>> +{
>> +	adev->gfx.me_fw_write_wait = false;
>> +	adev->gfx.mec_fw_write_wait = false;
>> +
>> +	switch (adev->asic_type) {
>> +	case CHIP_VEGA10:
>> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
>> +		    (adev->gfx.me_feature_version >= 42) &&
>> +		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
>> +		    (adev->gfx.pfp_feature_version >= 42))
>> +			adev->gfx.me_fw_write_wait = true;
>> +
>> +		if ((adev->gfx.mec_fw_version >=  0x00000193) &&
>> +		    (adev->gfx.mec_feature_version >= 42))
>> +			adev->gfx.mec_fw_write_wait = true;
>> +		break;
>> +	case CHIP_VEGA12:
>> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
>> +		    (adev->gfx.me_feature_version >= 44) &&
>> +		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
>> +		    (adev->gfx.pfp_feature_version >= 44))
>> +			adev->gfx.me_fw_write_wait = true;
>> +
>> +		if ((adev->gfx.mec_fw_version >=  0x00000196) &&
>> +		    (adev->gfx.mec_feature_version >= 44))
>> +			adev->gfx.mec_fw_write_wait = true;
>> +		break;
>> +	case CHIP_VEGA20:
>> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
>> +		    (adev->gfx.me_feature_version >= 44) &&
>> +		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
>> +		    (adev->gfx.pfp_feature_version >= 44))
>> +			adev->gfx.me_fw_write_wait = true;
>> +
>> +		if ((adev->gfx.mec_fw_version >=  0x00000197) &&
>> +		    (adev->gfx.mec_feature_version >= 44))
>> +			adev->gfx.mec_fw_write_wait = true;
>> +		break;
>> +	case CHIP_RAVEN:
>> +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
>> +		    (adev->gfx.me_feature_version >= 42) &&
>> +		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
>> +		    (adev->gfx.pfp_feature_version >= 42))
>> +			adev->gfx.me_fw_write_wait = true;
>> +
>> +		if ((adev->gfx.mec_fw_version >=  0x00000192) &&
>> +		    (adev->gfx.mec_feature_version >= 42))
>> +			adev->gfx.mec_fw_write_wait = true;
>> +		break;
>> +	}
>> +}
>> +
>>   static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
>>   {
>>   	const char *chip_name;
>> @@ -716,6 +769,7 @@ static int gfx_v9_0_init_microcode(struct
>amdgpu_device *adev)
>>   	}
>>
>>   out:
>> +	gfx_v9_0_check_fw_write_wait(adev);
>>   	if (err) {
>>   		dev_err(adev->dev,
>>   			"gfx9: Failed to load firmware \"%s\"\n", @@ -4353,8
>+4407,11 @@
>> static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
>>   						  uint32_t ref, uint32_t mask)
>>   {
>>   	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
>> +	struct amdgpu_device *adev = ring->adev;
>> +	bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
>> +		adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
>>
>> -	if (amdgpu_sriov_vf(ring->adev))
>> +	if (fw_version_ok)
>>   		gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
>>   				      ref, mask, 0x20);
>>   	else

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RE: [PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add firmware checking

[Zhu, Rex]

I have tested the patches on Rv/Vega10/Vega12.

Series is:
Reviewed-and-Tested-by: Rex Zhu <Rex.Zhu@amd.com>

Best Regards
Rex
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Christian König
> Sent: Friday, August 17, 2018 3:23 PM
> To: Deng, Emily <Emily.Deng@amd.com>; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2 1/2] drm/amdgpu: Remove the sriov checking and add
> firmware checking
> 
> Am 17.08.2018 um 07:40 schrieb Emily Deng:
> > Refine the patch 1, and the lock about invalidate_lock.
> >
> > Unify bare metal and sriov, and add firmware checking for reg write
> > and reg wait unify command.
> >
> > Signed-off-by: Emily Deng <Emily.Deng@amd.com>
> 
> Acked-by: Christian König <christian.koenig@amd.com> for this one because I
> can't verify the firmware numbers.
> 
> Reviewed-by: Christian König <christian.koenig@amd.com> for patch #2.
> 
> I can give the two patches a testing on bare metal Vega10 and Raven later
> today if nobody beats me on this.
> 
> Thanks for the patience, that looks *much* better now that we have an
> unified code path, Christian.
> 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  2 ++
> >   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 59
> ++++++++++++++++++++++++++++++++-
> >   2 files changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index 53e9e2a..f172e92 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -274,6 +274,8 @@ struct amdgpu_gfx {
> >   	uint32_t			rlc_srls_feature_version;
> >   	uint32_t			mec_feature_version;
> >   	uint32_t			mec2_feature_version;
> > +	bool				mec_fw_write_wait;
> > +	bool				me_fw_write_wait;
> >   	struct amdgpu_ring
> 	gfx_ring[AMDGPU_MAX_GFX_RINGS];
> >   	unsigned			num_gfx_rings;
> >   	struct amdgpu_ring
> 	compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 4e1e1a0..0cba430 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -482,6 +482,59 @@ static void gfx_v9_0_init_rlc_ext_microcode(struct
> amdgpu_device *adev)
> >   			le32_to_cpu(rlc_hdr-
> >reg_list_format_direct_reg_list_length);
> >   }
> >
> > +static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
> > +{
> > +	adev->gfx.me_fw_write_wait = false;
> > +	adev->gfx.mec_fw_write_wait = false;
> > +
> > +	switch (adev->asic_type) {
> > +	case CHIP_VEGA10:
> > +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> > +		    (adev->gfx.me_feature_version >= 42) &&
> > +		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
> > +		    (adev->gfx.pfp_feature_version >= 42))
> > +			adev->gfx.me_fw_write_wait = true;
> > +
> > +		if ((adev->gfx.mec_fw_version >=  0x00000193) &&
> > +		    (adev->gfx.mec_feature_version >= 42))
> > +			adev->gfx.mec_fw_write_wait = true;
> > +		break;
> > +	case CHIP_VEGA12:
> > +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> > +		    (adev->gfx.me_feature_version >= 44) &&
> > +		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
> > +		    (adev->gfx.pfp_feature_version >= 44))
> > +			adev->gfx.me_fw_write_wait = true;
> > +
> > +		if ((adev->gfx.mec_fw_version >=  0x00000196) &&
> > +		    (adev->gfx.mec_feature_version >= 44))
> > +			adev->gfx.mec_fw_write_wait = true;
> > +		break;
> > +	case CHIP_VEGA20:
> > +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> > +		    (adev->gfx.me_feature_version >= 44) &&
> > +		    (adev->gfx.pfp_fw_version >=  0x000000b2) &&
> > +		    (adev->gfx.pfp_feature_version >= 44))
> > +			adev->gfx.me_fw_write_wait = true;
> > +
> > +		if ((adev->gfx.mec_fw_version >=  0x00000197) &&
> > +		    (adev->gfx.mec_feature_version >= 44))
> > +			adev->gfx.mec_fw_write_wait = true;
> > +		break;
> > +	case CHIP_RAVEN:
> > +		if ((adev->gfx.me_fw_version >= 0x0000009c) &&
> > +		    (adev->gfx.me_feature_version >= 42) &&
> > +		    (adev->gfx.pfp_fw_version >=  0x000000b1) &&
> > +		    (adev->gfx.pfp_feature_version >= 42))
> > +			adev->gfx.me_fw_write_wait = true;
> > +
> > +		if ((adev->gfx.mec_fw_version >=  0x00000192) &&
> > +		    (adev->gfx.mec_feature_version >= 42))
> > +			adev->gfx.mec_fw_write_wait = true;
> > +		break;
> > +	}
> > +}
> > +
> >   static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
> >   {
> >   	const char *chip_name;
> > @@ -716,6 +769,7 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
> >   	}
> >
> >   out:
> > +	gfx_v9_0_check_fw_write_wait(adev);
> >   	if (err) {
> >   		dev_err(adev->dev,
> >   			"gfx9: Failed to load firmware \"%s\"\n", @@ -4353,8
> +4407,11 @@
> > static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring
> *ring,
> >   						  uint32_t ref, uint32_t mask)
> >   {
> >   	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
> > +	struct amdgpu_device *adev = ring->adev;
> > +	bool fw_version_ok = (ring->funcs->type ==
> AMDGPU_RING_TYPE_GFX) ?
> > +		adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
> >
> > -	if (amdgpu_sriov_vf(ring->adev))
> > +	if (fw_version_ok)
> >   		gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
> >   				      ref, mask, 0x20);
> >   	else
> 
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